Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	982781	0	0
ctrl_rd_A	2147483647	19947	0	0
intr_enable_rd_A	2147483647	18447	0	0
ovrd_rd_A	2147483647	19675	0	0
timeout_ctrl_rd_A	2147483647	19705	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	982781	0	0
T20	463823	0	0	0
T23	0	7227	0	0
T27	336431	0	0	0
T32	213228	8860	0	0
T33	135626	6488	0	0
T34	0	8461	0	0
T35	113999	0	0	0
T38	0	5770	0	0
T39	0	5646	0	0
T40	0	8152	0	0
T41	0	7545	0	0
T42	0	3534	0	0
T43	0	12601	0	0
T44	24056	0	0	0
T45	197996	0	0	0
T46	36340	0	0	0
T47	5217	0	0	0
T48	269506	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	19947	0	0
T39	165499	264	0	0
T40	159501	0	0	0
T41	0	340	0	0
T42	0	400	0	0
T43	0	660	0	0
T92	0	798	0	0
T93	0	825	0	0
T94	0	458	0	0
T95	0	1132	0	0
T96	0	984	0	0
T97	0	785	0	0
T98	757681	0	0	0
T99	180412	0	0	0
T100	407624	0	0	0
T101	303791	0	0	0
T102	505012	0	0	0
T103	58295	0	0	0
T104	957727	0	0	0
T105	1507	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	18447	0	0
T39	165499	211	0	0
T40	159501	0	0	0
T41	0	441	0	0
T42	0	308	0	0
T43	0	535	0	0
T77	0	17	0	0
T78	0	33	0	0
T92	0	727	0	0
T93	0	727	0	0
T94	0	347	0	0
T98	757681	0	0	0
T99	180412	0	0	0
T100	407624	0	0	0
T101	303791	0	0	0
T102	505012	0	0	0
T103	58295	0	0	0
T104	957727	0	0	0
T105	1507	0	0	0
T106	0	25	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	19675	0	0
T39	165499	246	0	0
T40	159501	0	0	0
T41	0	299	0	0
T42	0	338	0	0
T43	0	661	0	0
T92	0	983	0	0
T93	0	920	0	0
T94	0	573	0	0
T95	0	1081	0	0
T96	0	918	0	0
T97	0	794	0	0
T98	757681	0	0	0
T99	180412	0	0	0
T100	407624	0	0	0
T101	303791	0	0	0
T102	505012	0	0	0
T103	58295	0	0	0
T104	957727	0	0	0
T105	1507	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	19705	0	0
T39	165499	249	0	0
T40	159501	0	0	0
T41	0	272	0	0
T42	0	462	0	0
T43	0	621	0	0
T92	0	713	0	0
T93	0	781	0	0
T94	0	532	0	0
T95	0	1108	0	0
T96	0	1022	0	0
T97	0	856	0	0
T98	757681	0	0	0
T99	180412	0	0	0
T100	407624	0	0	0
T101	303791	0	0	0
T102	505012	0	0	0
T103	58295	0	0	0
T104	957727	0	0	0
T105	1507	0	0	0