Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	59189737	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

12840426

1

T1

13

T2

103

T4

22

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	70792845	1			T1	6227		T2	7156		T3	1
values[0x0]	599892	1			T1	5		T2	59		T4	30
values[0x1]	637426	1			T1	8		T2	57		T4	23

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	40869885	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

31160278

1

T1

2053

T2

2467

T4

4864

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	249898	1			T1	16		T2	17		T4	69
valid_sources[0x01]	257081	1			T1	29		T2	24		T4	55
valid_sources[0x02]	301915	1			T1	22		T2	7		T4	53
valid_sources[0x03]	244970	1			T1	23		T2	27		T4	48
valid_sources[0x04]	248438	1			T1	28		T2	48		T4	54
valid_sources[0x05]	273298	1			T1	24		T2	16		T4	45
valid_sources[0x06]	296864	1			T1	14		T2	36		T4	42
valid_sources[0x07]	258780	1			T1	25		T2	26		T4	56
valid_sources[0x08]	268085	1			T1	20		T2	41		T4	73
valid_sources[0x09]	261743	1			T1	24		T2	26		T4	48
valid_sources[0x0a]	277652	1			T1	26		T2	25		T4	46
valid_sources[0x0b]	261900	1			T1	22		T2	39		T4	73
valid_sources[0x0c]	489175	1			T1	17		T2	7		T4	54
valid_sources[0x0d]	283783	1			T1	18		T2	13		T4	62
valid_sources[0x0e]	275596	1			T1	22		T2	29		T4	54
valid_sources[0x0f]	291474	1			T1	27		T2	51		T4	48
valid_sources[0x10]	254713	1			T1	24		T2	35		T4	51
valid_sources[0x11]	274817	1			T1	23		T2	68		T4	80
valid_sources[0x12]	281411	1			T1	24		T2	9		T4	70
valid_sources[0x13]	453111	1			T1	29		T2	22		T4	57
valid_sources[0x14]	303060	1			T1	35		T2	25		T4	55
valid_sources[0x15]	263840	1			T1	22		T2	38		T4	42
valid_sources[0x16]	284369	1			T1	28		T2	44		T4	47
valid_sources[0x17]	298562	1			T1	34		T2	36		T4	62
valid_sources[0x18]	278062	1			T1	19		T2	34		T4	59
valid_sources[0x19]	280855	1			T1	15		T2	17		T4	40
valid_sources[0x1a]	301656	1			T1	23		T2	54		T4	70
valid_sources[0x1b]	252502	1			T1	16		T2	9		T4	59
valid_sources[0x1c]	288772	1			T1	27		T2	65		T4	92
valid_sources[0x1d]	462580	1			T1	32		T4	61		T6	1
valid_sources[0x1e]	260905	1			T1	29		T2	18		T4	44
valid_sources[0x1f]	266247	1			T1	23		T2	27		T4	53
valid_sources[0x20]	282102	1			T1	13		T2	16		T4	64
valid_sources[0x21]	266682	1			T1	22		T2	16		T4	48
valid_sources[0x22]	581174	1			T1	36		T2	21		T4	42
valid_sources[0x23]	253235	1			T1	29		T2	27		T4	58
valid_sources[0x24]	255707	1			T1	32		T2	29		T4	76
valid_sources[0x25]	269336	1			T1	22		T2	15		T4	50
valid_sources[0x26]	357796	1			T1	28		T2	18		T4	66
valid_sources[0x27]	288143	1			T1	23		T2	35		T4	59
valid_sources[0x28]	321418	1			T1	21		T2	43		T4	71
valid_sources[0x29]	256674	1			T1	22		T2	9		T4	41
valid_sources[0x2a]	287208	1			T1	15		T2	53		T4	53
valid_sources[0x2b]	300162	1			T1	16		T2	19		T4	44
valid_sources[0x2c]	260749	1			T1	35		T2	31		T4	39
valid_sources[0x2d]	261802	1			T1	27		T2	47		T4	82
valid_sources[0x2e]	263324	1			T1	23		T2	47		T4	55
valid_sources[0x2f]	332605	1			T1	24		T2	36		T4	65
valid_sources[0x30]	260907	1			T1	37		T2	19		T4	58
valid_sources[0x31]	320860	1			T1	21		T2	24		T4	42
valid_sources[0x32]	287087	1			T1	27		T2	54		T4	57
valid_sources[0x33]	310664	1			T1	18		T2	16		T4	54
valid_sources[0x34]	250872	1			T1	21		T2	36		T4	59
valid_sources[0x35]	312050	1			T1	14		T4	42		T6	2
valid_sources[0x36]	330046	1			T1	13		T2	43		T4	49
valid_sources[0x37]	245929	1			T1	20		T2	72		T4	50
valid_sources[0x38]	323536	1			T1	23		T2	26		T4	59
valid_sources[0x39]	256751	1			T1	22		T2	55		T4	40
valid_sources[0x3a]	377056	1			T1	26		T2	21		T4	47
valid_sources[0x3b]	263843	1			T1	28		T2	21		T4	57
valid_sources[0x3c]	295630	1			T1	22		T2	33		T4	52
valid_sources[0x3d]	280301	1			T1	25		T2	18		T4	58
valid_sources[0x3e]	259223	1			T1	19		T2	38		T4	67
valid_sources[0x3f]	242521	1			T1	20		T2	37		T4	45
valid_sources[0x40]	252132	1			T1	17		T2	8		T4	53
valid_sources[0x41]	262597	1			T1	21		T2	47		T4	64
valid_sources[0x42]	258436	1			T1	30		T2	20		T4	45
valid_sources[0x43]	253403	1			T1	16		T2	76		T4	45
valid_sources[0x44]	266324	1			T1	19		T2	11		T4	75
valid_sources[0x45]	264891	1			T1	31		T2	28		T4	61
valid_sources[0x46]	246861	1			T1	32		T2	11		T4	72
valid_sources[0x47]	262811	1			T1	21		T4	55		T6	3
valid_sources[0x48]	252673	1			T1	28		T2	23		T4	60
valid_sources[0x49]	298457	1			T1	21		T2	23		T4	52
valid_sources[0x4a]	265847	1			T1	40		T2	36		T4	64
valid_sources[0x4b]	262596	1			T1	27		T2	43		T4	72
valid_sources[0x4c]	251878	1			T1	27		T2	37		T4	52
valid_sources[0x4d]	253637	1			T1	33		T2	35		T4	59
valid_sources[0x4e]	282804	1			T1	29		T2	31		T4	66
valid_sources[0x4f]	286568	1			T1	29		T2	34		T4	58
valid_sources[0x50]	293764	1			T1	15		T2	33		T4	63
valid_sources[0x51]	298864	1			T1	29		T2	12		T4	36
valid_sources[0x52]	325336	1			T1	16		T2	25		T4	63
valid_sources[0x53]	274062	1			T1	30		T2	53		T4	48
valid_sources[0x54]	308753	1			T1	18		T2	14		T4	47
valid_sources[0x55]	248672	1			T1	31		T2	43		T4	47
valid_sources[0x56]	264760	1			T1	24		T2	46		T4	51
valid_sources[0x57]	270590	1			T1	30		T2	15		T4	67
valid_sources[0x58]	260837	1			T1	32		T2	23		T4	59
valid_sources[0x59]	273696	1			T1	21		T2	34		T4	55
valid_sources[0x5a]	256039	1			T1	17		T2	24		T4	44
valid_sources[0x5b]	264836	1			T1	25		T2	9		T4	62
valid_sources[0x5c]	286458	1			T1	13		T2	25		T4	69
valid_sources[0x5d]	250295	1			T1	29		T2	51		T4	46
valid_sources[0x5e]	245858	1			T1	22		T2	27		T4	49
valid_sources[0x5f]	256375	1			T1	19		T2	37		T4	56
valid_sources[0x60]	281132	1			T1	19		T2	27		T4	68
valid_sources[0x61]	269026	1			T1	30		T2	46		T4	46
valid_sources[0x62]	267053	1			T1	32		T2	21		T4	52
valid_sources[0x63]	265666	1			T1	32		T2	17		T4	70
valid_sources[0x64]	256964	1			T1	24		T2	26		T4	51
valid_sources[0x65]	261435	1			T1	22		T2	50		T4	72
valid_sources[0x66]	287871	1			T1	25		T2	37		T4	59
valid_sources[0x67]	255468	1			T1	27		T2	18		T4	48
valid_sources[0x68]	295238	1			T1	15		T2	25		T4	52
valid_sources[0x69]	255722	1			T1	24		T2	22		T4	46
valid_sources[0x6a]	277087	1			T1	23		T2	44		T4	52
valid_sources[0x6b]	261818	1			T1	26		T2	40		T4	65
valid_sources[0x6c]	316876	1			T1	22		T2	9		T4	47
valid_sources[0x6d]	264980	1			T1	27		T2	9		T4	50
valid_sources[0x6e]	312499	1			T1	17		T2	28		T4	54
valid_sources[0x6f]	247019	1			T1	16		T2	43		T4	62
valid_sources[0x70]	297771	1			T1	17		T2	34		T4	56
valid_sources[0x71]	246851	1			T1	28		T2	17		T4	80
valid_sources[0x72]	263932	1			T1	33		T2	17		T4	65
valid_sources[0x73]	269641	1			T1	36		T2	16		T4	62
valid_sources[0x74]	286831	1			T1	20		T2	27		T4	58
valid_sources[0x75]	244795	1			T1	35		T2	27		T4	68
valid_sources[0x76]	333357	1			T1	14		T2	32		T4	54
valid_sources[0x77]	305237	1			T1	22		T2	43		T4	55
valid_sources[0x78]	271113	1			T1	31		T2	20		T4	54
valid_sources[0x79]	267296	1			T1	27		T2	26		T4	50
valid_sources[0x7a]	328263	1			T1	23		T2	18		T4	58
valid_sources[0x7b]	251090	1			T1	20		T2	40		T4	53
valid_sources[0x7c]	266002	1			T1	37		T2	30		T4	44
valid_sources[0x7d]	260045	1			T1	25		T2	51		T4	57
valid_sources[0x7e]	369367	1			T1	33		T2	30		T4	42
valid_sources[0x7f]	249663	1			T1	20		T2	23		T4	50
valid_sources[0x80]	273346	1			T1	27		T2	26		T4	64

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

12059731

1

T1

9

T2

13

T4

8

values[0x0]

all_enables

biggest_size

415005

1

T1

3

T2

49

T4

12

values[0x1]

all_enables

biggest_size

365690

1

T1

1

T2

41

T4

2