Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	79717859	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

31907094

1

T1

3

T2

1

T3

9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	100669215	1			T1	1		T2	1		T3	32
values[0x0]	5180245	1			T1	6		T3	7		T4	8
values[0x1]	5775493	1			T1	6		T3	6		T4	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	55292825	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

56332128

1

T1

5

T2

1

T3

16

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	431529	1			T3	1		T4	3		T9	128
valid_sources[0x01]	414859	1			T3	3		T4	2		T9	126
valid_sources[0x02]	415427	1			T3	1		T9	121		T10	96
valid_sources[0x03]	474045	1			T4	1		T9	120		T10	44
valid_sources[0x04]	414005	1			T4	4		T9	154		T10	39
valid_sources[0x05]	436775	1			T4	2		T5	44		T9	112
valid_sources[0x06]	480634	1			T4	2		T6	12		T9	123
valid_sources[0x07]	451801	1			T4	5		T9	126		T10	98
valid_sources[0x08]	415864	1			T4	1		T7	1823		T9	141
valid_sources[0x09]	454762	1			T3	1		T4	4		T6	1
valid_sources[0x0a]	430071	1			T4	4		T9	145		T10	81
valid_sources[0x0b]	406455	1			T4	7		T9	112		T10	60
valid_sources[0x0c]	422309	1			T4	4		T9	113		T10	60
valid_sources[0x0d]	410243	1			T4	1		T6	1		T9	112
valid_sources[0x0e]	418297	1			T1	13		T3	1		T4	5
valid_sources[0x0f]	443895	1			T4	4		T5	5357		T6	4
valid_sources[0x10]	426900	1			T3	1		T4	6		T9	125
valid_sources[0x11]	543332	1			T3	1		T4	2		T9	138
valid_sources[0x12]	437840	1			T4	2		T9	144		T10	57
valid_sources[0x13]	436320	1			T6	15		T9	126		T10	69
valid_sources[0x14]	440806	1			T4	3		T6	2		T9	98
valid_sources[0x15]	461870	1			T4	4		T9	94		T10	80
valid_sources[0x16]	494753	1			T4	7		T6	1		T9	144
valid_sources[0x17]	474594	1			T4	2		T9	100		T10	81
valid_sources[0x18]	431159	1			T9	107		T10	56		T13	50
valid_sources[0x19]	422214	1			T4	2		T9	100		T10	81
valid_sources[0x1a]	433357	1			T4	5		T9	118		T10	66
valid_sources[0x1b]	448099	1			T3	4		T4	3		T8	5361
valid_sources[0x1c]	409922	1			T6	7		T9	106		T10	53
valid_sources[0x1d]	423792	1			T3	1		T4	3		T9	104
valid_sources[0x1e]	406970	1			T3	1		T4	1		T6	2
valid_sources[0x1f]	462611	1			T4	2		T9	91		T10	78
valid_sources[0x20]	415163	1			T4	2		T9	135		T10	63
valid_sources[0x21]	426922	1			T4	5		T9	107		T10	65
valid_sources[0x22]	466329	1			T4	2		T9	119		T10	90
valid_sources[0x23]	410872	1			T4	3		T9	117		T10	97
valid_sources[0x24]	439797	1			T4	3		T9	111		T10	58
valid_sources[0x25]	496935	1			T4	5		T9	113		T10	38
valid_sources[0x26]	409324	1			T4	3		T9	127		T10	56
valid_sources[0x27]	403289	1			T3	1		T4	2		T6	2
valid_sources[0x28]	420831	1			T3	1		T4	4		T6	2
valid_sources[0x29]	406236	1			T4	1		T9	119		T10	65
valid_sources[0x2a]	442151	1			T3	1		T4	3		T9	105
valid_sources[0x2b]	435018	1			T4	3		T9	135		T10	81
valid_sources[0x2c]	410036	1			T4	1		T9	117		T10	65
valid_sources[0x2d]	497919	1			T6	3		T7	2		T9	134
valid_sources[0x2e]	414273	1			T3	1		T4	5		T6	5
valid_sources[0x2f]	467551	1			T4	1		T9	126		T10	103
valid_sources[0x30]	466447	1			T4	4		T9	121		T10	66
valid_sources[0x31]	420233	1			T4	3		T6	4		T9	97
valid_sources[0x32]	404355	1			T4	2		T6	5		T9	106
valid_sources[0x33]	422990	1			T4	4		T9	107		T10	69
valid_sources[0x34]	421333	1			T3	1		T4	3		T9	124
valid_sources[0x35]	402384	1			T4	2		T9	112		T10	89
valid_sources[0x36]	429651	1			T4	1		T9	120		T10	48
valid_sources[0x37]	408090	1			T9	117		T10	80		T13	52
valid_sources[0x38]	420714	1			T4	5		T6	1		T9	130
valid_sources[0x39]	415614	1			T4	2		T6	2		T9	121
valid_sources[0x3a]	406400	1			T9	102		T10	69		T13	78
valid_sources[0x3b]	458016	1			T4	3		T6	3		T9	119
valid_sources[0x3c]	426005	1			T3	1		T4	4		T9	138
valid_sources[0x3d]	461970	1			T4	4		T9	137		T10	67
valid_sources[0x3e]	396181	1			T4	4		T9	99		T10	73
valid_sources[0x3f]	432302	1			T4	5		T9	106		T10	63
valid_sources[0x40]	442795	1			T4	2		T6	2		T9	105
valid_sources[0x41]	418554	1			T4	5		T6	3		T9	143
valid_sources[0x42]	434982	1			T4	2		T9	122		T10	61
valid_sources[0x43]	401224	1			T4	5		T5	1199		T6	4
valid_sources[0x44]	430971	1			T4	4		T9	119		T10	53
valid_sources[0x45]	406426	1			T4	3		T9	130		T10	68
valid_sources[0x46]	427443	1			T4	4		T9	84		T10	51
valid_sources[0x47]	409847	1			T4	1		T9	107		T10	48
valid_sources[0x48]	443718	1			T9	126		T10	89		T13	61
valid_sources[0x49]	419783	1			T4	2		T9	116		T10	32
valid_sources[0x4a]	445042	1			T2	1		T4	1		T6	2
valid_sources[0x4b]	420872	1			T4	2		T9	108		T10	39
valid_sources[0x4c]	402744	1			T4	2		T6	11		T9	127
valid_sources[0x4d]	416357	1			T4	3		T9	128		T10	38
valid_sources[0x4e]	427399	1			T4	4		T9	98		T10	39
valid_sources[0x4f]	402663	1			T4	3		T9	127		T10	74
valid_sources[0x50]	426677	1			T4	4		T9	110		T10	65
valid_sources[0x51]	453859	1			T4	7		T9	104		T10	47
valid_sources[0x52]	435778	1			T4	3		T6	4		T9	113
valid_sources[0x53]	521972	1			T4	1		T9	119		T10	96
valid_sources[0x54]	490385	1			T3	1		T4	2		T9	150
valid_sources[0x55]	430854	1			T3	2		T4	3		T6	3
valid_sources[0x56]	476912	1			T4	9		T9	108		T10	89
valid_sources[0x57]	409683	1			T4	3		T9	110		T10	66
valid_sources[0x58]	415745	1			T4	2		T9	117		T10	78
valid_sources[0x59]	416263	1			T4	5		T9	95		T10	71
valid_sources[0x5a]	465527	1			T3	1		T4	6		T9	127
valid_sources[0x5b]	619570	1			T4	1		T9	132		T10	57
valid_sources[0x5c]	406648	1			T4	1		T6	3		T9	124
valid_sources[0x5d]	422667	1			T3	1		T4	3		T9	110
valid_sources[0x5e]	472457	1			T4	1		T9	132		T10	79
valid_sources[0x5f]	457699	1			T9	131		T10	57		T13	61
valid_sources[0x60]	411109	1			T3	1		T4	3		T9	145
valid_sources[0x61]	414430	1			T4	2		T9	139		T10	66
valid_sources[0x62]	417929	1			T4	3		T6	1		T9	112
valid_sources[0x63]	461846	1			T4	3		T9	95		T10	83
valid_sources[0x64]	430106	1			T4	4		T9	131		T10	57
valid_sources[0x65]	440144	1			T4	4		T9	124		T10	70
valid_sources[0x66]	420885	1			T4	6		T6	2		T9	124
valid_sources[0x67]	410263	1			T4	5		T9	129		T10	64
valid_sources[0x68]	446000	1			T4	4		T9	103		T10	74
valid_sources[0x69]	401098	1			T4	3		T5	1		T9	127
valid_sources[0x6a]	406932	1			T4	3		T9	120		T10	52
valid_sources[0x6b]	424798	1			T3	1		T4	1		T6	4
valid_sources[0x6c]	429287	1			T4	1		T9	106		T10	85
valid_sources[0x6d]	467549	1			T4	1		T9	106		T10	74
valid_sources[0x6e]	518629	1			T4	6		T6	14		T9	120
valid_sources[0x6f]	421924	1			T4	3		T9	150		T10	58
valid_sources[0x70]	408643	1			T4	1		T9	100		T10	81
valid_sources[0x71]	426395	1			T4	2		T6	1		T9	116
valid_sources[0x72]	432332	1			T4	2		T9	113		T10	68
valid_sources[0x73]	420794	1			T4	2		T9	100		T10	59
valid_sources[0x74]	429109	1			T4	2		T5	882		T6	3
valid_sources[0x75]	454409	1			T9	118		T10	70		T13	64
valid_sources[0x76]	394033	1			T4	2		T6	2		T9	121
valid_sources[0x77]	438412	1			T4	4		T9	128		T10	67
valid_sources[0x78]	431816	1			T4	2		T9	109		T10	72
valid_sources[0x79]	459242	1			T4	7		T6	4		T9	100
valid_sources[0x7a]	428627	1			T4	7		T6	14		T9	132
valid_sources[0x7b]	454313	1			T4	3		T9	115		T10	68
valid_sources[0x7c]	420065	1			T4	2		T6	1		T9	103
valid_sources[0x7d]	434535	1			T4	3		T5	18		T9	135
valid_sources[0x7e]	431616	1			T4	2		T9	110		T10	86
valid_sources[0x7f]	450448	1			T3	2		T4	2		T6	1
valid_sources[0x80]	443573	1			T4	3		T9	133		T10	41

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

22174811

1

T1

1

T2

1

T3

5

values[0x0]

all_enables

biggest_size

4898367

1

T1

2

T3

2

T4

5

values[0x1]

all_enables

biggest_size

4833916

1

T3

2

T5

4

T6

12