Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression/uart-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	15931701	0	0
ctrl_rd_A	2147483647	349900	0	0
intr_enable_rd_A	2147483647	309619	0	0
ovrd_rd_A	2147483647	350544	0	0
timeout_ctrl_rd_A	2147483647	352072	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15931701	0	0
T25	260670	55256	0	0
T26	0	59804	0	0
T27	0	146482	0	0
T34	0	186256	0	0
T35	0	285608	0	0
T36	0	259353	0	0
T37	0	212729	0	0
T38	0	183597	0	0
T39	0	173916	0	0
T40	0	193533	0	0
T41	218692	0	0	0
T42	463827	0	0	0
T43	175662	0	0	0
T44	254958	0	0	0
T45	110974	0	0	0
T46	108426	0	0	0
T47	1046	0	0	0
T48	6639	0	0	0
T49	555418	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	349900	0	0
T27	594108	15056	0	0
T36	0	12675	0	0
T38	0	20713	0	0
T40	0	22440	0	0
T114	0	25877	0	0
T115	0	12295	0	0
T116	0	2435	0	0
T117	0	5958	0	0
T118	0	3393	0	0
T119	0	7727	0	0
T120	499376	0	0	0
T121	441121	0	0	0
T122	253896	0	0	0
T123	430393	0	0	0
T124	19084	0	0	0
T125	320441	0	0	0
T126	330435	0	0	0
T127	261851	0	0	0
T128	491408	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	309619	0	0
T27	594108	13542	0	0
T36	0	10937	0	0
T38	0	18055	0	0
T40	0	19409	0	0
T114	0	22868	0	0
T115	0	11086	0	0
T116	0	2171	0	0
T117	0	5380	0	0
T120	499376	0	0	0
T121	441121	0	0	0
T122	253896	0	0	0
T123	430393	0	0	0
T124	19084	0	0	0
T125	320441	0	0	0
T126	330435	0	0	0
T127	261851	0	0	0
T128	491408	0	0	0
T129	0	14	0	0
T130	0	29	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	350544	0	0
T27	594108	15358	0	0
T36	0	13086	0	0
T38	0	20900	0	0
T40	0	21722	0	0
T114	0	26231	0	0
T115	0	12379	0	0
T116	0	2381	0	0
T117	0	6138	0	0
T118	0	3539	0	0
T119	0	7491	0	0
T120	499376	0	0	0
T121	441121	0	0	0
T122	253896	0	0	0
T123	430393	0	0	0
T124	19084	0	0	0
T125	320441	0	0	0
T126	330435	0	0	0
T127	261851	0	0	0
T128	491408	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	352072	0	0
T27	594108	15328	0	0
T36	0	12874	0	0
T38	0	20697	0	0
T40	0	21422	0	0
T114	0	25397	0	0
T115	0	12642	0	0
T116	0	2532	0	0
T117	0	5938	0	0
T118	0	3267	0	0
T119	0	6964	0	0
T120	499376	0	0	0
T121	441121	0	0	0
T122	253896	0	0	0
T123	430393	0	0	0
T124	19084	0	0	0
T125	320441	0	0	0
T126	330435	0	0	0
T127	261851	0	0	0
T128	491408	0	0	0