USBDEV Simulation Results

Wednesday May 17 2023 07:05:42 UTC

GitHub Revision: 3df77bec1

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2320738200

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke usbdev_smoke 0.700s 2.225us 0 50 0.00
V1 csr_hw_reset usbdev_csr_hw_reset 0.770s 41.013us 5 5 100.00
V1 csr_rw usbdev_csr_rw 1.070s 172.128us 20 20 100.00
V1 csr_bit_bash usbdev_csr_bit_bash 14.240s 10.581ms 2 5 40.00
V1 csr_aliasing usbdev_csr_aliasing 3.360s 444.521us 5 5 100.00
V1 csr_mem_rw_with_rand_reset usbdev_csr_mem_rw_with_rand_reset 2.200s 163.410us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr usbdev_csr_rw 1.070s 172.128us 20 20 100.00
usbdev_csr_aliasing 3.360s 444.521us 5 5 100.00
V1 mem_walk usbdev_mem_walk 4.740s 688.297us 5 5 100.00
V1 mem_partial_access usbdev_mem_partial_access 2.190s 204.976us 5 5 100.00
V1 TOTAL 62 115 53.91
V2 intr_test usbdev_intr_test 0.750s 25.036us 50 50 100.00
V2 tl_d_oob_addr_access usbdev_tl_errors 3.680s 328.450us 20 20 100.00
V2 tl_d_illegal_access usbdev_tl_errors 3.680s 328.450us 20 20 100.00
V2 tl_d_outstanding_access usbdev_csr_hw_reset 0.770s 41.013us 5 5 100.00
usbdev_csr_rw 1.070s 172.128us 20 20 100.00
usbdev_csr_aliasing 3.360s 444.521us 5 5 100.00
usbdev_same_csr_outstanding 10.630s 10.160ms 16 20 80.00
V2 tl_d_partial_access usbdev_csr_hw_reset 0.770s 41.013us 5 5 100.00
usbdev_csr_rw 1.070s 172.128us 20 20 100.00
usbdev_csr_aliasing 3.360s 444.521us 5 5 100.00
usbdev_same_csr_outstanding 10.630s 10.160ms 16 20 80.00
V2 TOTAL 86 90 95.56
V2S tl_intg_err usbdev_sec_cm 0.710s 1.487us 0 5 0.00
usbdev_tl_intg_err 10.030s 10.016ms 4 20 20.00
V2S sec_cm_bus_integrity usbdev_tl_intg_err 10.030s 10.016ms 4 20 20.00
V2S TOTAL 4 25 16.00
V3 TOTAL 0 0 --
Unmapped tests usbdev_stress_all_with_rand_reset 0.720s 4.051us 0 50 0.00
usbdev_stress_all 0.620s 0 50 0.00
TOTAL 152 330 46.06

Testplan Progress

Items Total Written Passing Progress
N.A. 2 2 0 0.00
V1 8 8 6 75.00
V2 3 3 2 66.67
V2S 2 2 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
69.81 69.41 63.91 87.42 0.00 74.05 97.77 96.10

Failure Buckets

Past Results