Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
69.62	69.25	63.91	87.42	0.00	74.05	97.77	94.98

Total tests in report: 154

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
56.96	56.96	67.64	67.64	57.73	57.73	85.65	85.65	0.00	0.00	72.03	72.03	91.34	91.34	24.35	24.35	/workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3809581762
64.75	7.79	68.81	1.17	61.04	3.31	89.88	4.24	0.00	0.00	73.62	1.59	91.34	0.00	68.59	44.24	/workspace/coverage/cover_reg_top/41.usbdev_intr_test.2275665204
67.39	2.63	68.81	0.00	63.45	2.41	92.71	2.82	0.00	0.00	73.71	0.09	93.30	1.96	79.74	11.15	/workspace/coverage/cover_reg_top/2.usbdev_tl_errors.92259497
68.35	0.97	68.81	0.00	63.45	0.00	92.71	0.00	0.00	0.00	73.71	0.00	93.58	0.28	86.25	6.51	/workspace/coverage/cover_reg_top/15.usbdev_intr_test.114205626
68.95	0.60	68.81	0.00	63.45	0.00	92.71	0.00	0.00	0.00	73.71	0.00	97.77	4.19	86.25	0.00	/workspace/coverage/cover_reg_top/17.usbdev_csr_rw.3756765229
69.54	0.58	68.85	0.04	63.55	0.10	93.41	0.71	0.00	0.00	73.79	0.09	97.77	0.00	89.41	3.16	/workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.1476175977
69.94	0.40	68.85	0.00	63.55	0.00	93.41	0.00	0.00	0.00	73.79	0.00	97.77	0.00	92.19	2.79	/workspace/coverage/cover_reg_top/1.usbdev_intr_test.2950665997
70.18	0.24	68.91	0.06	63.68	0.13	94.59	1.18	0.00	0.00	73.92	0.13	97.77	0.00	92.38	0.19	/workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.3943641601
70.34	0.16	69.25	0.34	63.68	0.00	94.59	0.00	0.00	0.00	73.97	0.04	97.77	0.00	93.12	0.74	/workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3227861230
70.47	0.13	69.25	0.00	63.68	0.00	94.59	0.00	0.00	0.00	73.97	0.00	97.77	0.00	94.05	0.93	/workspace/coverage/cover_reg_top/13.usbdev_intr_test.1940290571
70.58	0.11	69.25	0.00	63.68	0.00	94.59	0.00	0.00	0.00	73.97	0.00	97.77	0.00	94.80	0.74	/workspace/coverage/cover_reg_top/32.usbdev_intr_test.1165654431
70.63	0.05	69.25	0.00	63.73	0.05	94.82	0.24	0.00	0.00	74.05	0.09	97.77	0.00	94.80	0.00	/workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3081446016
70.66	0.03	69.25	0.00	63.78	0.05	94.82	0.00	0.00	0.00	74.05	0.00	97.77	0.00	94.98	0.19	/workspace/coverage/cover_reg_top/13.usbdev_tl_errors.470408333
70.68	0.02	69.25	0.00	63.91	0.13	94.82	0.00	0.00	0.00	74.05	0.00	97.77	0.00	94.98	0.00	/workspace/coverage/cover_reg_top/1.usbdev_tl_errors.3348293920

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.135413049
/workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.181162655
/workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1093482143
/workspace/coverage/cover_reg_top/0.usbdev_intr_test.4266811175
/workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.1358340144
/workspace/coverage/cover_reg_top/0.usbdev_mem_walk.1437158798
/workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.3410900250
/workspace/coverage/cover_reg_top/0.usbdev_tl_errors.2234644097
/workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.1775072185
/workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.1754454045
/workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.2705255405
/workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.3422672781
/workspace/coverage/cover_reg_top/1.usbdev_csr_rw.1199414436
/workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.340499025
/workspace/coverage/cover_reg_top/1.usbdev_mem_walk.2834448033
/workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.4248353559
/workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.3913028584
/workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3880065007
/workspace/coverage/cover_reg_top/10.usbdev_intr_test.192542768
/workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2961388010
/workspace/coverage/cover_reg_top/10.usbdev_tl_errors.17407514
/workspace/coverage/cover_reg_top/11.usbdev_csr_rw.2838295878
/workspace/coverage/cover_reg_top/11.usbdev_intr_test.1101015946
/workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.1305086609
/workspace/coverage/cover_reg_top/11.usbdev_tl_errors.1862838146
/workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.2549979344
/workspace/coverage/cover_reg_top/12.usbdev_csr_rw.1295787650
/workspace/coverage/cover_reg_top/12.usbdev_intr_test.1478763844
/workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3368968734
/workspace/coverage/cover_reg_top/12.usbdev_tl_errors.1332112405
/workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.151222523
/workspace/coverage/cover_reg_top/13.usbdev_csr_rw.1600578608
/workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.3987504582
/workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2078494273
/workspace/coverage/cover_reg_top/14.usbdev_csr_rw.4010684713
/workspace/coverage/cover_reg_top/14.usbdev_intr_test.1714761187
/workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.2727490373
/workspace/coverage/cover_reg_top/14.usbdev_tl_errors.985117603
/workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.3346705235
/workspace/coverage/cover_reg_top/15.usbdev_csr_rw.2032661888
/workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1205304631
/workspace/coverage/cover_reg_top/15.usbdev_tl_errors.4008817786
/workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.1089574157
/workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2060007860
/workspace/coverage/cover_reg_top/16.usbdev_intr_test.171539440
/workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.1462940546
/workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3607365238
/workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.2294509977
/workspace/coverage/cover_reg_top/17.usbdev_intr_test.1028046125
/workspace/coverage/cover_reg_top/17.usbdev_tl_errors.1860331251
/workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.3499435624
/workspace/coverage/cover_reg_top/18.usbdev_csr_rw.3098426478
/workspace/coverage/cover_reg_top/18.usbdev_intr_test.1382675485
/workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.339003387
/workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3744102917
/workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2148524708
/workspace/coverage/cover_reg_top/19.usbdev_csr_rw.1873729839
/workspace/coverage/cover_reg_top/19.usbdev_intr_test.2455863866
/workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.937238034
/workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3713605786
/workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2696886881
/workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.4018101128
/workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.3035023701
/workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2708457248
/workspace/coverage/cover_reg_top/2.usbdev_intr_test.1672727641
/workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.2889648083
/workspace/coverage/cover_reg_top/2.usbdev_mem_walk.1272666572
/workspace/coverage/cover_reg_top/20.usbdev_intr_test.3796909591
/workspace/coverage/cover_reg_top/21.usbdev_intr_test.4275888082
/workspace/coverage/cover_reg_top/22.usbdev_intr_test.2016686680
/workspace/coverage/cover_reg_top/23.usbdev_intr_test.225394601
/workspace/coverage/cover_reg_top/24.usbdev_intr_test.3718103811
/workspace/coverage/cover_reg_top/25.usbdev_intr_test.995299123
/workspace/coverage/cover_reg_top/26.usbdev_intr_test.1996979730
/workspace/coverage/cover_reg_top/27.usbdev_intr_test.2901491749
/workspace/coverage/cover_reg_top/28.usbdev_intr_test.2085949106
/workspace/coverage/cover_reg_top/29.usbdev_intr_test.3297346067
/workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3903963251
/workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.1898159040
/workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3971078182
/workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.676262833
/workspace/coverage/cover_reg_top/3.usbdev_csr_rw.113036899
/workspace/coverage/cover_reg_top/3.usbdev_intr_test.4088258710
/workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2151473049
/workspace/coverage/cover_reg_top/3.usbdev_mem_walk.633616057
/workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.492368201
/workspace/coverage/cover_reg_top/3.usbdev_tl_errors.3815721033
/workspace/coverage/cover_reg_top/30.usbdev_intr_test.2728606689
/workspace/coverage/cover_reg_top/31.usbdev_intr_test.3970303886
/workspace/coverage/cover_reg_top/33.usbdev_intr_test.2883997539
/workspace/coverage/cover_reg_top/34.usbdev_intr_test.964580463
/workspace/coverage/cover_reg_top/35.usbdev_intr_test.301668808
/workspace/coverage/cover_reg_top/36.usbdev_intr_test.3891830603
/workspace/coverage/cover_reg_top/37.usbdev_intr_test.1361137729
/workspace/coverage/cover_reg_top/38.usbdev_intr_test.1642588558
/workspace/coverage/cover_reg_top/39.usbdev_intr_test.3449344255
/workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2103783934
/workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.2679137439
/workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.1390061699
/workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2766306676
/workspace/coverage/cover_reg_top/4.usbdev_csr_rw.3971663046
/workspace/coverage/cover_reg_top/4.usbdev_intr_test.1836229622
/workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.3693319598
/workspace/coverage/cover_reg_top/4.usbdev_mem_walk.1147105616
/workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.3663351267
/workspace/coverage/cover_reg_top/4.usbdev_tl_errors.4176385399
/workspace/coverage/cover_reg_top/40.usbdev_intr_test.192486462
/workspace/coverage/cover_reg_top/42.usbdev_intr_test.2029775109
/workspace/coverage/cover_reg_top/43.usbdev_intr_test.4099698004
/workspace/coverage/cover_reg_top/44.usbdev_intr_test.1302982422
/workspace/coverage/cover_reg_top/45.usbdev_intr_test.1272263932
/workspace/coverage/cover_reg_top/46.usbdev_intr_test.1448528600
/workspace/coverage/cover_reg_top/47.usbdev_intr_test.3911267052
/workspace/coverage/cover_reg_top/48.usbdev_intr_test.2858265987
/workspace/coverage/cover_reg_top/49.usbdev_intr_test.796900551
/workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.2620686764
/workspace/coverage/cover_reg_top/5.usbdev_csr_rw.284885436
/workspace/coverage/cover_reg_top/5.usbdev_intr_test.562296340
/workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.815421531
/workspace/coverage/cover_reg_top/5.usbdev_tl_errors.456340798
/workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.4293559894
/workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1270992982
/workspace/coverage/cover_reg_top/6.usbdev_intr_test.1386859934
/workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.1749537360
/workspace/coverage/cover_reg_top/6.usbdev_tl_errors.829699354
/workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.570096291
/workspace/coverage/cover_reg_top/7.usbdev_csr_rw.2268680367
/workspace/coverage/cover_reg_top/7.usbdev_intr_test.4040778974
/workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.1110294866
/workspace/coverage/cover_reg_top/7.usbdev_tl_errors.3365338630
/workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2274987825
/workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2134639230
/workspace/coverage/cover_reg_top/8.usbdev_intr_test.424742855
/workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3368771266
/workspace/coverage/cover_reg_top/8.usbdev_tl_errors.3516207801
/workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.246659302
/workspace/coverage/cover_reg_top/9.usbdev_csr_rw.592568314
/workspace/coverage/cover_reg_top/9.usbdev_intr_test.4131386852
/workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.2578957757
/workspace/coverage/cover_reg_top/9.usbdev_tl_errors.2488220071

Total test records in report: 154

tests.html | tests1.html | tests2.html

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/cover_reg_top/4.usbdev_mem_walk.1147105616	May 26 02:09:31 AM PDT 23	May 26 02:09:33 AM PDT 23	102752370 ps
T2	/workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3809581762	May 26 02:10:27 AM PDT 23	May 26 02:10:29 AM PDT 23	67069471 ps
T3	/workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.1358340144	May 26 02:08:58 AM PDT 23	May 26 02:08:59 AM PDT 23	57761490 ps
T6	/workspace/coverage/cover_reg_top/30.usbdev_intr_test.2728606689	May 26 02:10:29 AM PDT 23	May 26 02:10:30 AM PDT 23	39505879 ps
T7	/workspace/coverage/cover_reg_top/13.usbdev_tl_errors.470408333	May 26 02:10:24 AM PDT 23	May 26 02:10:26 AM PDT 23	83321353 ps
T4	/workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.1089574157	May 26 02:10:31 AM PDT 23	May 26 02:10:32 AM PDT 23	33866293 ps
T8	/workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.2727490373	May 26 02:10:26 AM PDT 23	May 26 02:10:28 AM PDT 23	46717373 ps
T9	/workspace/coverage/cover_reg_top/15.usbdev_csr_rw.2032661888	May 26 02:10:26 AM PDT 23	May 26 02:10:28 AM PDT 23	28725019 ps
T5	/workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.4293559894	May 26 02:09:29 AM PDT 23	May 26 02:09:31 AM PDT 23	39602058 ps
T23	/workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3227861230	May 26 02:10:21 AM PDT 23	May 26 02:10:23 AM PDT 23	22912869 ps
T16	/workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.1305086609	May 26 02:10:24 AM PDT 23	May 26 02:10:25 AM PDT 23	80068153 ps
T17	/workspace/coverage/cover_reg_top/41.usbdev_intr_test.2275665204	May 26 02:10:22 AM PDT 23	May 26 02:10:23 AM PDT 23	33940420 ps
T24	/workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.3499435624	May 26 02:10:30 AM PDT 23	May 26 02:10:33 AM PDT 23	233181612 ps
T25	/workspace/coverage/cover_reg_top/7.usbdev_tl_errors.3365338630	May 26 02:09:32 AM PDT 23	May 26 02:09:33 AM PDT 23	124607784 ps
T20	/workspace/coverage/cover_reg_top/15.usbdev_intr_test.114205626	May 26 02:10:27 AM PDT 23	May 26 02:10:27 AM PDT 23	33061882 ps
T34	/workspace/coverage/cover_reg_top/17.usbdev_csr_rw.3756765229	May 26 02:10:27 AM PDT 23	May 26 02:10:28 AM PDT 23	58813968 ps
T26	/workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.340499025	May 26 02:08:58 AM PDT 23	May 26 02:09:01 AM PDT 23	187437545 ps
T27	/workspace/coverage/cover_reg_top/2.usbdev_tl_errors.92259497	May 26 02:08:59 AM PDT 23	May 26 02:09:01 AM PDT 23	155577669 ps
T35	/workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2696886881	May 26 02:09:27 AM PDT 23	May 26 02:09:30 AM PDT 23	120382178 ps
T18	/workspace/coverage/cover_reg_top/16.usbdev_intr_test.171539440	May 26 02:10:26 AM PDT 23	May 26 02:10:27 AM PDT 23	18296471 ps
T22	/workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3971078182	May 26 02:09:32 AM PDT 23	May 26 02:09:35 AM PDT 23	27670498 ps
T21	/workspace/coverage/cover_reg_top/28.usbdev_intr_test.2085949106	May 26 02:10:30 AM PDT 23	May 26 02:10:31 AM PDT 23	17661835 ps
T28	/workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3713605786	May 26 02:10:29 AM PDT 23	May 26 02:10:31 AM PDT 23	47671548 ps
T19	/workspace/coverage/cover_reg_top/44.usbdev_intr_test.1302982422	May 26 02:10:22 AM PDT 23	May 26 02:10:23 AM PDT 23	36018252 ps
T70	/workspace/coverage/cover_reg_top/2.usbdev_mem_walk.1272666572	May 26 02:08:59 AM PDT 23	May 26 02:09:03 AM PDT 23	488176623 ps
T13	/workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1093482143	May 26 02:08:59 AM PDT 23	May 26 02:09:00 AM PDT 23	32481793 ps
T53	/workspace/coverage/cover_reg_top/19.usbdev_intr_test.2455863866	May 26 02:10:30 AM PDT 23	May 26 02:10:31 AM PDT 23	41736413 ps
T54	/workspace/coverage/cover_reg_top/14.usbdev_intr_test.1714761187	May 26 02:10:26 AM PDT 23	May 26 02:10:27 AM PDT 23	22342755 ps
T55	/workspace/coverage/cover_reg_top/9.usbdev_intr_test.4131386852	May 26 02:09:39 AM PDT 23	May 26 02:09:40 AM PDT 23	29543242 ps
T71	/workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.2294509977	May 26 02:10:32 AM PDT 23	May 26 02:10:33 AM PDT 23	17873531 ps
T67	/workspace/coverage/cover_reg_top/49.usbdev_intr_test.796900551	May 26 02:10:25 AM PDT 23	May 26 02:10:25 AM PDT 23	23015390 ps
T72	/workspace/coverage/cover_reg_top/1.usbdev_mem_walk.2834448033	May 26 02:08:59 AM PDT 23	May 26 02:09:03 AM PDT 23	143589028 ps
T10	/workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.3943641601	May 26 02:08:59 AM PDT 23	May 26 02:09:00 AM PDT 23	32175053 ps
T46	/workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.2549979344	May 26 02:10:24 AM PDT 23	May 26 02:10:25 AM PDT 23	24575182 ps
T64	/workspace/coverage/cover_reg_top/25.usbdev_intr_test.995299123	May 26 02:10:30 AM PDT 23	May 26 02:10:30 AM PDT 23	14538321 ps
T62	/workspace/coverage/cover_reg_top/1.usbdev_intr_test.2950665997	May 26 02:08:58 AM PDT 23	May 26 02:08:59 AM PDT 23	16777763 ps
T56	/workspace/coverage/cover_reg_top/26.usbdev_intr_test.1996979730	May 26 02:10:30 AM PDT 23	May 26 02:10:31 AM PDT 23	17917566 ps
T11	/workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.2620686764	May 26 02:09:41 AM PDT 23	May 26 02:09:43 AM PDT 23	84135128 ps
T59	/workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.246659302	May 26 02:09:25 AM PDT 23	May 26 02:09:30 AM PDT 23	134960512 ps
T60	/workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.181162655	May 26 02:09:00 AM PDT 23	May 26 02:09:03 AM PDT 23	85112961 ps
T63	/workspace/coverage/cover_reg_top/18.usbdev_intr_test.1382675485	May 26 02:10:30 AM PDT 23	May 26 02:10:31 AM PDT 23	37440309 ps
T36	/workspace/coverage/cover_reg_top/3.usbdev_csr_rw.113036899	May 26 02:09:27 AM PDT 23	May 26 02:09:28 AM PDT 23	53993171 ps
T73	/workspace/coverage/cover_reg_top/11.usbdev_intr_test.1101015946	May 26 02:10:22 AM PDT 23	May 26 02:10:23 AM PDT 23	22937786 ps
T47	/workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2103783934	May 26 02:09:41 AM PDT 23	May 26 02:09:44 AM PDT 23	209188936 ps
T61	/workspace/coverage/cover_reg_top/38.usbdev_intr_test.1642588558	May 26 02:10:24 AM PDT 23	May 26 02:10:25 AM PDT 23	22190565 ps
T43	/workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.937238034	May 26 02:10:30 AM PDT 23	May 26 02:10:32 AM PDT 23	81272175 ps
T29	/workspace/coverage/cover_reg_top/17.usbdev_tl_errors.1860331251	May 26 02:10:31 AM PDT 23	May 26 02:10:34 AM PDT 23	308058968 ps
T48	/workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.3346705235	May 26 02:10:32 AM PDT 23	May 26 02:10:33 AM PDT 23	44810000 ps
T37	/workspace/coverage/cover_reg_top/18.usbdev_csr_rw.3098426478	May 26 02:10:26 AM PDT 23	May 26 02:10:27 AM PDT 23	48798261 ps
T74	/workspace/coverage/cover_reg_top/32.usbdev_intr_test.1165654431	May 26 02:10:29 AM PDT 23	May 26 02:10:30 AM PDT 23	18012486 ps
T75	/workspace/coverage/cover_reg_top/23.usbdev_intr_test.225394601	May 26 02:10:30 AM PDT 23	May 26 02:10:31 AM PDT 23	17550993 ps
T38	/workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2151473049	May 26 02:09:40 AM PDT 23	May 26 02:09:43 AM PDT 23	208060018 ps
T76	/workspace/coverage/cover_reg_top/42.usbdev_intr_test.2029775109	May 26 02:10:24 AM PDT 23	May 26 02:10:25 AM PDT 23	12906373 ps
T39	/workspace/coverage/cover_reg_top/11.usbdev_csr_rw.2838295878	May 26 02:10:22 AM PDT 23	May 26 02:10:23 AM PDT 23	63022273 ps
T77	/workspace/coverage/cover_reg_top/29.usbdev_intr_test.3297346067	May 26 02:10:25 AM PDT 23	May 26 02:10:26 AM PDT 23	48668188 ps
T30	/workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3744102917	May 26 02:10:30 AM PDT 23	May 26 02:10:33 AM PDT 23	206322503 ps
T49	/workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3368771266	May 26 02:09:31 AM PDT 23	May 26 02:09:33 AM PDT 23	77815970 ps
T68	/workspace/coverage/cover_reg_top/6.usbdev_intr_test.1386859934	May 26 02:09:33 AM PDT 23	May 26 02:09:35 AM PDT 23	28194517 ps
T78	/workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.151222523	May 26 02:10:30 AM PDT 23	May 26 02:10:31 AM PDT 23	26339053 ps
T65	/workspace/coverage/cover_reg_top/13.usbdev_intr_test.1940290571	May 26 02:10:30 AM PDT 23	May 26 02:10:31 AM PDT 23	12696265 ps
T79	/workspace/coverage/cover_reg_top/5.usbdev_intr_test.562296340	May 26 02:09:29 AM PDT 23	May 26 02:09:30 AM PDT 23	12871123 ps
T12	/workspace/coverage/cover_reg_top/1.usbdev_csr_rw.1199414436	May 26 02:08:59 AM PDT 23	May 26 02:09:00 AM PDT 23	21421459 ps
T80	/workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3368968734	May 26 02:10:24 AM PDT 23	May 26 02:10:26 AM PDT 23	146927984 ps
T81	/workspace/coverage/cover_reg_top/0.usbdev_intr_test.4266811175	May 26 02:08:58 AM PDT 23	May 26 02:08:59 AM PDT 23	15620439 ps
T82	/workspace/coverage/cover_reg_top/17.usbdev_intr_test.1028046125	May 26 02:10:31 AM PDT 23	May 26 02:10:32 AM PDT 23	18722422 ps
T83	/workspace/coverage/cover_reg_top/7.usbdev_intr_test.4040778974	May 26 02:09:30 AM PDT 23	May 26 02:09:31 AM PDT 23	17608918 ps
T84	/workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2078494273	May 26 02:10:25 AM PDT 23	May 26 02:10:27 AM PDT 23	26492291 ps
T44	/workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.1390061699	May 26 02:09:29 AM PDT 23	May 26 02:09:30 AM PDT 23	22819726 ps
T40	/workspace/coverage/cover_reg_top/9.usbdev_csr_rw.592568314	May 26 02:09:34 AM PDT 23	May 26 02:09:35 AM PDT 23	19183319 ps
T31	/workspace/coverage/cover_reg_top/8.usbdev_tl_errors.3516207801	May 26 02:09:28 AM PDT 23	May 26 02:09:31 AM PDT 23	50328716 ps
T85	/workspace/coverage/cover_reg_top/3.usbdev_intr_test.4088258710	May 26 02:09:32 AM PDT 23	May 26 02:09:33 AM PDT 23	31905360 ps
T32	/workspace/coverage/cover_reg_top/15.usbdev_tl_errors.4008817786	May 26 02:10:27 AM PDT 23	May 26 02:10:29 AM PDT 23	136841494 ps
T86	/workspace/coverage/cover_reg_top/4.usbdev_intr_test.1836229622	May 26 02:09:41 AM PDT 23	May 26 02:09:42 AM PDT 23	31519020 ps
T87	/workspace/coverage/cover_reg_top/14.usbdev_csr_rw.4010684713	May 26 02:10:36 AM PDT 23	May 26 02:10:37 AM PDT 23	31995489 ps
T41	/workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.2679137439	May 26 02:09:29 AM PDT 23	May 26 02:09:38 AM PDT 23	372291043 ps
T88	/workspace/coverage/cover_reg_top/35.usbdev_intr_test.301668808	May 26 02:10:25 AM PDT 23	May 26 02:10:25 AM PDT 23	35456518 ps
T42	/workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.3693319598	May 26 02:09:31 AM PDT 23	May 26 02:09:33 AM PDT 23	59462855 ps
T89	/workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2961388010	May 26 02:10:23 AM PDT 23	May 26 02:10:24 AM PDT 23	60739650 ps
T90	/workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.492368201	May 26 02:09:25 AM PDT 23	May 26 02:09:28 AM PDT 23	132214616 ps
T91	/workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.2889648083	May 26 02:09:41 AM PDT 23	May 26 02:09:43 AM PDT 23	143909127 ps
T33	/workspace/coverage/cover_reg_top/10.usbdev_tl_errors.17407514	May 26 02:09:32 AM PDT 23	May 26 02:09:33 AM PDT 23	128747123 ps
T92	/workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3880065007	May 26 02:10:27 AM PDT 23	May 26 02:10:28 AM PDT 23	17577001 ps
T93	/workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2060007860	May 26 02:10:36 AM PDT 23	May 26 02:10:37 AM PDT 23	55268991 ps
T50	/workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.135413049	May 26 02:08:59 AM PDT 23	May 26 02:09:03 AM PDT 23	357474547 ps
T51	/workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.570096291	May 26 02:09:26 AM PDT 23	May 26 02:09:28 AM PDT 23	113142594 ps
T66	/workspace/coverage/cover_reg_top/22.usbdev_intr_test.2016686680	May 26 02:10:30 AM PDT 23	May 26 02:10:31 AM PDT 23	13474369 ps
T94	/workspace/coverage/cover_reg_top/11.usbdev_tl_errors.1862838146	May 26 02:10:23 AM PDT 23	May 26 02:10:26 AM PDT 23	159109338 ps
T52	/workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.1754454045	May 26 02:08:59 AM PDT 23	May 26 02:09:04 AM PDT 23	888110176 ps
T57	/workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2148524708	May 26 02:10:30 AM PDT 23	May 26 02:10:31 AM PDT 23	25683633 ps
T95	/workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.1749537360	May 26 02:09:32 AM PDT 23	May 26 02:09:33 AM PDT 23	127339716 ps
T96	/workspace/coverage/cover_reg_top/19.usbdev_csr_rw.1873729839	May 26 02:10:36 AM PDT 23	May 26 02:10:37 AM PDT 23	65033807 ps
T97	/workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.815421531	May 26 02:09:41 AM PDT 23	May 26 02:09:42 AM PDT 23	31666248 ps
T98	/workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.3913028584	May 26 02:10:24 AM PDT 23	May 26 02:10:25 AM PDT 23	50817485 ps
T99	/workspace/coverage/cover_reg_top/0.usbdev_mem_walk.1437158798	May 26 02:08:58 AM PDT 23	May 26 02:09:00 AM PDT 23	242555607 ps
T100	/workspace/coverage/cover_reg_top/3.usbdev_tl_errors.3815721033	May 26 02:09:39 AM PDT 23	May 26 02:09:42 AM PDT 23	206200212 ps
T101	/workspace/coverage/cover_reg_top/12.usbdev_csr_rw.1295787650	May 26 02:10:24 AM PDT 23	May 26 02:10:26 AM PDT 23	146938947 ps
T102	/workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.1110294866	May 26 02:09:29 AM PDT 23	May 26 02:09:31 AM PDT 23	29847267 ps
T103	/workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2274987825	May 26 02:09:30 AM PDT 23	May 26 02:09:32 AM PDT 23	24561851 ps
T58	/workspace/coverage/cover_reg_top/5.usbdev_csr_rw.284885436	May 26 02:09:31 AM PDT 23	May 26 02:09:32 AM PDT 23	62594132 ps
T104	/workspace/coverage/cover_reg_top/21.usbdev_intr_test.4275888082	May 26 02:10:30 AM PDT 23	May 26 02:10:31 AM PDT 23	42356665 ps
T105	/workspace/coverage/cover_reg_top/20.usbdev_intr_test.3796909591	May 26 02:10:31 AM PDT 23	May 26 02:10:33 AM PDT 23	87425483 ps
T106	/workspace/coverage/cover_reg_top/31.usbdev_intr_test.3970303886	May 26 02:10:30 AM PDT 23	May 26 02:10:31 AM PDT 23	18303263 ps
T107	/workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.3987504582	May 26 02:10:30 AM PDT 23	May 26 02:10:32 AM PDT 23	158412463 ps
T108	/workspace/coverage/cover_reg_top/4.usbdev_csr_rw.3971663046	May 26 02:09:28 AM PDT 23	May 26 02:09:30 AM PDT 23	39768268 ps
T109	/workspace/coverage/cover_reg_top/8.usbdev_intr_test.424742855	May 26 02:09:28 AM PDT 23	May 26 02:09:30 AM PDT 23	19019923 ps
T110	/workspace/coverage/cover_reg_top/37.usbdev_intr_test.1361137729	May 26 02:10:23 AM PDT 23	May 26 02:10:24 AM PDT 23	40098552 ps
T111	/workspace/coverage/cover_reg_top/14.usbdev_tl_errors.985117603	May 26 02:10:26 AM PDT 23	May 26 02:10:28 AM PDT 23	158842527 ps
T112	/workspace/coverage/cover_reg_top/36.usbdev_intr_test.3891830603	May 26 02:10:30 AM PDT 23	May 26 02:10:31 AM PDT 23	15053011 ps
T113	/workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2708457248	May 26 02:09:38 AM PDT 23	May 26 02:09:39 AM PDT 23	55074818 ps
T114	/workspace/coverage/cover_reg_top/0.usbdev_tl_errors.2234644097	May 26 02:08:57 AM PDT 23	May 26 02:09:00 AM PDT 23	306820965 ps
T14	/workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.2705255405	May 26 02:08:59 AM PDT 23	May 26 02:09:00 AM PDT 23	39398572 ps
T115	/workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1205304631	May 26 02:10:31 AM PDT 23	May 26 02:10:33 AM PDT 23	111241416 ps
T116	/workspace/coverage/cover_reg_top/1.usbdev_tl_errors.3348293920	May 26 02:08:59 AM PDT 23	May 26 02:09:01 AM PDT 23	210358764 ps
T117	/workspace/coverage/cover_reg_top/46.usbdev_intr_test.1448528600	May 26 02:10:21 AM PDT 23	May 26 02:10:22 AM PDT 23	12618893 ps
T118	/workspace/coverage/cover_reg_top/27.usbdev_intr_test.2901491749	May 26 02:10:29 AM PDT 23	May 26 02:10:29 AM PDT 23	19534251 ps
T119	/workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1270992982	May 26 02:09:26 AM PDT 23	May 26 02:09:28 AM PDT 23	69772855 ps
T120	/workspace/coverage/cover_reg_top/45.usbdev_intr_test.1272263932	May 26 02:10:21 AM PDT 23	May 26 02:10:22 AM PDT 23	26684511 ps
T121	/workspace/coverage/cover_reg_top/5.usbdev_tl_errors.456340798	May 26 02:09:31 AM PDT 23	May 26 02:09:33 AM PDT 23	59879971 ps
T122	/workspace/coverage/cover_reg_top/6.usbdev_tl_errors.829699354	May 26 02:09:32 AM PDT 23	May 26 02:09:37 AM PDT 23	225180344 ps
T123	/workspace/coverage/cover_reg_top/39.usbdev_intr_test.3449344255	May 26 02:10:22 AM PDT 23	May 26 02:10:23 AM PDT 23	42551145 ps
T124	/workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.3035023701	May 26 02:09:41 AM PDT 23	May 26 02:09:42 AM PDT 23	65935935 ps
T125	/workspace/coverage/cover_reg_top/12.usbdev_tl_errors.1332112405	May 26 02:10:23 AM PDT 23	May 26 02:10:25 AM PDT 23	153100615 ps
T126	/workspace/coverage/cover_reg_top/13.usbdev_csr_rw.1600578608	May 26 02:10:32 AM PDT 23	May 26 02:10:33 AM PDT 23	31949171 ps
T127	/workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2766306676	May 26 02:09:31 AM PDT 23	May 26 02:09:36 AM PDT 23	128427629 ps
T128	/workspace/coverage/cover_reg_top/4.usbdev_tl_errors.4176385399	May 26 02:09:36 AM PDT 23	May 26 02:09:39 AM PDT 23	298129275 ps
T15	/workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3081446016	May 26 02:09:29 AM PDT 23	May 26 02:09:30 AM PDT 23	30945608 ps
T129	/workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.1775072185	May 26 02:08:58 AM PDT 23	May 26 02:09:00 AM PDT 23	59641364 ps
T130	/workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.2578957757	May 26 02:09:35 AM PDT 23	May 26 02:09:37 AM PDT 23	119858300 ps
T69	/workspace/coverage/cover_reg_top/43.usbdev_intr_test.4099698004	May 26 02:10:21 AM PDT 23	May 26 02:10:22 AM PDT 23	16711260 ps
T131	/workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.1462940546	May 26 02:10:26 AM PDT 23	May 26 02:10:27 AM PDT 23	75754973 ps
T132	/workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.4248353559	May 26 02:08:57 AM PDT 23	May 26 02:08:59 AM PDT 23	130659657 ps
T133	/workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.3422672781	May 26 02:08:58 AM PDT 23	May 26 02:08:59 AM PDT 23	34272741 ps
T134	/workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3903963251	May 26 02:09:32 AM PDT 23	May 26 02:09:38 AM PDT 23	386839883 ps
T45	/workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.1476175977	May 26 02:10:30 AM PDT 23	May 26 02:10:35 AM PDT 23	471316142 ps
T135	/workspace/coverage/cover_reg_top/3.usbdev_mem_walk.633616057	May 26 02:09:27 AM PDT 23	May 26 02:09:30 AM PDT 23	370624493 ps
T136	/workspace/coverage/cover_reg_top/10.usbdev_intr_test.192542768	May 26 02:09:31 AM PDT 23	May 26 02:09:31 AM PDT 23	20559076 ps
T137	/workspace/coverage/cover_reg_top/48.usbdev_intr_test.2858265987	May 26 02:10:27 AM PDT 23	May 26 02:10:28 AM PDT 23	15248346 ps
T138	/workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.339003387	May 26 02:10:28 AM PDT 23	May 26 02:10:29 AM PDT 23	73060390 ps
T139	/workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.3410900250	May 26 02:08:59 AM PDT 23	May 26 02:09:01 AM PDT 23	100993367 ps
T140	/workspace/coverage/cover_reg_top/47.usbdev_intr_test.3911267052	May 26 02:10:21 AM PDT 23	May 26 02:10:22 AM PDT 23	26439108 ps
T141	/workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.1898159040	May 26 02:09:28 AM PDT 23	May 26 02:09:35 AM PDT 23	804167959 ps
T142	/workspace/coverage/cover_reg_top/34.usbdev_intr_test.964580463	May 26 02:10:30 AM PDT 23	May 26 02:10:31 AM PDT 23	28163643 ps
T143	/workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3607365238	May 26 02:10:35 AM PDT 23	May 26 02:10:38 AM PDT 23	68248267 ps
T144	/workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.4018101128	May 26 02:09:40 AM PDT 23	May 26 02:09:45 AM PDT 23	894205165 ps
T145	/workspace/coverage/cover_reg_top/12.usbdev_intr_test.1478763844	May 26 02:10:29 AM PDT 23	May 26 02:10:30 AM PDT 23	16350246 ps
T146	/workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.676262833	May 26 02:09:29 AM PDT 23	May 26 02:09:31 AM PDT 23	31036888 ps
T147	/workspace/coverage/cover_reg_top/7.usbdev_csr_rw.2268680367	May 26 02:09:41 AM PDT 23	May 26 02:09:43 AM PDT 23	54736774 ps
T148	/workspace/coverage/cover_reg_top/24.usbdev_intr_test.3718103811	May 26 02:10:30 AM PDT 23	May 26 02:10:30 AM PDT 23	13145631 ps
T149	/workspace/coverage/cover_reg_top/2.usbdev_intr_test.1672727641	May 26 02:08:59 AM PDT 23	May 26 02:09:00 AM PDT 23	12436175 ps
T150	/workspace/coverage/cover_reg_top/9.usbdev_tl_errors.2488220071	May 26 02:09:31 AM PDT 23	May 26 02:09:34 AM PDT 23	153803217 ps
T151	/workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.3663351267	May 26 02:09:29 AM PDT 23	May 26 02:09:31 AM PDT 23	49613456 ps
T152	/workspace/coverage/cover_reg_top/40.usbdev_intr_test.192486462	May 26 02:10:23 AM PDT 23	May 26 02:10:24 AM PDT 23	11908679 ps
T153	/workspace/coverage/cover_reg_top/33.usbdev_intr_test.2883997539	May 26 02:10:24 AM PDT 23	May 26 02:10:25 AM PDT 23	17554902 ps
T154	/workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2134639230	May 26 02:09:40 AM PDT 23	May 26 02:09:41 AM PDT 23	26024656 ps

Test location	/workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3809581762
Short name	T2
Test name
Test status
Simulation time	67069471 ps
CPU time	1.3 seconds
Started	May 26 02:10:27 AM PDT 23
Finished	May 26 02:10:29 AM PDT 23
Peak memory	201256 kb
Host	smart-21b483e8-4cac-478f-b1e2-4f8b50cbaa02
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809581762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_ csr_outstanding.3809581762
Directory	/workspace/17.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/41.usbdev_intr_test.2275665204
Short name	T17
Test name
Test status
Simulation time	33940420 ps
CPU time	0.63 seconds
Started	May 26 02:10:22 AM PDT 23
Finished	May 26 02:10:23 AM PDT 23
Peak memory	196680 kb
Host	smart-aa9d6428-3d55-483e-b7d9-c0d002f7dc77
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2275665204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.2275665204
Directory	/workspace/41.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_tl_errors.92259497
Short name	T27
Test name
Test status
Simulation time	155577669 ps
CPU time	1.92 seconds
Started	May 26 02:08:59 AM PDT 23
Finished	May 26 02:09:01 AM PDT 23
Peak memory	201244 kb
Host	smart-15ede807-1d50-4a3d-988b-27a9e15054a7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=92259497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.92259497
Directory	/workspace/2.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_intr_test.114205626
Short name	T20
Test name
Test status
Simulation time	33061882 ps
CPU time	0.63 seconds
Started	May 26 02:10:27 AM PDT 23
Finished	May 26 02:10:27 AM PDT 23
Peak memory	196820 kb
Host	smart-b96e6050-1848-4d88-99d4-75f7dbef171e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=114205626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.114205626
Directory	/workspace/15.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_csr_rw.3756765229
Short name	T34
Test name
Test status
Simulation time	58813968 ps
CPU time	0.98 seconds
Started	May 26 02:10:27 AM PDT 23
Finished	May 26 02:10:28 AM PDT 23
Peak memory	200584 kb
Host	smart-20b1566c-832f-4318-9554-b3eb46de0ecf
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756765229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.3756765229
Directory	/workspace/17.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.1476175977
Short name	T45
Test name
Test status
Simulation time	471316142 ps
CPU time	4.87 seconds
Started	May 26 02:10:30 AM PDT 23
Finished	May 26 02:10:35 AM PDT 23
Peak memory	201212 kb
Host	smart-1659b6dc-f418-49df-9d73-c0443c298609
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1476175977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.1476175977
Directory	/workspace/15.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_intr_test.2950665997
Short name	T62
Test name
Test status
Simulation time	16777763 ps
CPU time	0.58 seconds
Started	May 26 02:08:58 AM PDT 23
Finished	May 26 02:08:59 AM PDT 23
Peak memory	196720 kb
Host	smart-89cfa6f2-09c9-4c79-8d27-86981269e4e5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2950665997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.2950665997
Directory	/workspace/1.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.3943641601
Short name	T10
Test name
Test status
Simulation time	32175053 ps
CPU time	0.66 seconds
Started	May 26 02:08:59 AM PDT 23
Finished	May 26 02:09:00 AM PDT 23
Peak memory	197960 kb
Host	smart-3e2e2718-6b8f-42fb-b770-75b32223ed48
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943641601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.3943641601
Directory	/workspace/0.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3227861230
Short name	T23
Test name
Test status
Simulation time	22912869 ps
CPU time	1.34 seconds
Started	May 26 02:10:21 AM PDT 23
Finished	May 26 02:10:23 AM PDT 23
Peak memory	209736 kb
Host	smart-f100b96d-a51f-4507-86f1-d736510b42a8
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227861230 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_mem_rw_with_rand_reset.3227861230
Directory	/workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_intr_test.1940290571
Short name	T65
Test name
Test status
Simulation time	12696265 ps
CPU time	0.6 seconds
Started	May 26 02:10:30 AM PDT 23
Finished	May 26 02:10:31 AM PDT 23
Peak memory	196740 kb
Host	smart-0ed60ba4-c3c9-4427-ae22-b9e9fc156911
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1940290571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.1940290571
Directory	/workspace/13.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.usbdev_intr_test.1165654431
Short name	T74
Test name
Test status
Simulation time	18012486 ps
CPU time	0.64 seconds
Started	May 26 02:10:29 AM PDT 23
Finished	May 26 02:10:30 AM PDT 23
Peak memory	196892 kb
Host	smart-e77f5a40-174e-4767-ad19-fb2104a27117
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1165654431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.1165654431
Directory	/workspace/32.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3081446016
Short name	T15
Test name
Test status
Simulation time	30945608 ps
CPU time	0.7 seconds
Started	May 26 02:09:29 AM PDT 23
Finished	May 26 02:09:30 AM PDT 23
Peak memory	199620 kb
Host	smart-b3dc3b8c-7235-4f7a-ab1f-6d61f21bf256
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081446016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.3081446016
Directory	/workspace/2.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_tl_errors.470408333
Short name	T7
Test name
Test status
Simulation time	83321353 ps
CPU time	1.66 seconds
Started	May 26 02:10:24 AM PDT 23
Finished	May 26 02:10:26 AM PDT 23
Peak memory	201312 kb
Host	smart-682bcb67-e021-47e5-9652-323535793cae
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=470408333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.470408333
Directory	/workspace/13.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_tl_errors.3348293920
Short name	T116
Test name
Test status
Simulation time	210358764 ps
CPU time	2.34 seconds
Started	May 26 02:08:59 AM PDT 23
Finished	May 26 02:09:01 AM PDT 23
Peak memory	201308 kb
Host	smart-23709575-1697-40b1-9504-c3c4301bfa7d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3348293920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.3348293920
Directory	/workspace/1.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.135413049
Short name	T50
Test name
Test status
Simulation time	357474547 ps
CPU time	3.38 seconds
Started	May 26 02:08:59 AM PDT 23
Finished	May 26 02:09:03 AM PDT 23
Peak memory	201232 kb
Host	smart-2fe833d8-abfe-486e-85d6-d991b8c1feed
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135413049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.135413049
Directory	/workspace/0.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.181162655
Short name	T60
Test name
Test status
Simulation time	85112961 ps
CPU time	3.13 seconds
Started	May 26 02:09:00 AM PDT 23
Finished	May 26 02:09:03 AM PDT 23
Peak memory	209584 kb
Host	smart-f76ce99d-bb29-46f9-995b-e78a87c1f0f4
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181162655 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_mem_rw_with_rand_reset.181162655
Directory	/workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1093482143
Short name	T13
Test name
Test status
Simulation time	32481793 ps
CPU time	0.77 seconds
Started	May 26 02:08:59 AM PDT 23
Finished	May 26 02:09:00 AM PDT 23
Peak memory	201084 kb
Host	smart-a43dc6d3-165c-4f92-a9ae-d3045840384b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093482143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.1093482143
Directory	/workspace/0.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_intr_test.4266811175
Short name	T81
Test name
Test status
Simulation time	15620439 ps
CPU time	0.57 seconds
Started	May 26 02:08:58 AM PDT 23
Finished	May 26 02:08:59 AM PDT 23
Peak memory	196564 kb
Host	smart-9f076cae-13b9-40ba-be24-ba8f15352c82
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4266811175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.4266811175
Directory	/workspace/0.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.1358340144
Short name	T3
Test name
Test status
Simulation time	57761490 ps
CPU time	1.35 seconds
Started	May 26 02:08:58 AM PDT 23
Finished	May 26 02:08:59 AM PDT 23
Peak memory	198036 kb
Host	smart-d4c745a7-1631-4492-a7d3-fad682b29183
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1358340144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.1358340144
Directory	/workspace/0.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_mem_walk.1437158798
Short name	T99
Test name
Test status
Simulation time	242555607 ps
CPU time	2.6 seconds
Started	May 26 02:08:58 AM PDT 23
Finished	May 26 02:09:00 AM PDT 23
Peak memory	201168 kb
Host	smart-77582c8b-3734-46b9-9ec3-1bf18abaedc6
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1437158798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.1437158798
Directory	/workspace/0.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.3410900250
Short name	T139
Test name
Test status
Simulation time	100993367 ps
CPU time	1.01 seconds
Started	May 26 02:08:59 AM PDT 23
Finished	May 26 02:09:01 AM PDT 23
Peak memory	200312 kb
Host	smart-9b9c21df-19cc-4159-b70a-a9999bea159f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410900250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_c sr_outstanding.3410900250
Directory	/workspace/0.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_tl_errors.2234644097
Short name	T114
Test name
Test status
Simulation time	306820965 ps
CPU time	2.54 seconds
Started	May 26 02:08:57 AM PDT 23
Finished	May 26 02:09:00 AM PDT 23
Peak memory	201152 kb
Host	smart-60a3e306-4e56-4842-98fe-1343482cb562
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2234644097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.2234644097
Directory	/workspace/0.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.1775072185
Short name	T129
Test name
Test status
Simulation time	59641364 ps
CPU time	1.77 seconds
Started	May 26 02:08:58 AM PDT 23
Finished	May 26 02:09:00 AM PDT 23
Peak memory	199716 kb
Host	smart-c65006f4-94ef-4245-83d8-e6d3f9cbd377
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775072185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.1775072185
Directory	/workspace/1.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.1754454045
Short name	T52
Test name
Test status
Simulation time	888110176 ps
CPU time	5.18 seconds
Started	May 26 02:08:59 AM PDT 23
Finished	May 26 02:09:04 AM PDT 23
Peak memory	201156 kb
Host	smart-465e475d-724e-428d-aee4-e41882eea9a3
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754454045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.1754454045
Directory	/workspace/1.usbdev_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.2705255405
Short name	T14
Test name
Test status
Simulation time	39398572 ps
CPU time	0.75 seconds
Started	May 26 02:08:59 AM PDT 23
Finished	May 26 02:09:00 AM PDT 23
Peak memory	199112 kb
Host	smart-890bba2d-5444-4b48-a504-c3590ff26d9c
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705255405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.2705255405
Directory	/workspace/1.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.3422672781
Short name	T133
Test name
Test status
Simulation time	34272741 ps
CPU time	0.87 seconds
Started	May 26 02:08:58 AM PDT 23
Finished	May 26 02:08:59 AM PDT 23
Peak memory	201064 kb
Host	smart-21baedab-ac75-4abd-b5d1-6bd07cad7a3a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422672781 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_mem_rw_with_rand_reset.3422672781
Directory	/workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_rw.1199414436
Short name	T12
Test name
Test status
Simulation time	21421459 ps
CPU time	0.88 seconds
Started	May 26 02:08:59 AM PDT 23
Finished	May 26 02:09:00 AM PDT 23
Peak memory	201016 kb
Host	smart-8ce36c7e-4f11-4826-9479-e63bc9c87d24
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199414436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.1199414436
Directory	/workspace/1.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.340499025
Short name	T26
Test name
Test status
Simulation time	187437545 ps
CPU time	2.26 seconds
Started	May 26 02:08:58 AM PDT 23
Finished	May 26 02:09:01 AM PDT 23
Peak memory	198116 kb
Host	smart-91ba0d35-0b26-4af1-8ec7-b95efa189c50
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=340499025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.340499025
Directory	/workspace/1.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_mem_walk.2834448033
Short name	T72
Test name
Test status
Simulation time	143589028 ps
CPU time	3.72 seconds
Started	May 26 02:08:59 AM PDT 23
Finished	May 26 02:09:03 AM PDT 23
Peak memory	201208 kb
Host	smart-4cf43725-77a2-42ab-9b4d-48d01348da6c
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2834448033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.2834448033
Directory	/workspace/1.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.4248353559
Short name	T132
Test name
Test status
Simulation time	130659657 ps
CPU time	1 seconds
Started	May 26 02:08:57 AM PDT 23
Finished	May 26 02:08:59 AM PDT 23
Peak memory	200484 kb
Host	smart-6381c829-a43e-42c2-8fbd-44e81be40a69
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248353559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_c sr_outstanding.4248353559
Directory	/workspace/1.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.3913028584
Short name	T98
Test name
Test status
Simulation time	50817485 ps
CPU time	1.32 seconds
Started	May 26 02:10:24 AM PDT 23
Finished	May 26 02:10:25 AM PDT 23
Peak memory	201180 kb
Host	smart-e06bc8e0-1847-4438-86fd-624d5e5a2caf
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913028584 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_mem_rw_with_rand_reset.3913028584
Directory	/workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3880065007
Short name	T92
Test name
Test status
Simulation time	17577001 ps
CPU time	0.76 seconds
Started	May 26 02:10:27 AM PDT 23
Finished	May 26 02:10:28 AM PDT 23
Peak memory	200688 kb
Host	smart-e0aa51ea-cde0-4e47-b290-6e8448329625
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880065007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.3880065007
Directory	/workspace/10.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_intr_test.192542768
Short name	T136
Test name
Test status
Simulation time	20559076 ps
CPU time	0.58 seconds
Started	May 26 02:09:31 AM PDT 23
Finished	May 26 02:09:31 AM PDT 23
Peak memory	198076 kb
Host	smart-bca9684a-1b35-4485-be2b-8e5ce504f845
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=192542768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.192542768
Directory	/workspace/10.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2961388010
Short name	T89
Test name
Test status
Simulation time	60739650 ps
CPU time	0.99 seconds
Started	May 26 02:10:23 AM PDT 23
Finished	May 26 02:10:24 AM PDT 23
Peak memory	200352 kb
Host	smart-d4bf5a2d-0d0a-4a27-b394-35ded6e795e6
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961388010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_ csr_outstanding.2961388010
Directory	/workspace/10.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_tl_errors.17407514
Short name	T33
Test name
Test status
Simulation time	128747123 ps
CPU time	1.42 seconds
Started	May 26 02:09:32 AM PDT 23
Finished	May 26 02:09:33 AM PDT 23
Peak memory	201372 kb
Host	smart-603f19a3-58d5-4f8c-8594-b6a77b5046c5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=17407514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.17407514
Directory	/workspace/10.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_csr_rw.2838295878
Short name	T39
Test name
Test status
Simulation time	63022273 ps
CPU time	0.95 seconds
Started	May 26 02:10:22 AM PDT 23
Finished	May 26 02:10:23 AM PDT 23
Peak memory	200976 kb
Host	smart-1c3d112a-f20d-44f9-b20f-f7f61361936d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838295878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.2838295878
Directory	/workspace/11.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_intr_test.1101015946
Short name	T73
Test name
Test status
Simulation time	22937786 ps
CPU time	0.59 seconds
Started	May 26 02:10:22 AM PDT 23
Finished	May 26 02:10:23 AM PDT 23
Peak memory	196744 kb
Host	smart-7ad8bd91-fa5a-4f91-8e05-dbe8559e1d23
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1101015946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.1101015946
Directory	/workspace/11.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.1305086609
Short name	T16
Test name
Test status
Simulation time	80068153 ps
CPU time	1 seconds
Started	May 26 02:10:24 AM PDT 23
Finished	May 26 02:10:25 AM PDT 23
Peak memory	199580 kb
Host	smart-12c6840c-10de-49cc-834c-407f3480a228
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305086609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_ csr_outstanding.1305086609
Directory	/workspace/11.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_tl_errors.1862838146
Short name	T94
Test name
Test status
Simulation time	159109338 ps
CPU time	2.19 seconds
Started	May 26 02:10:23 AM PDT 23
Finished	May 26 02:10:26 AM PDT 23
Peak memory	201212 kb
Host	smart-d7a91561-533b-4d96-a08d-5622b3a1615d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1862838146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.1862838146
Directory	/workspace/11.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.2549979344
Short name	T46
Test name
Test status
Simulation time	24575182 ps
CPU time	0.87 seconds
Started	May 26 02:10:24 AM PDT 23
Finished	May 26 02:10:25 AM PDT 23
Peak memory	201088 kb
Host	smart-eb2972ff-31e0-4ccc-af1a-dbd24534d7ad
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549979344 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_mem_rw_with_rand_reset.2549979344
Directory	/workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_csr_rw.1295787650
Short name	T101
Test name
Test status
Simulation time	146938947 ps
CPU time	0.93 seconds
Started	May 26 02:10:24 AM PDT 23
Finished	May 26 02:10:26 AM PDT 23
Peak memory	200788 kb
Host	smart-816d529c-f74d-4c7d-8434-9d1884d9bd61
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295787650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.1295787650
Directory	/workspace/12.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_intr_test.1478763844
Short name	T145
Test name
Test status
Simulation time	16350246 ps
CPU time	0.63 seconds
Started	May 26 02:10:29 AM PDT 23
Finished	May 26 02:10:30 AM PDT 23
Peak memory	198076 kb
Host	smart-b72202d6-b967-4dbe-8423-08511e895f0b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1478763844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.1478763844
Directory	/workspace/12.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3368968734
Short name	T80
Test name
Test status
Simulation time	146927984 ps
CPU time	1.51 seconds
Started	May 26 02:10:24 AM PDT 23
Finished	May 26 02:10:26 AM PDT 23
Peak memory	201272 kb
Host	smart-fd397f63-6a52-4004-91ba-2e1bc3738b6c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368968734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_ csr_outstanding.3368968734
Directory	/workspace/12.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_tl_errors.1332112405
Short name	T125
Test name
Test status
Simulation time	153100615 ps
CPU time	1.93 seconds
Started	May 26 02:10:23 AM PDT 23
Finished	May 26 02:10:25 AM PDT 23
Peak memory	201380 kb
Host	smart-10250e9a-4652-4d9c-9ad4-dc30e37292a2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1332112405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.1332112405
Directory	/workspace/12.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.151222523
Short name	T78
Test name
Test status
Simulation time	26339053 ps
CPU time	0.94 seconds
Started	May 26 02:10:30 AM PDT 23
Finished	May 26 02:10:31 AM PDT 23
Peak memory	201124 kb
Host	smart-9dc8680d-32c0-4d44-b438-921415a09b7e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151222523 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_mem_rw_with_rand_reset.151222523
Directory	/workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_csr_rw.1600578608
Short name	T126
Test name
Test status
Simulation time	31949171 ps
CPU time	0.76 seconds
Started	May 26 02:10:32 AM PDT 23
Finished	May 26 02:10:33 AM PDT 23
Peak memory	199244 kb
Host	smart-9a97f41c-a020-4d7d-8285-483e31a2fdd0
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600578608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.1600578608
Directory	/workspace/13.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.3987504582
Short name	T107
Test name
Test status
Simulation time	158412463 ps
CPU time	1.56 seconds
Started	May 26 02:10:30 AM PDT 23
Finished	May 26 02:10:32 AM PDT 23
Peak memory	200628 kb
Host	smart-cd3ed8a2-6d73-4a3f-82d8-c0aad18560a4
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987504582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_ csr_outstanding.3987504582
Directory	/workspace/13.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2078494273
Short name	T84
Test name
Test status
Simulation time	26492291 ps
CPU time	1.43 seconds
Started	May 26 02:10:25 AM PDT 23
Finished	May 26 02:10:27 AM PDT 23
Peak memory	201256 kb
Host	smart-d21f12b7-aac9-459a-98f4-182a486167ec
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078494273 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_mem_rw_with_rand_reset.2078494273
Directory	/workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_csr_rw.4010684713
Short name	T87
Test name
Test status
Simulation time	31995489 ps
CPU time	0.93 seconds
Started	May 26 02:10:36 AM PDT 23
Finished	May 26 02:10:37 AM PDT 23
Peak memory	200916 kb
Host	smart-f75c3bc2-cd09-44cb-9b2c-b65f0364364f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010684713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.4010684713
Directory	/workspace/14.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_intr_test.1714761187
Short name	T54
Test name
Test status
Simulation time	22342755 ps
CPU time	0.61 seconds
Started	May 26 02:10:26 AM PDT 23
Finished	May 26 02:10:27 AM PDT 23
Peak memory	196644 kb
Host	smart-8b3697a2-b52a-4061-b46e-f5254f71b524
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1714761187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.1714761187
Directory	/workspace/14.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.2727490373
Short name	T8
Test name
Test status
Simulation time	46717373 ps
CPU time	1.34 seconds
Started	May 26 02:10:26 AM PDT 23
Finished	May 26 02:10:28 AM PDT 23
Peak memory	201084 kb
Host	smart-4905558d-c415-4dbe-8e93-e74db11c4428
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727490373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_ csr_outstanding.2727490373
Directory	/workspace/14.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_tl_errors.985117603
Short name	T111
Test name
Test status
Simulation time	158842527 ps
CPU time	1.66 seconds
Started	May 26 02:10:26 AM PDT 23
Finished	May 26 02:10:28 AM PDT 23
Peak memory	201240 kb
Host	smart-fda58d6c-0eb9-4dca-abdf-53a5bdf54517
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=985117603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.985117603
Directory	/workspace/14.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.3346705235
Short name	T48
Test name
Test status
Simulation time	44810000 ps
CPU time	0.9 seconds
Started	May 26 02:10:32 AM PDT 23
Finished	May 26 02:10:33 AM PDT 23
Peak memory	201116 kb
Host	smart-eea37e23-9281-4359-87ca-90ef187aa85d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346705235 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_mem_rw_with_rand_reset.3346705235
Directory	/workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_csr_rw.2032661888
Short name	T9
Test name
Test status
Simulation time	28725019 ps
CPU time	0.97 seconds
Started	May 26 02:10:26 AM PDT 23
Finished	May 26 02:10:28 AM PDT 23
Peak memory	200936 kb
Host	smart-6209bdb6-8b8c-4094-8a82-af88cddfa7de
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032661888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.2032661888
Directory	/workspace/15.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1205304631
Short name	T115
Test name
Test status
Simulation time	111241416 ps
CPU time	1.48 seconds
Started	May 26 02:10:31 AM PDT 23
Finished	May 26 02:10:33 AM PDT 23
Peak memory	200580 kb
Host	smart-2d0622e6-0300-4671-ae18-e826d8eaa9e6
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205304631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_ csr_outstanding.1205304631
Directory	/workspace/15.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_tl_errors.4008817786
Short name	T32
Test name
Test status
Simulation time	136841494 ps
CPU time	1.86 seconds
Started	May 26 02:10:27 AM PDT 23
Finished	May 26 02:10:29 AM PDT 23
Peak memory	201244 kb
Host	smart-a7b6487c-0bf9-4189-a7e4-b1036daf1c59
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4008817786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.4008817786
Directory	/workspace/15.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.1089574157
Short name	T4
Test name
Test status
Simulation time	33866293 ps
CPU time	0.9 seconds
Started	May 26 02:10:31 AM PDT 23
Finished	May 26 02:10:32 AM PDT 23
Peak memory	201116 kb
Host	smart-d12c0320-e9f6-4e45-a5c5-f66135505a07
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089574157 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_mem_rw_with_rand_reset.1089574157
Directory	/workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2060007860
Short name	T93
Test name
Test status
Simulation time	55268991 ps
CPU time	0.95 seconds
Started	May 26 02:10:36 AM PDT 23
Finished	May 26 02:10:37 AM PDT 23
Peak memory	200972 kb
Host	smart-aceeac0d-fd77-4d1c-9cc1-04b4b538cf4c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060007860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.2060007860
Directory	/workspace/16.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_intr_test.171539440
Short name	T18
Test name
Test status
Simulation time	18296471 ps
CPU time	0.6 seconds
Started	May 26 02:10:26 AM PDT 23
Finished	May 26 02:10:27 AM PDT 23
Peak memory	198028 kb
Host	smart-521dc412-0ec1-45bf-912a-6c3c208ae0dd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=171539440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.171539440
Directory	/workspace/16.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.1462940546
Short name	T131
Test name
Test status
Simulation time	75754973 ps
CPU time	1.02 seconds
Started	May 26 02:10:26 AM PDT 23
Finished	May 26 02:10:27 AM PDT 23
Peak memory	201244 kb
Host	smart-b92dab5a-14cd-441b-90d9-b2582cdefe8d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462940546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_ csr_outstanding.1462940546
Directory	/workspace/16.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3607365238
Short name	T143
Test name
Test status
Simulation time	68248267 ps
CPU time	1.62 seconds
Started	May 26 02:10:35 AM PDT 23
Finished	May 26 02:10:38 AM PDT 23
Peak memory	201316 kb
Host	smart-a49c224f-2f47-4c18-92fe-833ad7bbef5b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3607365238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.3607365238
Directory	/workspace/16.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.2294509977
Short name	T71
Test name
Test status
Simulation time	17873531 ps
CPU time	0.91 seconds
Started	May 26 02:10:32 AM PDT 23
Finished	May 26 02:10:33 AM PDT 23
Peak memory	201116 kb
Host	smart-ca70c8c1-5aec-427d-bdd9-9632d63e15b2
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294509977 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_mem_rw_with_rand_reset.2294509977
Directory	/workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_intr_test.1028046125
Short name	T82
Test name
Test status
Simulation time	18722422 ps
CPU time	0.62 seconds
Started	May 26 02:10:31 AM PDT 23
Finished	May 26 02:10:32 AM PDT 23
Peak memory	198100 kb
Host	smart-3746c925-2fe1-4697-9a8c-637e68707b46
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1028046125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.1028046125
Directory	/workspace/17.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_tl_errors.1860331251
Short name	T29
Test name
Test status
Simulation time	308058968 ps
CPU time	2.89 seconds
Started	May 26 02:10:31 AM PDT 23
Finished	May 26 02:10:34 AM PDT 23
Peak memory	201320 kb
Host	smart-ed86c1ec-3302-489d-bf10-af923be306c3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1860331251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.1860331251
Directory	/workspace/17.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.3499435624
Short name	T24
Test name
Test status
Simulation time	233181612 ps
CPU time	2.97 seconds
Started	May 26 02:10:30 AM PDT 23
Finished	May 26 02:10:33 AM PDT 23
Peak memory	209408 kb
Host	smart-4a9e20d2-7e5a-4e4e-9041-2d8dec5113ed
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499435624 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_mem_rw_with_rand_reset.3499435624
Directory	/workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_csr_rw.3098426478
Short name	T37
Test name
Test status
Simulation time	48798261 ps
CPU time	0.76 seconds
Started	May 26 02:10:26 AM PDT 23
Finished	May 26 02:10:27 AM PDT 23
Peak memory	200500 kb
Host	smart-59a27391-8f65-42c2-bd38-27d1d77d9068
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098426478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.3098426478
Directory	/workspace/18.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_intr_test.1382675485
Short name	T63
Test name
Test status
Simulation time	37440309 ps
CPU time	0.64 seconds
Started	May 26 02:10:30 AM PDT 23
Finished	May 26 02:10:31 AM PDT 23
Peak memory	197984 kb
Host	smart-612cb679-49d4-4189-9910-c525dac171a6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1382675485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.1382675485
Directory	/workspace/18.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.339003387
Short name	T138
Test name
Test status
Simulation time	73060390 ps
CPU time	1.02 seconds
Started	May 26 02:10:28 AM PDT 23
Finished	May 26 02:10:29 AM PDT 23
Peak memory	201264 kb
Host	smart-c9381d0a-7c16-46b3-9b0c-6f83fc20def9
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339003387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_c sr_outstanding.339003387
Directory	/workspace/18.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3744102917
Short name	T30
Test name
Test status
Simulation time	206322503 ps
CPU time	2.46 seconds
Started	May 26 02:10:30 AM PDT 23
Finished	May 26 02:10:33 AM PDT 23
Peak memory	201320 kb
Host	smart-ad08c62c-f254-4031-8660-814a8889ea95
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3744102917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.3744102917
Directory	/workspace/18.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2148524708
Short name	T57
Test name
Test status
Simulation time	25683633 ps
CPU time	0.92 seconds
Started	May 26 02:10:30 AM PDT 23
Finished	May 26 02:10:31 AM PDT 23
Peak memory	201004 kb
Host	smart-798cfeb4-2ad5-4e51-b542-ee25cf216060
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148524708 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_mem_rw_with_rand_reset.2148524708
Directory	/workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_csr_rw.1873729839
Short name	T96
Test name
Test status
Simulation time	65033807 ps
CPU time	0.84 seconds
Started	May 26 02:10:36 AM PDT 23
Finished	May 26 02:10:37 AM PDT 23
Peak memory	200856 kb
Host	smart-5fc219af-2329-4d8a-89e2-144fae9662a9
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873729839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.1873729839
Directory	/workspace/19.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_intr_test.2455863866
Short name	T53
Test name
Test status
Simulation time	41736413 ps
CPU time	0.62 seconds
Started	May 26 02:10:30 AM PDT 23
Finished	May 26 02:10:31 AM PDT 23
Peak memory	196728 kb
Host	smart-9646bdb0-81af-4fe8-9a45-ff729d6c1e0f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2455863866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.2455863866
Directory	/workspace/19.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.937238034
Short name	T43
Test name
Test status
Simulation time	81272175 ps
CPU time	1.06 seconds
Started	May 26 02:10:30 AM PDT 23
Finished	May 26 02:10:32 AM PDT 23
Peak memory	199664 kb
Host	smart-9593e8bc-1969-4cbe-bf81-287c01f55cfa
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937238034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_c sr_outstanding.937238034
Directory	/workspace/19.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3713605786
Short name	T28
Test name
Test status
Simulation time	47671548 ps
CPU time	1.63 seconds
Started	May 26 02:10:29 AM PDT 23
Finished	May 26 02:10:31 AM PDT 23
Peak memory	201252 kb
Host	smart-7ea34548-e61b-49f8-8c79-aadaa80ac760
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3713605786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.3713605786
Directory	/workspace/19.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2696886881
Short name	T35
Test name
Test status
Simulation time	120382178 ps
CPU time	2.92 seconds
Started	May 26 02:09:27 AM PDT 23
Finished	May 26 02:09:30 AM PDT 23
Peak memory	201148 kb
Host	smart-c4aa6b83-d8a2-41ae-809c-ef0b7c505a65
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696886881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.2696886881
Directory	/workspace/2.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.4018101128
Short name	T144
Test name
Test status
Simulation time	894205165 ps
CPU time	5 seconds
Started	May 26 02:09:40 AM PDT 23
Finished	May 26 02:09:45 AM PDT 23
Peak memory	201224 kb
Host	smart-4e3355fb-0508-447f-bb2e-673ba1701b1d
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018101128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.4018101128
Directory	/workspace/2.usbdev_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.3035023701
Short name	T124
Test name
Test status
Simulation time	65935935 ps
CPU time	1.44 seconds
Started	May 26 02:09:41 AM PDT 23
Finished	May 26 02:09:42 AM PDT 23
Peak memory	201316 kb
Host	smart-885a2dc5-3793-46a5-8146-03031d76dde8
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035023701 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_mem_rw_with_rand_reset.3035023701
Directory	/workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2708457248
Short name	T113
Test name
Test status
Simulation time	55074818 ps
CPU time	0.91 seconds
Started	May 26 02:09:38 AM PDT 23
Finished	May 26 02:09:39 AM PDT 23
Peak memory	200748 kb
Host	smart-b7e973dd-debb-4d05-aad1-2e6df701cb1f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708457248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.2708457248
Directory	/workspace/2.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_intr_test.1672727641
Short name	T149
Test name
Test status
Simulation time	12436175 ps
CPU time	0.62 seconds
Started	May 26 02:08:59 AM PDT 23
Finished	May 26 02:09:00 AM PDT 23
Peak memory	196680 kb
Host	smart-f9b15f43-9a06-45c4-abaf-f34b78a8c49b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1672727641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.1672727641
Directory	/workspace/2.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.2889648083
Short name	T91
Test name
Test status
Simulation time	143909127 ps
CPU time	2.33 seconds
Started	May 26 02:09:41 AM PDT 23
Finished	May 26 02:09:43 AM PDT 23
Peak memory	198272 kb
Host	smart-2bdf3903-c252-4802-89fb-1b654b8811d6
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2889648083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.2889648083
Directory	/workspace/2.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_mem_walk.1272666572
Short name	T70
Test name
Test status
Simulation time	488176623 ps
CPU time	3.99 seconds
Started	May 26 02:08:59 AM PDT 23
Finished	May 26 02:09:03 AM PDT 23
Peak memory	201156 kb
Host	smart-e4653e1c-d5a1-4b46-b911-5b25a89ee1dd
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1272666572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.1272666572
Directory	/workspace/2.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/20.usbdev_intr_test.3796909591
Short name	T105
Test name
Test status
Simulation time	87425483 ps
CPU time	0.65 seconds
Started	May 26 02:10:31 AM PDT 23
Finished	May 26 02:10:33 AM PDT 23
Peak memory	196732 kb
Host	smart-963c4f0e-de74-48fd-b9a0-3e868468d5a3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3796909591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.3796909591
Directory	/workspace/20.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.usbdev_intr_test.4275888082
Short name	T104
Test name
Test status
Simulation time	42356665 ps
CPU time	0.65 seconds
Started	May 26 02:10:30 AM PDT 23
Finished	May 26 02:10:31 AM PDT 23
Peak memory	197964 kb
Host	smart-8061ab53-cd85-4809-9c88-2bd45161cb85
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4275888082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.4275888082
Directory	/workspace/21.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.usbdev_intr_test.2016686680
Short name	T66
Test name
Test status
Simulation time	13474369 ps
CPU time	0.63 seconds
Started	May 26 02:10:30 AM PDT 23
Finished	May 26 02:10:31 AM PDT 23
Peak memory	196732 kb
Host	smart-3261a33c-8c51-4cb8-afb1-e0d50be47cd9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2016686680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.2016686680
Directory	/workspace/22.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.usbdev_intr_test.225394601
Short name	T75
Test name
Test status
Simulation time	17550993 ps
CPU time	0.61 seconds
Started	May 26 02:10:30 AM PDT 23
Finished	May 26 02:10:31 AM PDT 23
Peak memory	197988 kb
Host	smart-e8e8f839-c897-4e2a-85cf-85425b0dba90
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=225394601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.225394601
Directory	/workspace/23.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.usbdev_intr_test.3718103811
Short name	T148
Test name
Test status
Simulation time	13145631 ps
CPU time	0.61 seconds
Started	May 26 02:10:30 AM PDT 23
Finished	May 26 02:10:30 AM PDT 23
Peak memory	197956 kb
Host	smart-55365673-63c4-4a82-9a2e-88ff7fb169f4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3718103811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.3718103811
Directory	/workspace/24.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.usbdev_intr_test.995299123
Short name	T64
Test name
Test status
Simulation time	14538321 ps
CPU time	0.58 seconds
Started	May 26 02:10:30 AM PDT 23
Finished	May 26 02:10:30 AM PDT 23
Peak memory	196564 kb
Host	smart-184e6c3a-9441-4d18-9ef1-07dd39c058c6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=995299123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.995299123
Directory	/workspace/25.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.usbdev_intr_test.1996979730
Short name	T56
Test name
Test status
Simulation time	17917566 ps
CPU time	0.61 seconds
Started	May 26 02:10:30 AM PDT 23
Finished	May 26 02:10:31 AM PDT 23
Peak memory	198076 kb
Host	smart-dfa7ddfc-abba-49d3-abcc-2dc283c303f5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1996979730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.1996979730
Directory	/workspace/26.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.usbdev_intr_test.2901491749
Short name	T118
Test name
Test status
Simulation time	19534251 ps
CPU time	0.6 seconds
Started	May 26 02:10:29 AM PDT 23
Finished	May 26 02:10:29 AM PDT 23
Peak memory	198260 kb
Host	smart-d00258e5-ee68-4886-8441-acfb27613f5b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2901491749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.2901491749
Directory	/workspace/27.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.usbdev_intr_test.2085949106
Short name	T21
Test name
Test status
Simulation time	17661835 ps
CPU time	0.61 seconds
Started	May 26 02:10:30 AM PDT 23
Finished	May 26 02:10:31 AM PDT 23
Peak memory	197920 kb
Host	smart-fe8747e9-7ba1-4571-ab53-7377457457ac
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2085949106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.2085949106
Directory	/workspace/28.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.usbdev_intr_test.3297346067
Short name	T77
Test name
Test status
Simulation time	48668188 ps
CPU time	0.64 seconds
Started	May 26 02:10:25 AM PDT 23
Finished	May 26 02:10:26 AM PDT 23
Peak memory	196768 kb
Host	smart-e9942db2-11e3-493f-bb84-2dcd8d088a8f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3297346067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.3297346067
Directory	/workspace/29.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3903963251
Short name	T134
Test name
Test status
Simulation time	386839883 ps
CPU time	3.64 seconds
Started	May 26 02:09:32 AM PDT 23
Finished	May 26 02:09:38 AM PDT 23
Peak memory	201196 kb
Host	smart-8d215880-6e9e-4e6a-9e21-92d1de9c4f92
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903963251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.3903963251
Directory	/workspace/3.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.1898159040
Short name	T141
Test name
Test status
Simulation time	804167959 ps
CPU time	5.08 seconds
Started	May 26 02:09:28 AM PDT 23
Finished	May 26 02:09:35 AM PDT 23
Peak memory	201064 kb
Host	smart-9af4d913-fd0e-40ee-85bd-7eacdbecb2a3
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898159040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.1898159040
Directory	/workspace/3.usbdev_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3971078182
Short name	T22
Test name
Test status
Simulation time	27670498 ps
CPU time	0.67 seconds
Started	May 26 02:09:32 AM PDT 23
Finished	May 26 02:09:35 AM PDT 23
Peak memory	198304 kb
Host	smart-e3118378-6857-4297-ae9a-25a20a9d78a4
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971078182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.3971078182
Directory	/workspace/3.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.676262833
Short name	T146
Test name
Test status
Simulation time	31036888 ps
CPU time	1.51 seconds
Started	May 26 02:09:29 AM PDT 23
Finished	May 26 02:09:31 AM PDT 23
Peak memory	201256 kb
Host	smart-c3c1f85b-7351-4019-a167-322b88fc7b7a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676262833 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_mem_rw_with_rand_reset.676262833
Directory	/workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_rw.113036899
Short name	T36
Test name
Test status
Simulation time	53993171 ps
CPU time	0.8 seconds
Started	May 26 02:09:27 AM PDT 23
Finished	May 26 02:09:28 AM PDT 23
Peak memory	200500 kb
Host	smart-e6173bf1-1a90-4ac6-9176-9a766d3fb8ba
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113036899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.113036899
Directory	/workspace/3.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_intr_test.4088258710
Short name	T85
Test name
Test status
Simulation time	31905360 ps
CPU time	0.61 seconds
Started	May 26 02:09:32 AM PDT 23
Finished	May 26 02:09:33 AM PDT 23
Peak memory	196716 kb
Host	smart-3115fb3c-f8e3-42a9-a4b1-eecda99f4f2a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4088258710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.4088258710
Directory	/workspace/3.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2151473049
Short name	T38
Test name
Test status
Simulation time	208060018 ps
CPU time	2.31 seconds
Started	May 26 02:09:40 AM PDT 23
Finished	May 26 02:09:43 AM PDT 23
Peak memory	198268 kb
Host	smart-931b4fde-1fde-48b3-86f3-461678953523
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2151473049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.2151473049
Directory	/workspace/3.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_mem_walk.633616057
Short name	T135
Test name
Test status
Simulation time	370624493 ps
CPU time	2.49 seconds
Started	May 26 02:09:27 AM PDT 23
Finished	May 26 02:09:30 AM PDT 23
Peak memory	201168 kb
Host	smart-07042ae7-6a2b-436d-9dfa-944c185e0350
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=633616057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.633616057
Directory	/workspace/3.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.492368201
Short name	T90
Test name
Test status
Simulation time	132214616 ps
CPU time	1.56 seconds
Started	May 26 02:09:25 AM PDT 23
Finished	May 26 02:09:28 AM PDT 23
Peak memory	200364 kb
Host	smart-ea3d1f69-841d-4b23-9d1c-85d782df9cf9
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492368201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_cs r_outstanding.492368201
Directory	/workspace/3.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_tl_errors.3815721033
Short name	T100
Test name
Test status
Simulation time	206200212 ps
CPU time	2.65 seconds
Started	May 26 02:09:39 AM PDT 23
Finished	May 26 02:09:42 AM PDT 23
Peak memory	201284 kb
Host	smart-e4e688a6-3074-49ec-bcee-5ab769c54c97
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3815721033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.3815721033
Directory	/workspace/3.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/30.usbdev_intr_test.2728606689
Short name	T6
Test name
Test status
Simulation time	39505879 ps
CPU time	0.66 seconds
Started	May 26 02:10:29 AM PDT 23
Finished	May 26 02:10:30 AM PDT 23
Peak memory	196892 kb
Host	smart-a3a1284f-e149-4aa7-8fad-42d83803203a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2728606689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.2728606689
Directory	/workspace/30.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.usbdev_intr_test.3970303886
Short name	T106
Test name
Test status
Simulation time	18303263 ps
CPU time	0.6 seconds
Started	May 26 02:10:30 AM PDT 23
Finished	May 26 02:10:31 AM PDT 23
Peak memory	196568 kb
Host	smart-76b1cc30-711e-4d1e-bd39-038852a3cf32
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3970303886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.3970303886
Directory	/workspace/31.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.usbdev_intr_test.2883997539
Short name	T153
Test name
Test status
Simulation time	17554902 ps
CPU time	0.64 seconds
Started	May 26 02:10:24 AM PDT 23
Finished	May 26 02:10:25 AM PDT 23
Peak memory	196720 kb
Host	smart-78b2f803-1e4b-4c53-aab2-d5973e533386
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2883997539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.2883997539
Directory	/workspace/33.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.usbdev_intr_test.964580463
Short name	T142
Test name
Test status
Simulation time	28163643 ps
CPU time	0.61 seconds
Started	May 26 02:10:30 AM PDT 23
Finished	May 26 02:10:31 AM PDT 23
Peak memory	196564 kb
Host	smart-7ef0026f-c85c-47f8-b295-d642baa60e27
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=964580463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.964580463
Directory	/workspace/34.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.usbdev_intr_test.301668808
Short name	T88
Test name
Test status
Simulation time	35456518 ps
CPU time	0.64 seconds
Started	May 26 02:10:25 AM PDT 23
Finished	May 26 02:10:25 AM PDT 23
Peak memory	198060 kb
Host	smart-9840ac2c-2e8e-4b2f-9354-5204be92f79e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=301668808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.301668808
Directory	/workspace/35.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.usbdev_intr_test.3891830603
Short name	T112
Test name
Test status
Simulation time	15053011 ps
CPU time	0.61 seconds
Started	May 26 02:10:30 AM PDT 23
Finished	May 26 02:10:31 AM PDT 23
Peak memory	198236 kb
Host	smart-d2f9b873-aba6-4d0d-8935-fefed737187c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3891830603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.3891830603
Directory	/workspace/36.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.usbdev_intr_test.1361137729
Short name	T110
Test name
Test status
Simulation time	40098552 ps
CPU time	0.66 seconds
Started	May 26 02:10:23 AM PDT 23
Finished	May 26 02:10:24 AM PDT 23
Peak memory	198108 kb
Host	smart-cf6c4335-7377-4cc9-bdc5-d567091ca3a6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1361137729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.1361137729
Directory	/workspace/37.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.usbdev_intr_test.1642588558
Short name	T61
Test name
Test status
Simulation time	22190565 ps
CPU time	0.6 seconds
Started	May 26 02:10:24 AM PDT 23
Finished	May 26 02:10:25 AM PDT 23
Peak memory	197968 kb
Host	smart-67c578ba-e1d9-497b-a4ea-c51c5d2f0d1d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1642588558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.1642588558
Directory	/workspace/38.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.usbdev_intr_test.3449344255
Short name	T123
Test name
Test status
Simulation time	42551145 ps
CPU time	0.65 seconds
Started	May 26 02:10:22 AM PDT 23
Finished	May 26 02:10:23 AM PDT 23
Peak memory	198056 kb
Host	smart-cc7b0647-edc2-4178-a6cc-e102ecf36327
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3449344255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.3449344255
Directory	/workspace/39.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2103783934
Short name	T47
Test name
Test status
Simulation time	209188936 ps
CPU time	2.01 seconds
Started	May 26 02:09:41 AM PDT 23
Finished	May 26 02:09:44 AM PDT 23
Peak memory	199756 kb
Host	smart-d20a42d4-434f-4d5f-b4cb-434322c3447e
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103783934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.2103783934
Directory	/workspace/4.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.2679137439
Short name	T41
Test name
Test status
Simulation time	372291043 ps
CPU time	8.16 seconds
Started	May 26 02:09:29 AM PDT 23
Finished	May 26 02:09:38 AM PDT 23
Peak memory	201232 kb
Host	smart-754c6100-1b2a-45f8-ae20-33dd9958e717
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679137439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.2679137439
Directory	/workspace/4.usbdev_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.1390061699
Short name	T44
Test name
Test status
Simulation time	22819726 ps
CPU time	0.68 seconds
Started	May 26 02:09:29 AM PDT 23
Finished	May 26 02:09:30 AM PDT 23
Peak memory	198324 kb
Host	smart-489df119-e34c-43d0-9dfc-788870ee1ffd
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390061699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.1390061699
Directory	/workspace/4.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2766306676
Short name	T127
Test name
Test status
Simulation time	128427629 ps
CPU time	4.06 seconds
Started	May 26 02:09:31 AM PDT 23
Finished	May 26 02:09:36 AM PDT 23
Peak memory	209560 kb
Host	smart-3c14b8aa-b464-4395-b9ec-9d70ea8a5228
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766306676 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_mem_rw_with_rand_reset.2766306676
Directory	/workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_rw.3971663046
Short name	T108
Test name
Test status
Simulation time	39768268 ps
CPU time	0.83 seconds
Started	May 26 02:09:28 AM PDT 23
Finished	May 26 02:09:30 AM PDT 23
Peak memory	200812 kb
Host	smart-e1409e2c-ae84-4879-b877-8734994d7131
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971663046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.3971663046
Directory	/workspace/4.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_intr_test.1836229622
Short name	T86
Test name
Test status
Simulation time	31519020 ps
CPU time	0.65 seconds
Started	May 26 02:09:41 AM PDT 23
Finished	May 26 02:09:42 AM PDT 23
Peak memory	196632 kb
Host	smart-7f362146-b2dd-4a59-86d7-9dfa643661ea
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1836229622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.1836229622
Directory	/workspace/4.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.3693319598
Short name	T42
Test name
Test status
Simulation time	59462855 ps
CPU time	1.99 seconds
Started	May 26 02:09:31 AM PDT 23
Finished	May 26 02:09:33 AM PDT 23
Peak memory	201128 kb
Host	smart-ab1c026b-d0a6-4256-ab39-a30ad2e8a70b
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3693319598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.3693319598
Directory	/workspace/4.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_mem_walk.1147105616
Short name	T1
Test name
Test status
Simulation time	102752370 ps
CPU time	2.11 seconds
Started	May 26 02:09:31 AM PDT 23
Finished	May 26 02:09:33 AM PDT 23
Peak memory	201104 kb
Host	smart-a1143eaf-bb21-49f4-b404-c9ef2887915a
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1147105616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.1147105616
Directory	/workspace/4.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.3663351267
Short name	T151
Test name
Test status
Simulation time	49613456 ps
CPU time	1.37 seconds
Started	May 26 02:09:29 AM PDT 23
Finished	May 26 02:09:31 AM PDT 23
Peak memory	201288 kb
Host	smart-e5239f68-8955-4342-bb6e-e766db950bff
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663351267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_c sr_outstanding.3663351267
Directory	/workspace/4.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_tl_errors.4176385399
Short name	T128
Test name
Test status
Simulation time	298129275 ps
CPU time	2.84 seconds
Started	May 26 02:09:36 AM PDT 23
Finished	May 26 02:09:39 AM PDT 23
Peak memory	201196 kb
Host	smart-c86c3f9c-22e4-46b0-8f42-8a5cfd5895f0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4176385399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.4176385399
Directory	/workspace/4.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/40.usbdev_intr_test.192486462
Short name	T152
Test name
Test status
Simulation time	11908679 ps
CPU time	0.59 seconds
Started	May 26 02:10:23 AM PDT 23
Finished	May 26 02:10:24 AM PDT 23
Peak memory	196768 kb
Host	smart-e97a4d2f-d60b-4f5f-8d08-8cb7f49fb4f9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=192486462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.192486462
Directory	/workspace/40.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.usbdev_intr_test.2029775109
Short name	T76
Test name
Test status
Simulation time	12906373 ps
CPU time	0.65 seconds
Started	May 26 02:10:24 AM PDT 23
Finished	May 26 02:10:25 AM PDT 23
Peak memory	196724 kb
Host	smart-f585b8c1-bd73-4e85-9129-7edd3027ecdd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2029775109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.2029775109
Directory	/workspace/42.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.usbdev_intr_test.4099698004
Short name	T69
Test name
Test status
Simulation time	16711260 ps
CPU time	0.58 seconds
Started	May 26 02:10:21 AM PDT 23
Finished	May 26 02:10:22 AM PDT 23
Peak memory	196728 kb
Host	smart-bd3dcaf4-9640-46c4-94cb-89d9d7808b97
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4099698004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.4099698004
Directory	/workspace/43.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.usbdev_intr_test.1302982422
Short name	T19
Test name
Test status
Simulation time	36018252 ps
CPU time	0.7 seconds
Started	May 26 02:10:22 AM PDT 23
Finished	May 26 02:10:23 AM PDT 23
Peak memory	196748 kb
Host	smart-756de9e0-cabf-4a0f-aed7-5a58e1b49f22
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1302982422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.1302982422
Directory	/workspace/44.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.usbdev_intr_test.1272263932
Short name	T120
Test name
Test status
Simulation time	26684511 ps
CPU time	0.62 seconds
Started	May 26 02:10:21 AM PDT 23
Finished	May 26 02:10:22 AM PDT 23
Peak memory	198068 kb
Host	smart-661cbbb0-8991-4cd0-a3c7-0bc5175ca7c3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1272263932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.1272263932
Directory	/workspace/45.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.usbdev_intr_test.1448528600
Short name	T117
Test name
Test status
Simulation time	12618893 ps
CPU time	0.62 seconds
Started	May 26 02:10:21 AM PDT 23
Finished	May 26 02:10:22 AM PDT 23
Peak memory	198088 kb
Host	smart-6ba194fc-82fa-487c-a052-68a6511a6efa
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1448528600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.1448528600
Directory	/workspace/46.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.usbdev_intr_test.3911267052
Short name	T140
Test name
Test status
Simulation time	26439108 ps
CPU time	0.62 seconds
Started	May 26 02:10:21 AM PDT 23
Finished	May 26 02:10:22 AM PDT 23
Peak memory	196980 kb
Host	smart-dc9c6d0b-6012-4006-86a5-f7bbda3aba00
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3911267052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.3911267052
Directory	/workspace/47.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.usbdev_intr_test.2858265987
Short name	T137
Test name
Test status
Simulation time	15248346 ps
CPU time	0.71 seconds
Started	May 26 02:10:27 AM PDT 23
Finished	May 26 02:10:28 AM PDT 23
Peak memory	197788 kb
Host	smart-3e1bd483-7d90-418b-aabd-6dffdd421457
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2858265987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.2858265987
Directory	/workspace/48.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.usbdev_intr_test.796900551
Short name	T67
Test name
Test status
Simulation time	23015390 ps
CPU time	0.63 seconds
Started	May 26 02:10:25 AM PDT 23
Finished	May 26 02:10:25 AM PDT 23
Peak memory	196720 kb
Host	smart-cee210be-8afe-4216-84f9-edc621cc74e2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=796900551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.796900551
Directory	/workspace/49.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.2620686764
Short name	T11
Test name
Test status
Simulation time	84135128 ps
CPU time	1.57 seconds
Started	May 26 02:09:41 AM PDT 23
Finished	May 26 02:09:43 AM PDT 23
Peak memory	201536 kb
Host	smart-de80acf8-9136-4444-9bab-b57dd98d5d88
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620686764 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_mem_rw_with_rand_reset.2620686764
Directory	/workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_csr_rw.284885436
Short name	T58
Test name
Test status
Simulation time	62594132 ps
CPU time	1 seconds
Started	May 26 02:09:31 AM PDT 23
Finished	May 26 02:09:32 AM PDT 23
Peak memory	201000 kb
Host	smart-e614748f-e429-4da9-8edf-9819235fa3d3
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284885436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.284885436
Directory	/workspace/5.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_intr_test.562296340
Short name	T79
Test name
Test status
Simulation time	12871123 ps
CPU time	0.59 seconds
Started	May 26 02:09:29 AM PDT 23
Finished	May 26 02:09:30 AM PDT 23
Peak memory	196736 kb
Host	smart-913cf9b2-0d08-4762-8dc1-31bd498098ed
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=562296340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.562296340
Directory	/workspace/5.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.815421531
Short name	T97
Test name
Test status
Simulation time	31666248 ps
CPU time	0.95 seconds
Started	May 26 02:09:41 AM PDT 23
Finished	May 26 02:09:42 AM PDT 23
Peak memory	201272 kb
Host	smart-1582b343-b331-427f-a4cd-a95e6e631605
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815421531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_cs r_outstanding.815421531
Directory	/workspace/5.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_tl_errors.456340798
Short name	T121
Test name
Test status
Simulation time	59879971 ps
CPU time	1.73 seconds
Started	May 26 02:09:31 AM PDT 23
Finished	May 26 02:09:33 AM PDT 23
Peak memory	201308 kb
Host	smart-b27cdfdb-f2a4-4302-9d2e-b4ef24ef38a0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=456340798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.456340798
Directory	/workspace/5.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.4293559894
Short name	T5
Test name
Test status
Simulation time	39602058 ps
CPU time	1.17 seconds
Started	May 26 02:09:29 AM PDT 23
Finished	May 26 02:09:31 AM PDT 23
Peak memory	201436 kb
Host	smart-9e117aaf-3c4a-4eed-afca-e206e43c2e47
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293559894 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_mem_rw_with_rand_reset.4293559894
Directory	/workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1270992982
Short name	T119
Test name
Test status
Simulation time	69772855 ps
CPU time	0.93 seconds
Started	May 26 02:09:26 AM PDT 23
Finished	May 26 02:09:28 AM PDT 23
Peak memory	200704 kb
Host	smart-20260349-2a39-47b4-baf6-785b1267915b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270992982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.1270992982
Directory	/workspace/6.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_intr_test.1386859934
Short name	T68
Test name
Test status
Simulation time	28194517 ps
CPU time	0.65 seconds
Started	May 26 02:09:33 AM PDT 23
Finished	May 26 02:09:35 AM PDT 23
Peak memory	196732 kb
Host	smart-638e5e3c-c813-4d56-b829-f03bdb9c6628
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1386859934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.1386859934
Directory	/workspace/6.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.1749537360
Short name	T95
Test name
Test status
Simulation time	127339716 ps
CPU time	1.4 seconds
Started	May 26 02:09:32 AM PDT 23
Finished	May 26 02:09:33 AM PDT 23
Peak memory	201136 kb
Host	smart-d9d932bd-f5ec-428b-8483-5b4ea6ce61c6
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749537360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_c sr_outstanding.1749537360
Directory	/workspace/6.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_tl_errors.829699354
Short name	T122
Test name
Test status
Simulation time	225180344 ps
CPU time	2.85 seconds
Started	May 26 02:09:32 AM PDT 23
Finished	May 26 02:09:37 AM PDT 23
Peak memory	201340 kb
Host	smart-a2e83aee-73e1-471a-9c5d-5bc75a8eda55
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=829699354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.829699354
Directory	/workspace/6.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.570096291
Short name	T51
Test name
Test status
Simulation time	113142594 ps
CPU time	1.63 seconds
Started	May 26 02:09:26 AM PDT 23
Finished	May 26 02:09:28 AM PDT 23
Peak memory	201216 kb
Host	smart-7dc24835-a085-4aca-8e3c-8d8a7f0175d0
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570096291 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_mem_rw_with_rand_reset.570096291
Directory	/workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_csr_rw.2268680367
Short name	T147
Test name
Test status
Simulation time	54736774 ps
CPU time	1.02 seconds
Started	May 26 02:09:41 AM PDT 23
Finished	May 26 02:09:43 AM PDT 23
Peak memory	200852 kb
Host	smart-7f7fa3d0-0caa-4ad1-976f-03e29e895273
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268680367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.2268680367
Directory	/workspace/7.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_intr_test.4040778974
Short name	T83
Test name
Test status
Simulation time	17608918 ps
CPU time	0.61 seconds
Started	May 26 02:09:30 AM PDT 23
Finished	May 26 02:09:31 AM PDT 23
Peak memory	196708 kb
Host	smart-8db7dec4-291d-4cc0-a70b-c0b5a1bc0328
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4040778974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.4040778974
Directory	/workspace/7.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.1110294866
Short name	T102
Test name
Test status
Simulation time	29847267 ps
CPU time	0.96 seconds
Started	May 26 02:09:29 AM PDT 23
Finished	May 26 02:09:31 AM PDT 23
Peak memory	199840 kb
Host	smart-7525c750-2ae5-4f06-9aad-43d34c28f3b2
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110294866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_c sr_outstanding.1110294866
Directory	/workspace/7.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_tl_errors.3365338630
Short name	T25
Test name
Test status
Simulation time	124607784 ps
CPU time	1.52 seconds
Started	May 26 02:09:32 AM PDT 23
Finished	May 26 02:09:33 AM PDT 23
Peak memory	201308 kb
Host	smart-631abb38-0c30-4810-a347-d9bf1f141414
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3365338630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.3365338630
Directory	/workspace/7.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2274987825
Short name	T103
Test name
Test status
Simulation time	24561851 ps
CPU time	1.23 seconds
Started	May 26 02:09:30 AM PDT 23
Finished	May 26 02:09:32 AM PDT 23
Peak memory	201220 kb
Host	smart-ce623f77-0849-41a0-bf33-aa7422c133f7
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274987825 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_mem_rw_with_rand_reset.2274987825
Directory	/workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2134639230
Short name	T154
Test name
Test status
Simulation time	26024656 ps
CPU time	0.98 seconds
Started	May 26 02:09:40 AM PDT 23
Finished	May 26 02:09:41 AM PDT 23
Peak memory	201148 kb
Host	smart-c6e86ece-2d31-4e92-b0e9-98f9fe7591f9
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134639230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.2134639230
Directory	/workspace/8.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_intr_test.424742855
Short name	T109
Test name
Test status
Simulation time	19019923 ps
CPU time	0.67 seconds
Started	May 26 02:09:28 AM PDT 23
Finished	May 26 02:09:30 AM PDT 23
Peak memory	196760 kb
Host	smart-d67e3b52-26d7-4c68-8885-2482a1a71a9e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=424742855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.424742855
Directory	/workspace/8.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3368771266
Short name	T49
Test name
Test status
Simulation time	77815970 ps
CPU time	0.98 seconds
Started	May 26 02:09:31 AM PDT 23
Finished	May 26 02:09:33 AM PDT 23
Peak memory	201260 kb
Host	smart-df01caa5-d97c-4723-aa54-6b34cbf14d67
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368771266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_c sr_outstanding.3368771266
Directory	/workspace/8.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_tl_errors.3516207801
Short name	T31
Test name
Test status
Simulation time	50328716 ps
CPU time	1.76 seconds
Started	May 26 02:09:28 AM PDT 23
Finished	May 26 02:09:31 AM PDT 23
Peak memory	201316 kb
Host	smart-2c23d0fc-7b76-4534-929d-3a53d9e27f68
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3516207801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.3516207801
Directory	/workspace/8.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.246659302
Short name	T59
Test name
Test status
Simulation time	134960512 ps
CPU time	3.17 seconds
Started	May 26 02:09:25 AM PDT 23
Finished	May 26 02:09:30 AM PDT 23
Peak memory	209496 kb
Host	smart-1824abfa-b062-452e-856c-0203e6a34953
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246659302 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_mem_rw_with_rand_reset.246659302
Directory	/workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_csr_rw.592568314
Short name	T40
Test name
Test status
Simulation time	19183319 ps
CPU time	0.81 seconds
Started	May 26 02:09:34 AM PDT 23
Finished	May 26 02:09:35 AM PDT 23
Peak memory	200604 kb
Host	smart-91819dbb-3e1b-4bdf-99dc-db4d8c730762
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592568314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.592568314
Directory	/workspace/9.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_intr_test.4131386852
Short name	T55
Test name
Test status
Simulation time	29543242 ps
CPU time	0.63 seconds
Started	May 26 02:09:39 AM PDT 23
Finished	May 26 02:09:40 AM PDT 23
Peak memory	198032 kb
Host	smart-64a3ed17-c45a-496d-a993-7796a26df8dd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4131386852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.4131386852
Directory	/workspace/9.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.2578957757
Short name	T130
Test name
Test status
Simulation time	119858300 ps
CPU time	1.48 seconds
Started	May 26 02:09:35 AM PDT 23
Finished	May 26 02:09:37 AM PDT 23
Peak memory	200552 kb
Host	smart-154a5eec-0d29-4e6c-b44f-77ca84bd8a48
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578957757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_c sr_outstanding.2578957757
Directory	/workspace/9.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_tl_errors.2488220071
Short name	T150
Test name
Test status
Simulation time	153803217 ps
CPU time	2.16 seconds
Started	May 26 02:09:31 AM PDT 23
Finished	May 26 02:09:34 AM PDT 23
Peak memory	201228 kb
Host	smart-f3fa08d0-df5c-4907-9d57-cf59795c528b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2488220071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.2488220071
Directory	/workspace/9.usbdev_tl_errors/latest