Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
76.40	90.48	74.16	95.23	0.00	86.85	92.01	96.10

Total tests in report: 158

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
52.02	52.02	67.98	67.98	57.68	57.68	76.90	76.90	0.00	0.00	72.07	72.07	67.21	67.21	22.30	22.30	/workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3028462711
62.97	10.95	89.23	21.25	69.32	11.64	85.57	8.68	0.00	0.00	86.29	14.22	87.50	20.29	22.86	0.56	/workspace/coverage/default/4.usbdev_sec_cm.1913538071
69.97	7.00	90.05	0.83	71.19	1.87	89.26	3.69	0.00	0.00	86.51	0.22	87.70	0.20	65.06	42.19	/workspace/coverage/cover_reg_top/47.usbdev_intr_test.3324874663
72.86	2.89	90.09	0.04	73.72	2.54	93.49	4.23	0.00	0.00	86.59	0.09	89.14	1.43	76.95	11.90	/workspace/coverage/cover_reg_top/2.usbdev_tl_errors.4023710173
74.06	1.20	90.46	0.36	73.72	0.00	93.93	0.43	0.00	0.00	86.59	0.00	89.14	0.00	84.57	7.62	/workspace/coverage/cover_reg_top/20.usbdev_intr_test.3046160823
74.68	0.62	90.46	0.00	73.72	0.00	93.93	0.00	0.00	0.00	86.59	0.00	92.01	2.87	86.06	1.49	/workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1184934010
75.21	0.52	90.48	0.02	73.80	0.08	93.93	0.00	0.00	0.00	86.64	0.04	92.01	0.00	89.59	3.53	/workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.1299527332
75.60	0.40	90.48	0.00	73.80	0.00	93.93	0.00	0.00	0.00	86.64	0.00	92.01	0.00	92.38	2.79	/workspace/coverage/cover_reg_top/36.usbdev_intr_test.661193202
75.84	0.24	90.48	0.00	73.80	0.00	93.93	0.00	0.00	0.00	86.64	0.00	92.01	0.00	94.05	1.67	/workspace/coverage/cover_reg_top/4.usbdev_intr_test.24411151
76.05	0.21	90.50	0.02	73.98	0.18	94.79	0.87	0.00	0.00	86.85	0.22	92.01	0.00	94.24	0.19	/workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.1561663616
76.14	0.09	90.50	0.00	74.06	0.08	94.79	0.00	0.00	0.00	86.85	0.00	92.01	0.00	94.80	0.56	/workspace/coverage/cover_reg_top/9.usbdev_tl_errors.1800192485
76.22	0.08	90.50	0.00	74.06	0.00	94.79	0.00	0.00	0.00	86.85	0.00	92.01	0.00	95.35	0.56	/workspace/coverage/cover_reg_top/30.usbdev_intr_test.3700333156
76.28	0.05	90.50	0.00	74.06	0.00	94.79	0.00	0.00	0.00	86.85	0.00	92.01	0.00	95.72	0.37	/workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.3797219694
76.31	0.04	90.68	0.18	74.13	0.08	94.79	0.00	0.00	0.00	86.85	0.00	92.01	0.00	95.72	0.00	/workspace/coverage/cover_reg_top/4.usbdev_tl_errors.1248880658
76.35	0.03	90.68	0.00	74.16	0.03	95.01	0.22	0.00	0.00	86.85	0.00	92.01	0.00	95.72	0.00	/workspace/coverage/default/0.usbdev_sec_cm.3762273946
76.38	0.03	90.68	0.00	74.16	0.00	95.23	0.22	0.00	0.00	86.85	0.00	92.01	0.00	95.72	0.00	/workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.2771063744
76.41	0.03	90.68	0.00	74.16	0.00	95.23	0.00	0.00	0.00	86.85	0.00	92.01	0.00	95.91	0.19	/workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2598188567
76.43	0.03	90.68	0.00	74.16	0.00	95.23	0.00	0.00	0.00	86.85	0.00	92.01	0.00	96.10	0.19	/workspace/coverage/cover_reg_top/26.usbdev_intr_test.1835563364
76.46	0.02	90.84	0.16	74.16	0.00	95.23	0.00	0.00	0.00	86.85	0.00	92.01	0.00	96.10	0.00	/workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3031593774

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.490805809
/workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.397923786
/workspace/coverage/cover_reg_top/0.usbdev_intr_test.739679003
/workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.3416569454
/workspace/coverage/cover_reg_top/0.usbdev_mem_walk.3504075807
/workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.72376803
/workspace/coverage/cover_reg_top/0.usbdev_tl_errors.173790365
/workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.66686490
/workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.2367860667
/workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.354037310
/workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.4139372740
/workspace/coverage/cover_reg_top/1.usbdev_csr_rw.91465555
/workspace/coverage/cover_reg_top/1.usbdev_intr_test.2858827788
/workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.3373964848
/workspace/coverage/cover_reg_top/1.usbdev_mem_walk.1792526303
/workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2124664697
/workspace/coverage/cover_reg_top/1.usbdev_tl_errors.3256934969
/workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.4077900482
/workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.1612154209
/workspace/coverage/cover_reg_top/10.usbdev_csr_rw.2189649146
/workspace/coverage/cover_reg_top/10.usbdev_intr_test.4187400622
/workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.3172115622
/workspace/coverage/cover_reg_top/10.usbdev_tl_errors.3886550279
/workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2828602487
/workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3196099688
/workspace/coverage/cover_reg_top/11.usbdev_intr_test.3735454316
/workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.4253873727
/workspace/coverage/cover_reg_top/11.usbdev_tl_errors.2175707928
/workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.2053933200
/workspace/coverage/cover_reg_top/12.usbdev_csr_rw.1434929955
/workspace/coverage/cover_reg_top/12.usbdev_intr_test.2945530575
/workspace/coverage/cover_reg_top/12.usbdev_tl_errors.426037226
/workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.523414372
/workspace/coverage/cover_reg_top/13.usbdev_csr_rw.1029905750
/workspace/coverage/cover_reg_top/13.usbdev_intr_test.3055987693
/workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.2976711110
/workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2611611068
/workspace/coverage/cover_reg_top/14.usbdev_csr_rw.2171362576
/workspace/coverage/cover_reg_top/14.usbdev_intr_test.4088749501
/workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1253032766
/workspace/coverage/cover_reg_top/14.usbdev_tl_errors.2512041426
/workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.1387529701
/workspace/coverage/cover_reg_top/15.usbdev_csr_rw.813319428
/workspace/coverage/cover_reg_top/15.usbdev_intr_test.2678787305
/workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3384793525
/workspace/coverage/cover_reg_top/15.usbdev_tl_errors.2173896337
/workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.2883802133
/workspace/coverage/cover_reg_top/16.usbdev_csr_rw.3036936833
/workspace/coverage/cover_reg_top/16.usbdev_intr_test.2464356030
/workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.4120486898
/workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1555140777
/workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.806334032
/workspace/coverage/cover_reg_top/17.usbdev_csr_rw.503189740
/workspace/coverage/cover_reg_top/17.usbdev_intr_test.2538637306
/workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.2599723095
/workspace/coverage/cover_reg_top/17.usbdev_tl_errors.2034221888
/workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.3078229093
/workspace/coverage/cover_reg_top/18.usbdev_csr_rw.1747543845
/workspace/coverage/cover_reg_top/18.usbdev_intr_test.1507448884
/workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.2163833418
/workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1210339590
/workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.4105321998
/workspace/coverage/cover_reg_top/19.usbdev_csr_rw.639588089
/workspace/coverage/cover_reg_top/19.usbdev_intr_test.3224682725
/workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.3297889875
/workspace/coverage/cover_reg_top/19.usbdev_tl_errors.2976492647
/workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.3504929783
/workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.3185263798
/workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.1077086075
/workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1449127764
/workspace/coverage/cover_reg_top/2.usbdev_csr_rw.189376900
/workspace/coverage/cover_reg_top/2.usbdev_intr_test.606247446
/workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.2368940763
/workspace/coverage/cover_reg_top/2.usbdev_mem_walk.3637228799
/workspace/coverage/cover_reg_top/21.usbdev_intr_test.4090815009
/workspace/coverage/cover_reg_top/22.usbdev_intr_test.801401940
/workspace/coverage/cover_reg_top/23.usbdev_intr_test.3620571460
/workspace/coverage/cover_reg_top/24.usbdev_intr_test.4073862912
/workspace/coverage/cover_reg_top/25.usbdev_intr_test.1994271107
/workspace/coverage/cover_reg_top/27.usbdev_intr_test.394506968
/workspace/coverage/cover_reg_top/28.usbdev_intr_test.1744319940
/workspace/coverage/cover_reg_top/29.usbdev_intr_test.767481802
/workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.4013973338
/workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.209800984
/workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.1343244464
/workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.399622109
/workspace/coverage/cover_reg_top/3.usbdev_csr_rw.78915383
/workspace/coverage/cover_reg_top/3.usbdev_intr_test.2968377437
/workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.157333486
/workspace/coverage/cover_reg_top/3.usbdev_mem_walk.1512443667
/workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.587456027
/workspace/coverage/cover_reg_top/3.usbdev_tl_errors.3963523694
/workspace/coverage/cover_reg_top/31.usbdev_intr_test.716825200
/workspace/coverage/cover_reg_top/32.usbdev_intr_test.3506485639
/workspace/coverage/cover_reg_top/33.usbdev_intr_test.3270809988
/workspace/coverage/cover_reg_top/34.usbdev_intr_test.306576213
/workspace/coverage/cover_reg_top/35.usbdev_intr_test.3821670662
/workspace/coverage/cover_reg_top/37.usbdev_intr_test.102062425
/workspace/coverage/cover_reg_top/38.usbdev_intr_test.1299887093
/workspace/coverage/cover_reg_top/39.usbdev_intr_test.1463719490
/workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2869324247
/workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.1488216107
/workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.1614366612
/workspace/coverage/cover_reg_top/4.usbdev_csr_rw.3078986453
/workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.1500244727
/workspace/coverage/cover_reg_top/4.usbdev_mem_walk.239556157
/workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.4033891486
/workspace/coverage/cover_reg_top/40.usbdev_intr_test.1886762665
/workspace/coverage/cover_reg_top/41.usbdev_intr_test.10350054
/workspace/coverage/cover_reg_top/42.usbdev_intr_test.4109221908
/workspace/coverage/cover_reg_top/43.usbdev_intr_test.1218940379
/workspace/coverage/cover_reg_top/44.usbdev_intr_test.517856155
/workspace/coverage/cover_reg_top/45.usbdev_intr_test.2545485793
/workspace/coverage/cover_reg_top/46.usbdev_intr_test.1397523407
/workspace/coverage/cover_reg_top/48.usbdev_intr_test.2543430237
/workspace/coverage/cover_reg_top/49.usbdev_intr_test.2473059958
/workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.3019064381
/workspace/coverage/cover_reg_top/5.usbdev_csr_rw.3634905192
/workspace/coverage/cover_reg_top/5.usbdev_intr_test.1123562856
/workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.4054794349
/workspace/coverage/cover_reg_top/5.usbdev_tl_errors.3914479713
/workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.927962753
/workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1684663990
/workspace/coverage/cover_reg_top/6.usbdev_intr_test.1204034388
/workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.2136395973
/workspace/coverage/cover_reg_top/6.usbdev_tl_errors.3030511278
/workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1435389467
/workspace/coverage/cover_reg_top/7.usbdev_csr_rw.1915610827
/workspace/coverage/cover_reg_top/7.usbdev_intr_test.4153620605
/workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.2713861984
/workspace/coverage/cover_reg_top/7.usbdev_tl_errors.4164701103
/workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.3996850888
/workspace/coverage/cover_reg_top/8.usbdev_csr_rw.3645691545
/workspace/coverage/cover_reg_top/8.usbdev_intr_test.1007153264
/workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.4171399293
/workspace/coverage/cover_reg_top/8.usbdev_tl_errors.1028107946
/workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2087119513
/workspace/coverage/cover_reg_top/9.usbdev_csr_rw.672390240
/workspace/coverage/cover_reg_top/9.usbdev_intr_test.2709395368

Total test records in report: 158

tests.html | tests1.html | tests2.html

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/0.usbdev_sec_cm.3762273946	May 28 05:21:14 AM PDT 23	May 28 05:21:16 AM PDT 23	113938330 ps
T2	/workspace/coverage/default/4.usbdev_sec_cm.1913538071	May 28 05:21:23 AM PDT 23	May 28 05:21:24 AM PDT 23	70002314 ps
T3	/workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1184934010	May 28 03:19:47 AM PDT 23	May 28 03:19:49 AM PDT 23	145052009 ps
T4	/workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.1614366612	May 28 03:20:40 AM PDT 23	May 28 03:20:42 AM PDT 23	30982164 ps
T5	/workspace/coverage/cover_reg_top/11.usbdev_tl_errors.2175707928	May 28 03:20:46 AM PDT 23	May 28 03:20:49 AM PDT 23	74663340 ps
T6	/workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3028462711	May 28 03:20:46 AM PDT 23	May 28 03:20:47 AM PDT 23	28077818 ps
T7	/workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2598188567	May 28 03:19:48 AM PDT 23	May 28 03:19:49 AM PDT 23	18770996 ps
T8	/workspace/coverage/cover_reg_top/47.usbdev_intr_test.3324874663	May 28 03:21:26 AM PDT 23	May 28 03:21:27 AM PDT 23	21216299 ps
T9	/workspace/coverage/cover_reg_top/2.usbdev_tl_errors.4023710173	May 28 03:20:37 AM PDT 23	May 28 03:20:42 AM PDT 23	143223256 ps
T10	/workspace/coverage/cover_reg_top/13.usbdev_csr_rw.1029905750	May 28 03:20:44 AM PDT 23	May 28 03:20:45 AM PDT 23	26990408 ps
T11	/workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.2053933200	May 28 03:20:45 AM PDT 23	May 28 03:20:46 AM PDT 23	31168025 ps
T19	/workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1684663990	May 28 03:20:42 AM PDT 23	May 28 03:20:44 AM PDT 23	60885749 ps
T24	/workspace/coverage/cover_reg_top/37.usbdev_intr_test.102062425	May 28 03:21:22 AM PDT 23	May 28 03:21:23 AM PDT 23	21237029 ps
T12	/workspace/coverage/cover_reg_top/9.usbdev_tl_errors.1800192485	May 28 03:20:49 AM PDT 23	May 28 03:20:51 AM PDT 23	136361417 ps
T47	/workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.4033891486	May 28 03:20:38 AM PDT 23	May 28 03:20:40 AM PDT 23	31329228 ps
T20	/workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.1561663616	May 28 03:20:39 AM PDT 23	May 28 03:20:40 AM PDT 23	37883611 ps
T25	/workspace/coverage/cover_reg_top/2.usbdev_intr_test.606247446	May 28 03:20:38 AM PDT 23	May 28 03:20:40 AM PDT 23	24349061 ps
T26	/workspace/coverage/cover_reg_top/44.usbdev_intr_test.517856155	May 28 03:21:25 AM PDT 23	May 28 03:21:26 AM PDT 23	13340348 ps
T37	/workspace/coverage/cover_reg_top/19.usbdev_csr_rw.639588089	May 28 03:21:27 AM PDT 23	May 28 03:21:28 AM PDT 23	18753257 ps
T13	/workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.927962753	May 28 03:20:42 AM PDT 23	May 28 03:20:45 AM PDT 23	71368099 ps
T38	/workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.66686490	May 28 03:19:45 AM PDT 23	May 28 03:19:48 AM PDT 23	106827592 ps
T39	/workspace/coverage/cover_reg_top/3.usbdev_csr_rw.78915383	May 28 03:20:37 AM PDT 23	May 28 03:20:40 AM PDT 23	23282462 ps
T40	/workspace/coverage/cover_reg_top/17.usbdev_csr_rw.503189740	May 28 03:21:32 AM PDT 23	May 28 03:21:34 AM PDT 23	67926411 ps
T41	/workspace/coverage/cover_reg_top/27.usbdev_intr_test.394506968	May 28 03:21:28 AM PDT 23	May 28 03:21:29 AM PDT 23	38390351 ps
T14	/workspace/coverage/cover_reg_top/1.usbdev_mem_walk.1792526303	May 28 03:19:47 AM PDT 23	May 28 03:19:52 AM PDT 23	154867028 ps
T17	/workspace/coverage/cover_reg_top/4.usbdev_intr_test.24411151	May 28 03:20:39 AM PDT 23	May 28 03:20:40 AM PDT 23	38134860 ps
T18	/workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.4054794349	May 28 03:20:47 AM PDT 23	May 28 03:20:48 AM PDT 23	99778653 ps
T57	/workspace/coverage/cover_reg_top/20.usbdev_intr_test.3046160823	May 28 03:21:29 AM PDT 23	May 28 03:21:30 AM PDT 23	15739149 ps
T58	/workspace/coverage/cover_reg_top/28.usbdev_intr_test.1744319940	May 28 03:21:29 AM PDT 23	May 28 03:21:30 AM PDT 23	18751056 ps
T64	/workspace/coverage/cover_reg_top/41.usbdev_intr_test.10350054	May 28 03:21:32 AM PDT 23	May 28 03:21:33 AM PDT 23	15553259 ps
T62	/workspace/coverage/cover_reg_top/0.usbdev_intr_test.739679003	May 28 03:19:47 AM PDT 23	May 28 03:19:47 AM PDT 23	32178621 ps
T59	/workspace/coverage/cover_reg_top/8.usbdev_intr_test.1007153264	May 28 03:20:38 AM PDT 23	May 28 03:20:40 AM PDT 23	19711315 ps
T60	/workspace/coverage/cover_reg_top/26.usbdev_intr_test.1835563364	May 28 03:21:25 AM PDT 23	May 28 03:21:26 AM PDT 23	18394825 ps
T61	/workspace/coverage/cover_reg_top/31.usbdev_intr_test.716825200	May 28 03:21:17 AM PDT 23	May 28 03:21:18 AM PDT 23	21556500 ps
T48	/workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1253032766	May 28 03:21:17 AM PDT 23	May 28 03:21:19 AM PDT 23	119591398 ps
T68	/workspace/coverage/cover_reg_top/17.usbdev_intr_test.2538637306	May 28 03:21:19 AM PDT 23	May 28 03:21:20 AM PDT 23	37800265 ps
T15	/workspace/coverage/cover_reg_top/0.usbdev_mem_walk.3504075807	May 28 03:19:45 AM PDT 23	May 28 03:19:47 AM PDT 23	355068104 ps
T69	/workspace/coverage/cover_reg_top/38.usbdev_intr_test.1299887093	May 28 03:21:26 AM PDT 23	May 28 03:21:27 AM PDT 23	16150057 ps
T16	/workspace/coverage/cover_reg_top/6.usbdev_tl_errors.3030511278	May 28 03:20:42 AM PDT 23	May 28 03:20:43 AM PDT 23	52405410 ps
T27	/workspace/coverage/cover_reg_top/3.usbdev_tl_errors.3963523694	May 28 03:20:38 AM PDT 23	May 28 03:20:42 AM PDT 23	255028745 ps
T52	/workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.2883802133	May 28 03:21:25 AM PDT 23	May 28 03:21:27 AM PDT 23	65716481 ps
T42	/workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.490805809	May 28 03:19:44 AM PDT 23	May 28 03:19:46 AM PDT 23	77659625 ps
T70	/workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.4105321998	May 28 03:21:27 AM PDT 23	May 28 03:21:29 AM PDT 23	31590991 ps
T71	/workspace/coverage/cover_reg_top/18.usbdev_intr_test.1507448884	May 28 03:21:22 AM PDT 23	May 28 03:21:22 AM PDT 23	36932095 ps
T72	/workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.3019064381	May 28 03:20:42 AM PDT 23	May 28 03:20:44 AM PDT 23	51125107 ps
T73	/workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2124664697	May 28 03:20:00 AM PDT 23	May 28 03:20:02 AM PDT 23	57236296 ps
T43	/workspace/coverage/cover_reg_top/7.usbdev_csr_rw.1915610827	May 28 03:20:45 AM PDT 23	May 28 03:20:46 AM PDT 23	43866413 ps
T28	/workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3031593774	May 28 03:20:43 AM PDT 23	May 28 03:20:46 AM PDT 23	177626340 ps
T33	/workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.523414372	May 28 03:21:20 AM PDT 23	May 28 03:21:22 AM PDT 23	81574553 ps
T34	/workspace/coverage/cover_reg_top/11.usbdev_intr_test.3735454316	May 28 03:20:47 AM PDT 23	May 28 03:20:48 AM PDT 23	15169952 ps
T35	/workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.399622109	May 28 03:20:37 AM PDT 23	May 28 03:20:42 AM PDT 23	273499896 ps
T36	/workspace/coverage/cover_reg_top/29.usbdev_intr_test.767481802	May 28 03:21:28 AM PDT 23	May 28 03:21:29 AM PDT 23	42018948 ps
T74	/workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.1387529701	May 28 03:21:23 AM PDT 23	May 28 03:21:25 AM PDT 23	29102107 ps
T63	/workspace/coverage/cover_reg_top/36.usbdev_intr_test.661193202	May 28 03:21:26 AM PDT 23	May 28 03:21:27 AM PDT 23	19369520 ps
T75	/workspace/coverage/cover_reg_top/21.usbdev_intr_test.4090815009	May 28 03:21:28 AM PDT 23	May 28 03:21:29 AM PDT 23	31473563 ps
T29	/workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1555140777	May 28 03:21:16 AM PDT 23	May 28 03:21:18 AM PDT 23	101486036 ps
T76	/workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.4139372740	May 28 03:20:35 AM PDT 23	May 28 03:20:41 AM PDT 23	49173291 ps
T44	/workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.3416569454	May 28 03:19:41 AM PDT 23	May 28 03:19:44 AM PDT 23	63313089 ps
T67	/workspace/coverage/cover_reg_top/7.usbdev_intr_test.4153620605	May 28 03:20:42 AM PDT 23	May 28 03:20:43 AM PDT 23	17211852 ps
T77	/workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.2136395973	May 28 03:20:44 AM PDT 23	May 28 03:20:46 AM PDT 23	31311983 ps
T45	/workspace/coverage/cover_reg_top/12.usbdev_csr_rw.1434929955	May 28 03:20:45 AM PDT 23	May 28 03:20:46 AM PDT 23	24561405 ps
T78	/workspace/coverage/cover_reg_top/10.usbdev_intr_test.4187400622	May 28 03:20:42 AM PDT 23	May 28 03:20:43 AM PDT 23	42417203 ps
T79	/workspace/coverage/cover_reg_top/23.usbdev_intr_test.3620571460	May 28 03:21:18 AM PDT 23	May 28 03:21:19 AM PDT 23	15568970 ps
T30	/workspace/coverage/cover_reg_top/0.usbdev_tl_errors.173790365	May 28 03:19:45 AM PDT 23	May 28 03:19:47 AM PDT 23	147707710 ps
T31	/workspace/coverage/cover_reg_top/15.usbdev_tl_errors.2173896337	May 28 03:21:12 AM PDT 23	May 28 03:21:16 AM PDT 23	247169671 ps
T32	/workspace/coverage/cover_reg_top/14.usbdev_tl_errors.2512041426	May 28 03:21:32 AM PDT 23	May 28 03:21:34 AM PDT 23	116903186 ps
T80	/workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.397923786	May 28 03:19:49 AM PDT 23	May 28 03:19:54 AM PDT 23	188433893 ps
T49	/workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.4077900482	May 28 03:19:44 AM PDT 23	May 28 03:19:49 AM PDT 23	477506863 ps
T65	/workspace/coverage/cover_reg_top/46.usbdev_intr_test.1397523407	May 28 03:21:36 AM PDT 23	May 28 03:21:37 AM PDT 23	13638797 ps
T81	/workspace/coverage/cover_reg_top/32.usbdev_intr_test.3506485639	May 28 03:21:21 AM PDT 23	May 28 03:21:22 AM PDT 23	20198328 ps
T82	/workspace/coverage/cover_reg_top/12.usbdev_intr_test.2945530575	May 28 03:20:45 AM PDT 23	May 28 03:20:46 AM PDT 23	29298861 ps
T83	/workspace/coverage/cover_reg_top/40.usbdev_intr_test.1886762665	May 28 03:21:32 AM PDT 23	May 28 03:21:33 AM PDT 23	29246541 ps
T84	/workspace/coverage/cover_reg_top/10.usbdev_csr_rw.2189649146	May 28 03:20:46 AM PDT 23	May 28 03:20:47 AM PDT 23	18723858 ps
T85	/workspace/coverage/cover_reg_top/15.usbdev_csr_rw.813319428	May 28 03:21:22 AM PDT 23	May 28 03:21:23 AM PDT 23	62335523 ps
T46	/workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.3373964848	May 28 03:19:49 AM PDT 23	May 28 03:19:51 AM PDT 23	143987418 ps
T86	/workspace/coverage/cover_reg_top/1.usbdev_csr_rw.91465555	May 28 03:19:45 AM PDT 23	May 28 03:19:47 AM PDT 23	54959436 ps
T87	/workspace/coverage/cover_reg_top/8.usbdev_tl_errors.1028107946	May 28 03:20:48 AM PDT 23	May 28 03:20:50 AM PDT 23	128735039 ps
T88	/workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2611611068	May 28 03:21:28 AM PDT 23	May 28 03:21:30 AM PDT 23	17360778 ps
T89	/workspace/coverage/cover_reg_top/16.usbdev_intr_test.2464356030	May 28 03:21:23 AM PDT 23	May 28 03:21:24 AM PDT 23	14220055 ps
T90	/workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.4013973338	May 28 03:20:39 AM PDT 23	May 28 03:20:41 AM PDT 23	79860109 ps
T53	/workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.4120486898	May 28 03:21:38 AM PDT 23	May 28 03:21:40 AM PDT 23	66425993 ps
T91	/workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.1500244727	May 28 03:20:37 AM PDT 23	May 28 03:20:41 AM PDT 23	34749084 ps
T92	/workspace/coverage/cover_reg_top/4.usbdev_csr_rw.3078986453	May 28 03:20:37 AM PDT 23	May 28 03:20:41 AM PDT 23	59944341 ps
T93	/workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3384793525	May 28 03:21:30 AM PDT 23	May 28 03:21:32 AM PDT 23	63904178 ps
T54	/workspace/coverage/cover_reg_top/8.usbdev_csr_rw.3645691545	May 28 03:20:45 AM PDT 23	May 28 03:20:46 AM PDT 23	66949489 ps
T94	/workspace/coverage/cover_reg_top/49.usbdev_intr_test.2473059958	May 28 03:21:37 AM PDT 23	May 28 03:21:38 AM PDT 23	57554972 ps
T95	/workspace/coverage/cover_reg_top/35.usbdev_intr_test.3821670662	May 28 03:21:22 AM PDT 23	May 28 03:21:23 AM PDT 23	43345427 ps
T96	/workspace/coverage/cover_reg_top/4.usbdev_tl_errors.1248880658	May 28 03:20:38 AM PDT 23	May 28 03:20:41 AM PDT 23	54374035 ps
T97	/workspace/coverage/cover_reg_top/9.usbdev_csr_rw.672390240	May 28 03:20:48 AM PDT 23	May 28 03:20:49 AM PDT 23	61592948 ps
T66	/workspace/coverage/cover_reg_top/42.usbdev_intr_test.4109221908	May 28 03:21:36 AM PDT 23	May 28 03:21:37 AM PDT 23	50257163 ps
T98	/workspace/coverage/cover_reg_top/19.usbdev_tl_errors.2976492647	May 28 03:21:30 AM PDT 23	May 28 03:21:32 AM PDT 23	108281242 ps
T99	/workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1449127764	May 28 03:20:35 AM PDT 23	May 28 03:20:41 AM PDT 23	53677328 ps
T55	/workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.3172115622	May 28 03:20:48 AM PDT 23	May 28 03:20:49 AM PDT 23	126966917 ps
T100	/workspace/coverage/cover_reg_top/30.usbdev_intr_test.3700333156	May 28 03:21:20 AM PDT 23	May 28 03:21:21 AM PDT 23	13669601 ps
T101	/workspace/coverage/cover_reg_top/10.usbdev_tl_errors.3886550279	May 28 03:20:38 AM PDT 23	May 28 03:20:42 AM PDT 23	228963798 ps
T56	/workspace/coverage/cover_reg_top/16.usbdev_csr_rw.3036936833	May 28 03:21:30 AM PDT 23	May 28 03:21:31 AM PDT 23	39271279 ps
T102	/workspace/coverage/cover_reg_top/43.usbdev_intr_test.1218940379	May 28 03:21:31 AM PDT 23	May 28 03:21:32 AM PDT 23	13010293 ps
T50	/workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.1299527332	May 28 03:21:26 AM PDT 23	May 28 03:21:31 AM PDT 23	606883491 ps
T103	/workspace/coverage/cover_reg_top/1.usbdev_tl_errors.3256934969	May 28 03:19:48 AM PDT 23	May 28 03:19:50 AM PDT 23	54495719 ps
T104	/workspace/coverage/cover_reg_top/17.usbdev_tl_errors.2034221888	May 28 03:21:16 AM PDT 23	May 28 03:21:18 AM PDT 23	114575603 ps
T105	/workspace/coverage/cover_reg_top/39.usbdev_intr_test.1463719490	May 28 03:21:30 AM PDT 23	May 28 03:21:31 AM PDT 23	16937281 ps
T106	/workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1210339590	May 28 03:21:22 AM PDT 23	May 28 03:21:25 AM PDT 23	246678889 ps
T107	/workspace/coverage/cover_reg_top/3.usbdev_mem_walk.1512443667	May 28 03:20:37 AM PDT 23	May 28 03:20:43 AM PDT 23	165890473 ps
T108	/workspace/coverage/cover_reg_top/33.usbdev_intr_test.3270809988	May 28 03:21:23 AM PDT 23	May 28 03:21:24 AM PDT 23	17874981 ps
T109	/workspace/coverage/cover_reg_top/48.usbdev_intr_test.2543430237	May 28 03:21:26 AM PDT 23	May 28 03:21:26 AM PDT 23	19861037 ps
T110	/workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.4253873727	May 28 03:20:46 AM PDT 23	May 28 03:20:49 AM PDT 23	115212707 ps
T111	/workspace/coverage/cover_reg_top/12.usbdev_tl_errors.426037226	May 28 03:20:46 AM PDT 23	May 28 03:20:48 AM PDT 23	229896131 ps
T112	/workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.2599723095	May 28 03:21:30 AM PDT 23	May 28 03:21:31 AM PDT 23	27011030 ps
T113	/workspace/coverage/cover_reg_top/24.usbdev_intr_test.4073862912	May 28 03:21:27 AM PDT 23	May 28 03:21:28 AM PDT 23	35674431 ps
T114	/workspace/coverage/cover_reg_top/14.usbdev_csr_rw.2171362576	May 28 03:21:36 AM PDT 23	May 28 03:21:37 AM PDT 23	56328633 ps
T115	/workspace/coverage/cover_reg_top/22.usbdev_intr_test.801401940	May 28 03:21:35 AM PDT 23	May 28 03:21:36 AM PDT 23	18364902 ps
T116	/workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.3185263798	May 28 03:20:37 AM PDT 23	May 28 03:20:44 AM PDT 23	179834225 ps
T117	/workspace/coverage/cover_reg_top/25.usbdev_intr_test.1994271107	May 28 03:21:16 AM PDT 23	May 28 03:21:16 AM PDT 23	31945812 ps
T21	/workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.2771063744	May 28 03:19:48 AM PDT 23	May 28 03:19:49 AM PDT 23	49759491 ps
T118	/workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2828602487	May 28 03:20:41 AM PDT 23	May 28 03:20:42 AM PDT 23	30279351 ps
T119	/workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.4171399293	May 28 03:20:40 AM PDT 23	May 28 03:20:41 AM PDT 23	72829409 ps
T120	/workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.2713861984	May 28 03:20:42 AM PDT 23	May 28 03:20:45 AM PDT 23	106400122 ps
T121	/workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.3078229093	May 28 03:21:20 AM PDT 23	May 28 03:21:23 AM PDT 23	52809290 ps
T122	/workspace/coverage/cover_reg_top/9.usbdev_intr_test.2709395368	May 28 03:20:43 AM PDT 23	May 28 03:20:44 AM PDT 23	52173287 ps
T123	/workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.1488216107	May 28 03:20:39 AM PDT 23	May 28 03:20:48 AM PDT 23	371299573 ps
T124	/workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.3297889875	May 28 03:21:25 AM PDT 23	May 28 03:21:27 AM PDT 23	52858866 ps
T125	/workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.157333486	May 28 03:20:39 AM PDT 23	May 28 03:20:42 AM PDT 23	165599321 ps
T126	/workspace/coverage/cover_reg_top/7.usbdev_tl_errors.4164701103	May 28 03:20:43 AM PDT 23	May 28 03:20:45 AM PDT 23	41459493 ps
T127	/workspace/coverage/cover_reg_top/5.usbdev_csr_rw.3634905192	May 28 03:20:42 AM PDT 23	May 28 03:20:44 AM PDT 23	71210979 ps
T128	/workspace/coverage/cover_reg_top/1.usbdev_intr_test.2858827788	May 28 03:19:44 AM PDT 23	May 28 03:19:45 AM PDT 23	35946775 ps
T129	/workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.3504929783	May 28 03:20:37 AM PDT 23	May 28 03:20:43 AM PDT 23	360974032 ps
T130	/workspace/coverage/cover_reg_top/15.usbdev_intr_test.2678787305	May 28 03:21:21 AM PDT 23	May 28 03:21:22 AM PDT 23	13999753 ps
T131	/workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2087119513	May 28 03:20:43 AM PDT 23	May 28 03:20:45 AM PDT 23	54945564 ps
T132	/workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.2163833418	May 28 03:21:26 AM PDT 23	May 28 03:21:28 AM PDT 23	131949373 ps
T133	/workspace/coverage/cover_reg_top/4.usbdev_mem_walk.239556157	May 28 03:20:39 AM PDT 23	May 28 03:20:44 AM PDT 23	696344166 ps
T134	/workspace/coverage/cover_reg_top/5.usbdev_intr_test.1123562856	May 28 03:20:39 AM PDT 23	May 28 03:20:40 AM PDT 23	20068544 ps
T135	/workspace/coverage/cover_reg_top/14.usbdev_intr_test.4088749501	May 28 03:21:28 AM PDT 23	May 28 03:21:29 AM PDT 23	42186088 ps
T136	/workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3196099688	May 28 03:20:41 AM PDT 23	May 28 03:20:42 AM PDT 23	17341442 ps
T137	/workspace/coverage/cover_reg_top/2.usbdev_csr_rw.189376900	May 28 03:20:37 AM PDT 23	May 28 03:20:40 AM PDT 23	18396421 ps
T138	/workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.3996850888	May 28 03:20:39 AM PDT 23	May 28 03:20:40 AM PDT 23	25139182 ps
T139	/workspace/coverage/cover_reg_top/6.usbdev_intr_test.1204034388	May 28 03:20:42 AM PDT 23	May 28 03:20:43 AM PDT 23	20765367 ps
T140	/workspace/coverage/cover_reg_top/2.usbdev_mem_walk.3637228799	May 28 03:20:36 AM PDT 23	May 28 03:20:44 AM PDT 23	711136765 ps
T141	/workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.2368940763	May 28 03:20:39 AM PDT 23	May 28 03:20:42 AM PDT 23	58649339 ps
T142	/workspace/coverage/cover_reg_top/13.usbdev_intr_test.3055987693	May 28 03:20:36 AM PDT 23	May 28 03:20:40 AM PDT 23	46884040 ps
T143	/workspace/coverage/cover_reg_top/34.usbdev_intr_test.306576213	May 28 03:21:27 AM PDT 23	May 28 03:21:28 AM PDT 23	45035672 ps
T144	/workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.2367860667	May 28 03:19:46 AM PDT 23	May 28 03:19:55 AM PDT 23	397235449 ps
T145	/workspace/coverage/cover_reg_top/18.usbdev_csr_rw.1747543845	May 28 03:21:27 AM PDT 23	May 28 03:21:28 AM PDT 23	65104082 ps
T146	/workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2869324247	May 28 03:20:36 AM PDT 23	May 28 03:20:42 AM PDT 23	125326598 ps
T147	/workspace/coverage/cover_reg_top/45.usbdev_intr_test.2545485793	May 28 03:21:33 AM PDT 23	May 28 03:21:34 AM PDT 23	20838099 ps
T148	/workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.1612154209	May 28 03:20:46 AM PDT 23	May 28 03:20:48 AM PDT 23	62069354 ps
T149	/workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.2976711110	May 28 03:21:24 AM PDT 23	May 28 03:21:25 AM PDT 23	59786761 ps
T22	/workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.1077086075	May 28 03:20:39 AM PDT 23	May 28 03:20:40 AM PDT 23	68908706 ps
T150	/workspace/coverage/cover_reg_top/5.usbdev_tl_errors.3914479713	May 28 03:20:42 AM PDT 23	May 28 03:20:45 AM PDT 23	90008738 ps
T151	/workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.587456027	May 28 03:20:39 AM PDT 23	May 28 03:20:40 AM PDT 23	30327398 ps
T152	/workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.1343244464	May 28 03:20:39 AM PDT 23	May 28 03:20:40 AM PDT 23	39365954 ps
T153	/workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.209800984	May 28 03:20:37 AM PDT 23	May 28 03:20:44 AM PDT 23	180420882 ps
T154	/workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1435389467	May 28 03:20:42 AM PDT 23	May 28 03:20:43 AM PDT 23	91309779 ps
T155	/workspace/coverage/cover_reg_top/19.usbdev_intr_test.3224682725	May 28 03:21:25 AM PDT 23	May 28 03:21:26 AM PDT 23	107997996 ps
T156	/workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.72376803	May 28 03:19:39 AM PDT 23	May 28 03:19:40 AM PDT 23	27570544 ps
T157	/workspace/coverage/cover_reg_top/3.usbdev_intr_test.2968377437	May 28 03:20:38 AM PDT 23	May 28 03:20:40 AM PDT 23	17945360 ps
T51	/workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.3797219694	May 28 03:21:22 AM PDT 23	May 28 03:21:28 AM PDT 23	446719347 ps
T158	/workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.806334032	May 28 03:21:22 AM PDT 23	May 28 03:21:23 AM PDT 23	36174346 ps
T23	/workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.354037310	May 28 03:19:54 AM PDT 23	May 28 03:19:55 AM PDT 23	29334425 ps

Test location	/workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3028462711
Short name	T6
Test name
Test status
Simulation time	28077818 ps
CPU time	0.98 seconds
Started	May 28 03:20:46 AM PDT 23
Finished	May 28 03:20:47 AM PDT 23
Peak memory	200888 kb
Host	smart-082bd7fd-ffad-4554-93e8-b9e3a219718c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028462711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_ csr_outstanding.3028462711
Directory	/workspace/12.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/default/4.usbdev_sec_cm.1913538071
Short name	T2
Test name
Test status
Simulation time	70002314 ps
CPU time	0.83 seconds
Started	May 28 05:21:23 AM PDT 23
Finished	May 28 05:21:24 AM PDT 23
Peak memory	218612 kb
Host	smart-05a5e1e5-0b01-4d55-9838-90173d73f1d6
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1913538071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.1913538071
Directory	/workspace/4.usbdev_sec_cm/latest

Test location	/workspace/coverage/cover_reg_top/47.usbdev_intr_test.3324874663
Short name	T8
Test name
Test status
Simulation time	21216299 ps
CPU time	0.65 seconds
Started	May 28 03:21:26 AM PDT 23
Finished	May 28 03:21:27 AM PDT 23
Peak memory	196664 kb
Host	smart-2613be2f-55ea-4a4c-bd5d-2edf741e4d73
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3324874663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.3324874663
Directory	/workspace/47.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_tl_errors.4023710173
Short name	T9
Test name
Test status
Simulation time	143223256 ps
CPU time	2.07 seconds
Started	May 28 03:20:37 AM PDT 23
Finished	May 28 03:20:42 AM PDT 23
Peak memory	201160 kb
Host	smart-b767a1d6-f421-40c3-8b36-6635a8e123b5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4023710173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.4023710173
Directory	/workspace/2.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/20.usbdev_intr_test.3046160823
Short name	T57
Test name
Test status
Simulation time	15739149 ps
CPU time	0.64 seconds
Started	May 28 03:21:29 AM PDT 23
Finished	May 28 03:21:30 AM PDT 23
Peak memory	198076 kb
Host	smart-ad1cbb87-b0d5-4167-bcde-bf865f85f757
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3046160823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.3046160823
Directory	/workspace/20.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1184934010
Short name	T3
Test name
Test status
Simulation time	145052009 ps
CPU time	1.01 seconds
Started	May 28 03:19:47 AM PDT 23
Finished	May 28 03:19:49 AM PDT 23
Peak memory	200684 kb
Host	smart-6ec5bd43-a853-4f2d-a836-52e73b71c226
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184934010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.1184934010
Directory	/workspace/0.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.1299527332
Short name	T50
Test name
Test status
Simulation time	606883491 ps
CPU time	5.35 seconds
Started	May 28 03:21:26 AM PDT 23
Finished	May 28 03:21:31 AM PDT 23
Peak memory	201312 kb
Host	smart-3d3c07dd-6f89-4044-a76b-81d4b15295ef
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1299527332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.1299527332
Directory	/workspace/14.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/36.usbdev_intr_test.661193202
Short name	T63
Test name
Test status
Simulation time	19369520 ps
CPU time	0.64 seconds
Started	May 28 03:21:26 AM PDT 23
Finished	May 28 03:21:27 AM PDT 23
Peak memory	197876 kb
Host	smart-81750567-6d8f-4d99-acaf-cda4702feeaf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=661193202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.661193202
Directory	/workspace/36.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_intr_test.24411151
Short name	T17
Test name
Test status
Simulation time	38134860 ps
CPU time	0.64 seconds
Started	May 28 03:20:39 AM PDT 23
Finished	May 28 03:20:40 AM PDT 23
Peak memory	196676 kb
Host	smart-b908ee90-80a1-409c-af6f-89e0f70ad060
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=24411151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.24411151
Directory	/workspace/4.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.1561663616
Short name	T20
Test name
Test status
Simulation time	37883611 ps
CPU time	0.76 seconds
Started	May 28 03:20:39 AM PDT 23
Finished	May 28 03:20:40 AM PDT 23
Peak memory	199224 kb
Host	smart-a0a857ae-d3da-48e3-9aac-fd6d7beb4c17
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561663616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.1561663616
Directory	/workspace/4.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_tl_errors.1800192485
Short name	T12
Test name
Test status
Simulation time	136361417 ps
CPU time	1.67 seconds
Started	May 28 03:20:49 AM PDT 23
Finished	May 28 03:20:51 AM PDT 23
Peak memory	201332 kb
Host	smart-b3adbd92-99af-444b-bac6-bfed8fb43ca7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1800192485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.1800192485
Directory	/workspace/9.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/30.usbdev_intr_test.3700333156
Short name	T100
Test name
Test status
Simulation time	13669601 ps
CPU time	0.64 seconds
Started	May 28 03:21:20 AM PDT 23
Finished	May 28 03:21:21 AM PDT 23
Peak memory	196764 kb
Host	smart-d4972512-0973-4558-9af0-0e988574ceae
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3700333156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.3700333156
Directory	/workspace/30.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.3797219694
Short name	T51
Test name
Test status
Simulation time	446719347 ps
CPU time	4.91 seconds
Started	May 28 03:21:22 AM PDT 23
Finished	May 28 03:21:28 AM PDT 23
Peak memory	201212 kb
Host	smart-179ee05b-4b0e-4b1f-8bf8-b9c6fe76c8fd
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3797219694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.3797219694
Directory	/workspace/19.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_tl_errors.1248880658
Short name	T96
Test name
Test status
Simulation time	54374035 ps
CPU time	2.05 seconds
Started	May 28 03:20:38 AM PDT 23
Finished	May 28 03:20:41 AM PDT 23
Peak memory	201248 kb
Host	smart-c14733a9-568d-4c6f-83f9-b27454b8ea11
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1248880658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.1248880658
Directory	/workspace/4.usbdev_tl_errors/latest

Test location	/workspace/coverage/default/0.usbdev_sec_cm.3762273946
Short name	T1
Test name
Test status
Simulation time	113938330 ps
CPU time	0.92 seconds
Started	May 28 05:21:14 AM PDT 23
Finished	May 28 05:21:16 AM PDT 23
Peak memory	218100 kb
Host	smart-c309667d-76f6-4296-9915-7a1489da8ea7
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3762273946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.3762273946
Directory	/workspace/0.usbdev_sec_cm/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.2771063744
Short name	T21
Test name
Test status
Simulation time	49759491 ps
CPU time	0.77 seconds
Started	May 28 03:19:48 AM PDT 23
Finished	May 28 03:19:49 AM PDT 23
Peak memory	200784 kb
Host	smart-41b69b33-9311-496f-95d3-52ce0428598b
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771063744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.2771063744
Directory	/workspace/0.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2598188567
Short name	T7
Test name
Test status
Simulation time	18770996 ps
CPU time	0.9 seconds
Started	May 28 03:19:48 AM PDT 23
Finished	May 28 03:19:49 AM PDT 23
Peak memory	200836 kb
Host	smart-56df4fef-2f2e-408b-9c21-2a0c12b2c3e2
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598188567 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_mem_rw_with_rand_reset.2598188567
Directory	/workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/26.usbdev_intr_test.1835563364
Short name	T60
Test name
Test status
Simulation time	18394825 ps
CPU time	0.64 seconds
Started	May 28 03:21:25 AM PDT 23
Finished	May 28 03:21:26 AM PDT 23
Peak memory	196724 kb
Host	smart-0198200f-2ef5-47ae-9670-9ad086253afb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1835563364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.1835563364
Directory	/workspace/26.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3031593774
Short name	T28
Test name
Test status
Simulation time	177626340 ps
CPU time	2.54 seconds
Started	May 28 03:20:43 AM PDT 23
Finished	May 28 03:20:46 AM PDT 23
Peak memory	201068 kb
Host	smart-3dc5f4b0-6810-4a6d-addb-589a3e8961e8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3031593774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.3031593774
Directory	/workspace/13.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.490805809
Short name	T42
Test name
Test status
Simulation time	77659625 ps
CPU time	1.78 seconds
Started	May 28 03:19:44 AM PDT 23
Finished	May 28 03:19:46 AM PDT 23
Peak memory	201260 kb
Host	smart-b4d0416e-90be-40ad-8b22-06414866332d
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490805809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.490805809
Directory	/workspace/0.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.397923786
Short name	T80
Test name
Test status
Simulation time	188433893 ps
CPU time	4.54 seconds
Started	May 28 03:19:49 AM PDT 23
Finished	May 28 03:19:54 AM PDT 23
Peak memory	201140 kb
Host	smart-3fe771b5-2a0c-4497-9b52-9bf2688c319e
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397923786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.397923786
Directory	/workspace/0.usbdev_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_intr_test.739679003
Short name	T62
Test name
Test status
Simulation time	32178621 ps
CPU time	0.62 seconds
Started	May 28 03:19:47 AM PDT 23
Finished	May 28 03:19:47 AM PDT 23
Peak memory	197788 kb
Host	smart-12f9e313-c267-4695-96c5-b1e29e53c487
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=739679003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.739679003
Directory	/workspace/0.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.3416569454
Short name	T44
Test name
Test status
Simulation time	63313089 ps
CPU time	2.11 seconds
Started	May 28 03:19:41 AM PDT 23
Finished	May 28 03:19:44 AM PDT 23
Peak memory	198168 kb
Host	smart-82c8ee65-2a40-4e8c-888b-1d399e108808
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3416569454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.3416569454
Directory	/workspace/0.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_mem_walk.3504075807
Short name	T15
Test name
Test status
Simulation time	355068104 ps
CPU time	2.52 seconds
Started	May 28 03:19:45 AM PDT 23
Finished	May 28 03:19:47 AM PDT 23
Peak memory	201188 kb
Host	smart-9e18e4d8-60fe-4b52-8a42-c19d22303e1e
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3504075807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.3504075807
Directory	/workspace/0.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.72376803
Short name	T156
Test name
Test status
Simulation time	27570544 ps
CPU time	0.93 seconds
Started	May 28 03:19:39 AM PDT 23
Finished	May 28 03:19:40 AM PDT 23
Peak memory	201092 kb
Host	smart-d3db8d57-71bc-487b-b7b6-854a8a7b75e7
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72376803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr _outstanding.72376803
Directory	/workspace/0.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_tl_errors.173790365
Short name	T30
Test name
Test status
Simulation time	147707710 ps
CPU time	1.98 seconds
Started	May 28 03:19:45 AM PDT 23
Finished	May 28 03:19:47 AM PDT 23
Peak memory	201324 kb
Host	smart-11aad3e6-eb88-43fb-b717-56f9e5bcbf7e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=173790365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.173790365
Directory	/workspace/0.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.66686490
Short name	T38
Test name
Test status
Simulation time	106827592 ps
CPU time	3.13 seconds
Started	May 28 03:19:45 AM PDT 23
Finished	May 28 03:19:48 AM PDT 23
Peak memory	201232 kb
Host	smart-69f3fc06-70c4-44c4-b49d-c2de2b559043
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66686490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.66686490
Directory	/workspace/1.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.2367860667
Short name	T144
Test name
Test status
Simulation time	397235449 ps
CPU time	8.65 seconds
Started	May 28 03:19:46 AM PDT 23
Finished	May 28 03:19:55 AM PDT 23
Peak memory	200268 kb
Host	smart-337d05bb-b2bf-4a6c-b0c9-d0cab1e79efd
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367860667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.2367860667
Directory	/workspace/1.usbdev_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.354037310
Short name	T23
Test name
Test status
Simulation time	29334425 ps
CPU time	0.82 seconds
Started	May 28 03:19:54 AM PDT 23
Finished	May 28 03:19:55 AM PDT 23
Peak memory	198772 kb
Host	smart-45b2ab76-2810-4da9-a720-230cc4eec1cc
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354037310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.354037310
Directory	/workspace/1.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.4139372740
Short name	T76
Test name
Test status
Simulation time	49173291 ps
CPU time	1.22 seconds
Started	May 28 03:20:35 AM PDT 23
Finished	May 28 03:20:41 AM PDT 23
Peak memory	201336 kb
Host	smart-9fe5f87b-e905-410e-80af-c7fdbb343a1c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139372740 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_mem_rw_with_rand_reset.4139372740
Directory	/workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_rw.91465555
Short name	T86
Test name
Test status
Simulation time	54959436 ps
CPU time	0.98 seconds
Started	May 28 03:19:45 AM PDT 23
Finished	May 28 03:19:47 AM PDT 23
Peak memory	200948 kb
Host	smart-7c9d0363-af62-48cb-a070-5053864558c1
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91465555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.91465555
Directory	/workspace/1.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_intr_test.2858827788
Short name	T128
Test name
Test status
Simulation time	35946775 ps
CPU time	0.68 seconds
Started	May 28 03:19:44 AM PDT 23
Finished	May 28 03:19:45 AM PDT 23
Peak memory	198060 kb
Host	smart-041f8968-3ad7-4127-b28f-ef542621349c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2858827788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.2858827788
Directory	/workspace/1.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.3373964848
Short name	T46
Test name
Test status
Simulation time	143987418 ps
CPU time	2.41 seconds
Started	May 28 03:19:49 AM PDT 23
Finished	May 28 03:19:51 AM PDT 23
Peak memory	198012 kb
Host	smart-e3306bdc-95dd-496a-b422-e6bb3d3f93ee
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3373964848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.3373964848
Directory	/workspace/1.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_mem_walk.1792526303
Short name	T14
Test name
Test status
Simulation time	154867028 ps
CPU time	3.89 seconds
Started	May 28 03:19:47 AM PDT 23
Finished	May 28 03:19:52 AM PDT 23
Peak memory	201128 kb
Host	smart-a3e0f26f-32f7-4865-9886-6ce37ba06802
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1792526303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.1792526303
Directory	/workspace/1.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2124664697
Short name	T73
Test name
Test status
Simulation time	57236296 ps
CPU time	1.47 seconds
Started	May 28 03:20:00 AM PDT 23
Finished	May 28 03:20:02 AM PDT 23
Peak memory	200444 kb
Host	smart-7c1a3b1b-192d-45fe-90c3-6736c967b56c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124664697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_c sr_outstanding.2124664697
Directory	/workspace/1.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_tl_errors.3256934969
Short name	T103
Test name
Test status
Simulation time	54495719 ps
CPU time	1.89 seconds
Started	May 28 03:19:48 AM PDT 23
Finished	May 28 03:19:50 AM PDT 23
Peak memory	201136 kb
Host	smart-beb64604-143e-4630-ac91-09a9b5c29a82
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3256934969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.3256934969
Directory	/workspace/1.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.4077900482
Short name	T49
Test name
Test status
Simulation time	477506863 ps
CPU time	4.98 seconds
Started	May 28 03:19:44 AM PDT 23
Finished	May 28 03:19:49 AM PDT 23
Peak memory	201316 kb
Host	smart-6d3f5a25-d430-4adf-b28d-d9f1f93942e4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=4077900482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.4077900482
Directory	/workspace/1.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.1612154209
Short name	T148
Test name
Test status
Simulation time	62069354 ps
CPU time	1.8 seconds
Started	May 28 03:20:46 AM PDT 23
Finished	May 28 03:20:48 AM PDT 23
Peak memory	209656 kb
Host	smart-aacb7b13-e0b0-45fe-91b3-0685124dc127
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612154209 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_mem_rw_with_rand_reset.1612154209
Directory	/workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_csr_rw.2189649146
Short name	T84
Test name
Test status
Simulation time	18723858 ps
CPU time	0.86 seconds
Started	May 28 03:20:46 AM PDT 23
Finished	May 28 03:20:47 AM PDT 23
Peak memory	200584 kb
Host	smart-89fb4663-f166-4a62-8ee4-a4e16a489be6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189649146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.2189649146
Directory	/workspace/10.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_intr_test.4187400622
Short name	T78
Test name
Test status
Simulation time	42417203 ps
CPU time	0.65 seconds
Started	May 28 03:20:42 AM PDT 23
Finished	May 28 03:20:43 AM PDT 23
Peak memory	196612 kb
Host	smart-4f22d58d-39b3-4709-a731-a8044d514cfc
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4187400622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.4187400622
Directory	/workspace/10.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.3172115622
Short name	T55
Test name
Test status
Simulation time	126966917 ps
CPU time	1.26 seconds
Started	May 28 03:20:48 AM PDT 23
Finished	May 28 03:20:49 AM PDT 23
Peak memory	201240 kb
Host	smart-baf6a013-3c6f-4297-9edd-7f4717c2edd1
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172115622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_ csr_outstanding.3172115622
Directory	/workspace/10.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_tl_errors.3886550279
Short name	T101
Test name
Test status
Simulation time	228963798 ps
CPU time	2.7 seconds
Started	May 28 03:20:38 AM PDT 23
Finished	May 28 03:20:42 AM PDT 23
Peak memory	201436 kb
Host	smart-7d996443-3c4d-48e5-b6ad-0e34cb251fe3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3886550279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.3886550279
Directory	/workspace/10.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2828602487
Short name	T118
Test name
Test status
Simulation time	30279351 ps
CPU time	1.03 seconds
Started	May 28 03:20:41 AM PDT 23
Finished	May 28 03:20:42 AM PDT 23
Peak memory	200996 kb
Host	smart-5ad9d416-39c6-4b86-9def-5ffbd90a5638
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828602487 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_mem_rw_with_rand_reset.2828602487
Directory	/workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3196099688
Short name	T136
Test name
Test status
Simulation time	17341442 ps
CPU time	0.71 seconds
Started	May 28 03:20:41 AM PDT 23
Finished	May 28 03:20:42 AM PDT 23
Peak memory	198820 kb
Host	smart-de019da2-cde5-4781-b6ce-0e20ef5b2e0a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196099688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.3196099688
Directory	/workspace/11.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_intr_test.3735454316
Short name	T34
Test name
Test status
Simulation time	15169952 ps
CPU time	0.61 seconds
Started	May 28 03:20:47 AM PDT 23
Finished	May 28 03:20:48 AM PDT 23
Peak memory	196784 kb
Host	smart-bda9596f-9e65-4425-b370-28d823b6330b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3735454316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.3735454316
Directory	/workspace/11.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.4253873727
Short name	T110
Test name
Test status
Simulation time	115212707 ps
CPU time	1.54 seconds
Started	May 28 03:20:46 AM PDT 23
Finished	May 28 03:20:49 AM PDT 23
Peak memory	201220 kb
Host	smart-dd14b4ea-170c-49be-ac7b-d8898d2b5d1a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253873727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_ csr_outstanding.4253873727
Directory	/workspace/11.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_tl_errors.2175707928
Short name	T5
Test name
Test status
Simulation time	74663340 ps
CPU time	2.59 seconds
Started	May 28 03:20:46 AM PDT 23
Finished	May 28 03:20:49 AM PDT 23
Peak memory	201308 kb
Host	smart-02362cb9-acfa-4155-840f-ca657b7941e6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2175707928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.2175707928
Directory	/workspace/11.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.2053933200
Short name	T11
Test name
Test status
Simulation time	31168025 ps
CPU time	0.95 seconds
Started	May 28 03:20:45 AM PDT 23
Finished	May 28 03:20:46 AM PDT 23
Peak memory	201096 kb
Host	smart-05e35409-36a4-4d2f-bb87-be8035a8fa93
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053933200 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_mem_rw_with_rand_reset.2053933200
Directory	/workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_csr_rw.1434929955
Short name	T45
Test name
Test status
Simulation time	24561405 ps
CPU time	0.77 seconds
Started	May 28 03:20:45 AM PDT 23
Finished	May 28 03:20:46 AM PDT 23
Peak memory	200432 kb
Host	smart-ce6f14c5-4702-491d-bacb-569126c96e75
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434929955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.1434929955
Directory	/workspace/12.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_intr_test.2945530575
Short name	T82
Test name
Test status
Simulation time	29298861 ps
CPU time	0.65 seconds
Started	May 28 03:20:45 AM PDT 23
Finished	May 28 03:20:46 AM PDT 23
Peak memory	196708 kb
Host	smart-9c3b5b94-026f-4018-ae87-88347e5a1ad8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2945530575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.2945530575
Directory	/workspace/12.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_tl_errors.426037226
Short name	T111
Test name
Test status
Simulation time	229896131 ps
CPU time	2.04 seconds
Started	May 28 03:20:46 AM PDT 23
Finished	May 28 03:20:48 AM PDT 23
Peak memory	201308 kb
Host	smart-90fa102b-202e-46a5-a5b0-45c80ece782e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=426037226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.426037226
Directory	/workspace/12.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.523414372
Short name	T33
Test name
Test status
Simulation time	81574553 ps
CPU time	2.66 seconds
Started	May 28 03:21:20 AM PDT 23
Finished	May 28 03:21:22 AM PDT 23
Peak memory	209508 kb
Host	smart-18e48a62-bea6-4fb2-a06c-cdc478708272
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523414372 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_mem_rw_with_rand_reset.523414372
Directory	/workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_csr_rw.1029905750
Short name	T10
Test name
Test status
Simulation time	26990408 ps
CPU time	0.94 seconds
Started	May 28 03:20:44 AM PDT 23
Finished	May 28 03:20:45 AM PDT 23
Peak memory	200940 kb
Host	smart-2c000577-1aa4-4789-aee6-3c5a2a939cf6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029905750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.1029905750
Directory	/workspace/13.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_intr_test.3055987693
Short name	T142
Test name
Test status
Simulation time	46884040 ps
CPU time	0.63 seconds
Started	May 28 03:20:36 AM PDT 23
Finished	May 28 03:20:40 AM PDT 23
Peak memory	198116 kb
Host	smart-22c7d6cf-b3b8-4e7c-b25c-098ead9e9656
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3055987693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.3055987693
Directory	/workspace/13.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.2976711110
Short name	T149
Test name
Test status
Simulation time	59786761 ps
CPU time	1.13 seconds
Started	May 28 03:21:24 AM PDT 23
Finished	May 28 03:21:25 AM PDT 23
Peak memory	201196 kb
Host	smart-16127e84-8633-412e-82ca-e793f8a48b03
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976711110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_ csr_outstanding.2976711110
Directory	/workspace/13.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2611611068
Short name	T88
Test name
Test status
Simulation time	17360778 ps
CPU time	1.14 seconds
Started	May 28 03:21:28 AM PDT 23
Finished	May 28 03:21:30 AM PDT 23
Peak memory	201300 kb
Host	smart-32c59275-4cba-4e05-b825-99ad81d30801
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611611068 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_mem_rw_with_rand_reset.2611611068
Directory	/workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_csr_rw.2171362576
Short name	T114
Test name
Test status
Simulation time	56328633 ps
CPU time	1.05 seconds
Started	May 28 03:21:36 AM PDT 23
Finished	May 28 03:21:37 AM PDT 23
Peak memory	200968 kb
Host	smart-3b2c5cd8-a295-496e-9d62-34f96dbda225
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171362576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.2171362576
Directory	/workspace/14.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_intr_test.4088749501
Short name	T135
Test name
Test status
Simulation time	42186088 ps
CPU time	0.65 seconds
Started	May 28 03:21:28 AM PDT 23
Finished	May 28 03:21:29 AM PDT 23
Peak memory	196764 kb
Host	smart-31ebab3e-248f-479c-a8fe-9722c7103254
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4088749501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.4088749501
Directory	/workspace/14.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1253032766
Short name	T48
Test name
Test status
Simulation time	119591398 ps
CPU time	1.39 seconds
Started	May 28 03:21:17 AM PDT 23
Finished	May 28 03:21:19 AM PDT 23
Peak memory	200464 kb
Host	smart-0b0e6559-4b7c-4bb7-8d1c-7851e716ce56
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253032766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_ csr_outstanding.1253032766
Directory	/workspace/14.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_tl_errors.2512041426
Short name	T32
Test name
Test status
Simulation time	116903186 ps
CPU time	1.55 seconds
Started	May 28 03:21:32 AM PDT 23
Finished	May 28 03:21:34 AM PDT 23
Peak memory	201356 kb
Host	smart-21cb6ff9-c92f-4783-93f1-4e840d211c3c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2512041426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.2512041426
Directory	/workspace/14.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.1387529701
Short name	T74
Test name
Test status
Simulation time	29102107 ps
CPU time	1.45 seconds
Started	May 28 03:21:23 AM PDT 23
Finished	May 28 03:21:25 AM PDT 23
Peak memory	201188 kb
Host	smart-b7d45107-68a4-44cd-82e5-fa45c58396b0
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387529701 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_mem_rw_with_rand_reset.1387529701
Directory	/workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_csr_rw.813319428
Short name	T85
Test name
Test status
Simulation time	62335523 ps
CPU time	0.82 seconds
Started	May 28 03:21:22 AM PDT 23
Finished	May 28 03:21:23 AM PDT 23
Peak memory	200384 kb
Host	smart-a2bcf964-fa90-48a7-8f94-869c536a4fae
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813319428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.813319428
Directory	/workspace/15.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_intr_test.2678787305
Short name	T130
Test name
Test status
Simulation time	13999753 ps
CPU time	0.6 seconds
Started	May 28 03:21:21 AM PDT 23
Finished	May 28 03:21:22 AM PDT 23
Peak memory	196692 kb
Host	smart-43465539-f45c-43eb-9a8d-48cf2101d09c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2678787305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.2678787305
Directory	/workspace/15.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3384793525
Short name	T93
Test name
Test status
Simulation time	63904178 ps
CPU time	1.03 seconds
Started	May 28 03:21:30 AM PDT 23
Finished	May 28 03:21:32 AM PDT 23
Peak memory	201368 kb
Host	smart-20915ada-5dea-42af-ae80-9693bcd25081
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384793525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_ csr_outstanding.3384793525
Directory	/workspace/15.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_tl_errors.2173896337
Short name	T31
Test name
Test status
Simulation time	247169671 ps
CPU time	3.29 seconds
Started	May 28 03:21:12 AM PDT 23
Finished	May 28 03:21:16 AM PDT 23
Peak memory	201304 kb
Host	smart-4a50504f-86b9-4f08-afb7-6e720504fff3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2173896337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.2173896337
Directory	/workspace/15.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.2883802133
Short name	T52
Test name
Test status
Simulation time	65716481 ps
CPU time	1.53 seconds
Started	May 28 03:21:25 AM PDT 23
Finished	May 28 03:21:27 AM PDT 23
Peak memory	201296 kb
Host	smart-2797c132-9395-4968-a197-72d167d3814f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883802133 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_mem_rw_with_rand_reset.2883802133
Directory	/workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_csr_rw.3036936833
Short name	T56
Test name
Test status
Simulation time	39271279 ps
CPU time	0.84 seconds
Started	May 28 03:21:30 AM PDT 23
Finished	May 28 03:21:31 AM PDT 23
Peak memory	200152 kb
Host	smart-e01481f0-49ab-4377-bb92-1c4ab702d1f9
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036936833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.3036936833
Directory	/workspace/16.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_intr_test.2464356030
Short name	T89
Test name
Test status
Simulation time	14220055 ps
CPU time	0.6 seconds
Started	May 28 03:21:23 AM PDT 23
Finished	May 28 03:21:24 AM PDT 23
Peak memory	196456 kb
Host	smart-fb2d18eb-20b5-4228-8bea-4605d70c91e3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2464356030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.2464356030
Directory	/workspace/16.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.4120486898
Short name	T53
Test name
Test status
Simulation time	66425993 ps
CPU time	1.14 seconds
Started	May 28 03:21:38 AM PDT 23
Finished	May 28 03:21:40 AM PDT 23
Peak memory	201356 kb
Host	smart-25523d53-c0c7-4eaa-a3d6-20254fdd8eb8
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120486898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_ csr_outstanding.4120486898
Directory	/workspace/16.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1555140777
Short name	T29
Test name
Test status
Simulation time	101486036 ps
CPU time	1.57 seconds
Started	May 28 03:21:16 AM PDT 23
Finished	May 28 03:21:18 AM PDT 23
Peak memory	201256 kb
Host	smart-b6265650-8e92-46d1-8324-ae787daee3bd
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1555140777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.1555140777
Directory	/workspace/16.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.806334032
Short name	T158
Test name
Test status
Simulation time	36174346 ps
CPU time	1.03 seconds
Started	May 28 03:21:22 AM PDT 23
Finished	May 28 03:21:23 AM PDT 23
Peak memory	201080 kb
Host	smart-ebee2a41-2e2b-439d-b781-3dadc35dd10b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806334032 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_mem_rw_with_rand_reset.806334032
Directory	/workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_csr_rw.503189740
Short name	T40
Test name
Test status
Simulation time	67926411 ps
CPU time	1.09 seconds
Started	May 28 03:21:32 AM PDT 23
Finished	May 28 03:21:34 AM PDT 23
Peak memory	200980 kb
Host	smart-9a20a744-f24a-4182-befc-e00c389b89a4
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503189740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.503189740
Directory	/workspace/17.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_intr_test.2538637306
Short name	T68
Test name
Test status
Simulation time	37800265 ps
CPU time	0.64 seconds
Started	May 28 03:21:19 AM PDT 23
Finished	May 28 03:21:20 AM PDT 23
Peak memory	198108 kb
Host	smart-6e1270cd-a559-42b2-845c-034c3bef70ba
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2538637306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.2538637306
Directory	/workspace/17.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.2599723095
Short name	T112
Test name
Test status
Simulation time	27011030 ps
CPU time	0.89 seconds
Started	May 28 03:21:30 AM PDT 23
Finished	May 28 03:21:31 AM PDT 23
Peak memory	200828 kb
Host	smart-ee3942cf-c05e-47a8-b6ce-f22b83dae40a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599723095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_ csr_outstanding.2599723095
Directory	/workspace/17.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_tl_errors.2034221888
Short name	T104
Test name
Test status
Simulation time	114575603 ps
CPU time	1.67 seconds
Started	May 28 03:21:16 AM PDT 23
Finished	May 28 03:21:18 AM PDT 23
Peak memory	201260 kb
Host	smart-c66239dc-6c7e-41cf-8a08-9d6b8b24785f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2034221888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.2034221888
Directory	/workspace/17.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.3078229093
Short name	T121
Test name
Test status
Simulation time	52809290 ps
CPU time	2.21 seconds
Started	May 28 03:21:20 AM PDT 23
Finished	May 28 03:21:23 AM PDT 23
Peak memory	201372 kb
Host	smart-c6ecf87e-79d7-42c2-8a55-79c7762b7dad
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078229093 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_mem_rw_with_rand_reset.3078229093
Directory	/workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_csr_rw.1747543845
Short name	T145
Test name
Test status
Simulation time	65104082 ps
CPU time	0.78 seconds
Started	May 28 03:21:27 AM PDT 23
Finished	May 28 03:21:28 AM PDT 23
Peak memory	198976 kb
Host	smart-4025ed72-c2a0-4b70-8e71-a6e061a233f9
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747543845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.1747543845
Directory	/workspace/18.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_intr_test.1507448884
Short name	T71
Test name
Test status
Simulation time	36932095 ps
CPU time	0.63 seconds
Started	May 28 03:21:22 AM PDT 23
Finished	May 28 03:21:22 AM PDT 23
Peak memory	198012 kb
Host	smart-4988b75f-f023-4313-b1b1-dc0f02dba084
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1507448884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.1507448884
Directory	/workspace/18.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.2163833418
Short name	T132
Test name
Test status
Simulation time	131949373 ps
CPU time	1.44 seconds
Started	May 28 03:21:26 AM PDT 23
Finished	May 28 03:21:28 AM PDT 23
Peak memory	201332 kb
Host	smart-ede12c25-39ef-41df-b177-b2d75bca8b97
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163833418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_ csr_outstanding.2163833418
Directory	/workspace/18.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1210339590
Short name	T106
Test name
Test status
Simulation time	246678889 ps
CPU time	3.25 seconds
Started	May 28 03:21:22 AM PDT 23
Finished	May 28 03:21:25 AM PDT 23
Peak memory	201284 kb
Host	smart-190b0b89-f6fc-4c7c-a7af-4cdc117772e4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1210339590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.1210339590
Directory	/workspace/18.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.4105321998
Short name	T70
Test name
Test status
Simulation time	31590991 ps
CPU time	1.26 seconds
Started	May 28 03:21:27 AM PDT 23
Finished	May 28 03:21:29 AM PDT 23
Peak memory	201336 kb
Host	smart-e0916b33-97f4-4738-8425-c358429ad089
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105321998 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_mem_rw_with_rand_reset.4105321998
Directory	/workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_csr_rw.639588089
Short name	T37
Test name
Test status
Simulation time	18753257 ps
CPU time	0.81 seconds
Started	May 28 03:21:27 AM PDT 23
Finished	May 28 03:21:28 AM PDT 23
Peak memory	200672 kb
Host	smart-b4d5df33-f039-4074-8b1f-efa5124a4b48
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639588089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.639588089
Directory	/workspace/19.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_intr_test.3224682725
Short name	T155
Test name
Test status
Simulation time	107997996 ps
CPU time	0.68 seconds
Started	May 28 03:21:25 AM PDT 23
Finished	May 28 03:21:26 AM PDT 23
Peak memory	198040 kb
Host	smart-e2821df7-7387-4292-8192-e31c985fa954
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3224682725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.3224682725
Directory	/workspace/19.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.3297889875
Short name	T124
Test name
Test status
Simulation time	52858866 ps
CPU time	1.42 seconds
Started	May 28 03:21:25 AM PDT 23
Finished	May 28 03:21:27 AM PDT 23
Peak memory	201268 kb
Host	smart-16501a3c-4eb5-4aee-a5d6-3c43d5a3114a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297889875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_ csr_outstanding.3297889875
Directory	/workspace/19.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_tl_errors.2976492647
Short name	T98
Test name
Test status
Simulation time	108281242 ps
CPU time	1.68 seconds
Started	May 28 03:21:30 AM PDT 23
Finished	May 28 03:21:32 AM PDT 23
Peak memory	201272 kb
Host	smart-27345abe-4d41-478d-808d-31c02a08e9fc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2976492647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.2976492647
Directory	/workspace/19.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.3504929783
Short name	T129
Test name
Test status
Simulation time	360974032 ps
CPU time	3.56 seconds
Started	May 28 03:20:37 AM PDT 23
Finished	May 28 03:20:43 AM PDT 23
Peak memory	201080 kb
Host	smart-51ec0803-3409-4aa7-814f-b0f01b344f00
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504929783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.3504929783
Directory	/workspace/2.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.3185263798
Short name	T116
Test name
Test status
Simulation time	179834225 ps
CPU time	4.34 seconds
Started	May 28 03:20:37 AM PDT 23
Finished	May 28 03:20:44 AM PDT 23
Peak memory	201008 kb
Host	smart-3e7e2d58-3ece-4c24-a647-946a38a02287
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185263798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.3185263798
Directory	/workspace/2.usbdev_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.1077086075
Short name	T22
Test name
Test status
Simulation time	68908706 ps
CPU time	0.74 seconds
Started	May 28 03:20:39 AM PDT 23
Finished	May 28 03:20:40 AM PDT 23
Peak memory	198404 kb
Host	smart-42c71f28-82f7-4d6f-b248-a0063f7c2784
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077086075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.1077086075
Directory	/workspace/2.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1449127764
Short name	T99
Test name
Test status
Simulation time	53677328 ps
CPU time	1.24 seconds
Started	May 28 03:20:35 AM PDT 23
Finished	May 28 03:20:41 AM PDT 23
Peak memory	201264 kb
Host	smart-10b8fc97-852e-4984-8103-ad0117ade717
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449127764 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_mem_rw_with_rand_reset.1449127764
Directory	/workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_rw.189376900
Short name	T137
Test name
Test status
Simulation time	18396421 ps
CPU time	0.77 seconds
Started	May 28 03:20:37 AM PDT 23
Finished	May 28 03:20:40 AM PDT 23
Peak memory	200312 kb
Host	smart-560fe3fd-b7a8-4a6c-9236-4cc2f8fe8d91
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189376900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.189376900
Directory	/workspace/2.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_intr_test.606247446
Short name	T25
Test name
Test status
Simulation time	24349061 ps
CPU time	0.64 seconds
Started	May 28 03:20:38 AM PDT 23
Finished	May 28 03:20:40 AM PDT 23
Peak memory	198156 kb
Host	smart-deba9658-aaf6-483c-945a-03d16ed5f92b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=606247446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.606247446
Directory	/workspace/2.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.2368940763
Short name	T141
Test name
Test status
Simulation time	58649339 ps
CPU time	2.18 seconds
Started	May 28 03:20:39 AM PDT 23
Finished	May 28 03:20:42 AM PDT 23
Peak memory	198128 kb
Host	smart-40fe44ba-ef00-46d4-8371-430532c5d11c
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2368940763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.2368940763
Directory	/workspace/2.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_mem_walk.3637228799
Short name	T140
Test name
Test status
Simulation time	711136765 ps
CPU time	4.38 seconds
Started	May 28 03:20:36 AM PDT 23
Finished	May 28 03:20:44 AM PDT 23
Peak memory	201076 kb
Host	smart-a472ab24-d002-4080-9fa9-702d1428b090
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3637228799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.3637228799
Directory	/workspace/2.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/21.usbdev_intr_test.4090815009
Short name	T75
Test name
Test status
Simulation time	31473563 ps
CPU time	0.62 seconds
Started	May 28 03:21:28 AM PDT 23
Finished	May 28 03:21:29 AM PDT 23
Peak memory	195764 kb
Host	smart-0979b39a-9b4b-4897-9bf6-198e96735b44
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4090815009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.4090815009
Directory	/workspace/21.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.usbdev_intr_test.801401940
Short name	T115
Test name
Test status
Simulation time	18364902 ps
CPU time	0.62 seconds
Started	May 28 03:21:35 AM PDT 23
Finished	May 28 03:21:36 AM PDT 23
Peak memory	196892 kb
Host	smart-e0921c56-be38-46e8-9211-c56abfcc882b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=801401940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.801401940
Directory	/workspace/22.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.usbdev_intr_test.3620571460
Short name	T79
Test name
Test status
Simulation time	15568970 ps
CPU time	0.64 seconds
Started	May 28 03:21:18 AM PDT 23
Finished	May 28 03:21:19 AM PDT 23
Peak memory	198124 kb
Host	smart-8b20de28-ce43-4828-bae0-6ac19b08df7f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3620571460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.3620571460
Directory	/workspace/23.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.usbdev_intr_test.4073862912
Short name	T113
Test name
Test status
Simulation time	35674431 ps
CPU time	0.66 seconds
Started	May 28 03:21:27 AM PDT 23
Finished	May 28 03:21:28 AM PDT 23
Peak memory	198144 kb
Host	smart-173356ea-1b47-4693-9c14-aa97e3ba03fc
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4073862912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.4073862912
Directory	/workspace/24.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.usbdev_intr_test.1994271107
Short name	T117
Test name
Test status
Simulation time	31945812 ps
CPU time	0.7 seconds
Started	May 28 03:21:16 AM PDT 23
Finished	May 28 03:21:16 AM PDT 23
Peak memory	196664 kb
Host	smart-fcd1ff76-a515-4451-8a76-08aca59d677a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1994271107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.1994271107
Directory	/workspace/25.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.usbdev_intr_test.394506968
Short name	T41
Test name
Test status
Simulation time	38390351 ps
CPU time	0.66 seconds
Started	May 28 03:21:28 AM PDT 23
Finished	May 28 03:21:29 AM PDT 23
Peak memory	195824 kb
Host	smart-e82db423-7764-4cbb-bf74-e5c856837b81
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=394506968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.394506968
Directory	/workspace/27.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.usbdev_intr_test.1744319940
Short name	T58
Test name
Test status
Simulation time	18751056 ps
CPU time	0.61 seconds
Started	May 28 03:21:29 AM PDT 23
Finished	May 28 03:21:30 AM PDT 23
Peak memory	196656 kb
Host	smart-1b7df992-feff-493f-a5e4-9f395268158a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1744319940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.1744319940
Directory	/workspace/28.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.usbdev_intr_test.767481802
Short name	T36
Test name
Test status
Simulation time	42018948 ps
CPU time	0.63 seconds
Started	May 28 03:21:28 AM PDT 23
Finished	May 28 03:21:29 AM PDT 23
Peak memory	196676 kb
Host	smart-28b68d99-a375-4c3a-b3fb-24f8260a53c3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=767481802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.767481802
Directory	/workspace/29.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.4013973338
Short name	T90
Test name
Test status
Simulation time	79860109 ps
CPU time	1.82 seconds
Started	May 28 03:20:39 AM PDT 23
Finished	May 28 03:20:41 AM PDT 23
Peak memory	200032 kb
Host	smart-7ad2833b-20e5-4302-9594-bad97e735ff1
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013973338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.4013973338
Directory	/workspace/3.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.209800984
Short name	T153
Test name
Test status
Simulation time	180420882 ps
CPU time	4.54 seconds
Started	May 28 03:20:37 AM PDT 23
Finished	May 28 03:20:44 AM PDT 23
Peak memory	201000 kb
Host	smart-2e5ce70f-7c00-42db-bb89-8799de6930bb
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209800984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.209800984
Directory	/workspace/3.usbdev_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.1343244464
Short name	T152
Test name
Test status
Simulation time	39365954 ps
CPU time	0.7 seconds
Started	May 28 03:20:39 AM PDT 23
Finished	May 28 03:20:40 AM PDT 23
Peak memory	197692 kb
Host	smart-2029ebb3-afc2-4120-bc97-2514b343da6d
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343244464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.1343244464
Directory	/workspace/3.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.399622109
Short name	T35
Test name
Test status
Simulation time	273499896 ps
CPU time	2.1 seconds
Started	May 28 03:20:37 AM PDT 23
Finished	May 28 03:20:42 AM PDT 23
Peak memory	209572 kb
Host	smart-dbef009a-ca03-4d99-833b-48b5b44bd264
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399622109 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_mem_rw_with_rand_reset.399622109
Directory	/workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_rw.78915383
Short name	T39
Test name
Test status
Simulation time	23282462 ps
CPU time	0.76 seconds
Started	May 28 03:20:37 AM PDT 23
Finished	May 28 03:20:40 AM PDT 23
Peak memory	200212 kb
Host	smart-584b2fc9-1749-45ec-bcb8-36d1e08c7c06
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78915383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.78915383
Directory	/workspace/3.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_intr_test.2968377437
Short name	T157
Test name
Test status
Simulation time	17945360 ps
CPU time	0.64 seconds
Started	May 28 03:20:38 AM PDT 23
Finished	May 28 03:20:40 AM PDT 23
Peak memory	196788 kb
Host	smart-f194f605-e25f-40b5-9282-67918c2ca77e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2968377437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.2968377437
Directory	/workspace/3.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.157333486
Short name	T125
Test name
Test status
Simulation time	165599321 ps
CPU time	2.42 seconds
Started	May 28 03:20:39 AM PDT 23
Finished	May 28 03:20:42 AM PDT 23
Peak memory	198096 kb
Host	smart-6f218223-52a0-49b2-b6bb-59f2a1e5042d
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=157333486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.157333486
Directory	/workspace/3.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_mem_walk.1512443667
Short name	T107
Test name
Test status
Simulation time	165890473 ps
CPU time	3.8 seconds
Started	May 28 03:20:37 AM PDT 23
Finished	May 28 03:20:43 AM PDT 23
Peak memory	201148 kb
Host	smart-248c93c7-2946-4f12-882c-009ad09e7fd5
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1512443667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.1512443667
Directory	/workspace/3.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.587456027
Short name	T151
Test name
Test status
Simulation time	30327398 ps
CPU time	1.01 seconds
Started	May 28 03:20:39 AM PDT 23
Finished	May 28 03:20:40 AM PDT 23
Peak memory	199812 kb
Host	smart-3fe9ff19-2a8c-45c8-b985-4c7b9135dc4b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587456027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_cs r_outstanding.587456027
Directory	/workspace/3.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_tl_errors.3963523694
Short name	T27
Test name
Test status
Simulation time	255028745 ps
CPU time	2.88 seconds
Started	May 28 03:20:38 AM PDT 23
Finished	May 28 03:20:42 AM PDT 23
Peak memory	201316 kb
Host	smart-53b9319f-72ce-4f0a-84af-4ca01cb45e69
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3963523694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.3963523694
Directory	/workspace/3.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/31.usbdev_intr_test.716825200
Short name	T61
Test name
Test status
Simulation time	21556500 ps
CPU time	0.61 seconds
Started	May 28 03:21:17 AM PDT 23
Finished	May 28 03:21:18 AM PDT 23
Peak memory	198112 kb
Host	smart-22b292c7-9a8d-4605-8d52-9fec6c2f2121
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=716825200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.716825200
Directory	/workspace/31.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.usbdev_intr_test.3506485639
Short name	T81
Test name
Test status
Simulation time	20198328 ps
CPU time	0.61 seconds
Started	May 28 03:21:21 AM PDT 23
Finished	May 28 03:21:22 AM PDT 23
Peak memory	198292 kb
Host	smart-fdb02f24-1832-47f0-bcb1-8ba66b9b7439
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3506485639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.3506485639
Directory	/workspace/32.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.usbdev_intr_test.3270809988
Short name	T108
Test name
Test status
Simulation time	17874981 ps
CPU time	0.61 seconds
Started	May 28 03:21:23 AM PDT 23
Finished	May 28 03:21:24 AM PDT 23
Peak memory	196776 kb
Host	smart-ca37d21f-46de-4baf-8542-d7e136a23417
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3270809988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.3270809988
Directory	/workspace/33.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.usbdev_intr_test.306576213
Short name	T143
Test name
Test status
Simulation time	45035672 ps
CPU time	0.65 seconds
Started	May 28 03:21:27 AM PDT 23
Finished	May 28 03:21:28 AM PDT 23
Peak memory	196692 kb
Host	smart-c2153128-19c7-427a-bb02-979f38eb7f1f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=306576213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.306576213
Directory	/workspace/34.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.usbdev_intr_test.3821670662
Short name	T95
Test name
Test status
Simulation time	43345427 ps
CPU time	0.63 seconds
Started	May 28 03:21:22 AM PDT 23
Finished	May 28 03:21:23 AM PDT 23
Peak memory	198076 kb
Host	smart-5cf50633-2cda-4e5b-ab4a-7f7e3156f359
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3821670662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.3821670662
Directory	/workspace/35.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.usbdev_intr_test.102062425
Short name	T24
Test name
Test status
Simulation time	21237029 ps
CPU time	0.61 seconds
Started	May 28 03:21:22 AM PDT 23
Finished	May 28 03:21:23 AM PDT 23
Peak memory	198288 kb
Host	smart-d5c3c71f-c5b2-48c6-a9db-378d01603352
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=102062425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.102062425
Directory	/workspace/37.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.usbdev_intr_test.1299887093
Short name	T69
Test name
Test status
Simulation time	16150057 ps
CPU time	0.6 seconds
Started	May 28 03:21:26 AM PDT 23
Finished	May 28 03:21:27 AM PDT 23
Peak memory	196784 kb
Host	smart-58a32431-b645-467d-9f7e-7ac9a97dcc10
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1299887093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.1299887093
Directory	/workspace/38.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.usbdev_intr_test.1463719490
Short name	T105
Test name
Test status
Simulation time	16937281 ps
CPU time	0.64 seconds
Started	May 28 03:21:30 AM PDT 23
Finished	May 28 03:21:31 AM PDT 23
Peak memory	196212 kb
Host	smart-5b0d3c64-105f-4301-958d-4cb454794789
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1463719490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.1463719490
Directory	/workspace/39.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2869324247
Short name	T146
Test name
Test status
Simulation time	125326598 ps
CPU time	3 seconds
Started	May 28 03:20:36 AM PDT 23
Finished	May 28 03:20:42 AM PDT 23
Peak memory	199796 kb
Host	smart-9b86dbee-b778-479b-b8f3-471106c66f38
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869324247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.2869324247
Directory	/workspace/4.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.1488216107
Short name	T123
Test name
Test status
Simulation time	371299573 ps
CPU time	8.74 seconds
Started	May 28 03:20:39 AM PDT 23
Finished	May 28 03:20:48 AM PDT 23
Peak memory	201128 kb
Host	smart-fcca9ccb-c779-4817-9e96-f7baecab9472
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488216107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.1488216107
Directory	/workspace/4.usbdev_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.1614366612
Short name	T4
Test name
Test status
Simulation time	30982164 ps
CPU time	1.17 seconds
Started	May 28 03:20:40 AM PDT 23
Finished	May 28 03:20:42 AM PDT 23
Peak memory	201408 kb
Host	smart-3329923d-c8b2-40af-9753-cce518ee0924
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614366612 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_mem_rw_with_rand_reset.1614366612
Directory	/workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_rw.3078986453
Short name	T92
Test name
Test status
Simulation time	59944341 ps
CPU time	0.98 seconds
Started	May 28 03:20:37 AM PDT 23
Finished	May 28 03:20:41 AM PDT 23
Peak memory	200828 kb
Host	smart-df470dd8-7096-4b04-aa2f-41b06200a935
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078986453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.3078986453
Directory	/workspace/4.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.1500244727
Short name	T91
Test name
Test status
Simulation time	34749084 ps
CPU time	1.3 seconds
Started	May 28 03:20:37 AM PDT 23
Finished	May 28 03:20:41 AM PDT 23
Peak memory	200996 kb
Host	smart-838160b9-1f81-4252-a87d-35cd440c78a5
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1500244727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.1500244727
Directory	/workspace/4.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_mem_walk.239556157
Short name	T133
Test name
Test status
Simulation time	696344166 ps
CPU time	4.45 seconds
Started	May 28 03:20:39 AM PDT 23
Finished	May 28 03:20:44 AM PDT 23
Peak memory	201196 kb
Host	smart-0ffb7c91-439d-4738-8f39-87a99fef2ad9
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=239556157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.239556157
Directory	/workspace/4.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.4033891486
Short name	T47
Test name
Test status
Simulation time	31329228 ps
CPU time	1 seconds
Started	May 28 03:20:38 AM PDT 23
Finished	May 28 03:20:40 AM PDT 23
Peak memory	200312 kb
Host	smart-4ce5f8d8-fe9e-45b4-aace-7f98e3511c4f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033891486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_c sr_outstanding.4033891486
Directory	/workspace/4.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/40.usbdev_intr_test.1886762665
Short name	T83
Test name
Test status
Simulation time	29246541 ps
CPU time	0.64 seconds
Started	May 28 03:21:32 AM PDT 23
Finished	May 28 03:21:33 AM PDT 23
Peak memory	198048 kb
Host	smart-99b29adc-0086-49d9-915b-df5426b13745
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1886762665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.1886762665
Directory	/workspace/40.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.usbdev_intr_test.10350054
Short name	T64
Test name
Test status
Simulation time	15553259 ps
CPU time	0.64 seconds
Started	May 28 03:21:32 AM PDT 23
Finished	May 28 03:21:33 AM PDT 23
Peak memory	196712 kb
Host	smart-58457605-5815-4152-89fd-523957392e23
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=10350054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.10350054
Directory	/workspace/41.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.usbdev_intr_test.4109221908
Short name	T66
Test name
Test status
Simulation time	50257163 ps
CPU time	0.71 seconds
Started	May 28 03:21:36 AM PDT 23
Finished	May 28 03:21:37 AM PDT 23
Peak memory	196736 kb
Host	smart-40f3cd80-8e7b-40c0-9fd7-48a90f8a2c75
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4109221908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.4109221908
Directory	/workspace/42.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.usbdev_intr_test.1218940379
Short name	T102
Test name
Test status
Simulation time	13010293 ps
CPU time	0.63 seconds
Started	May 28 03:21:31 AM PDT 23
Finished	May 28 03:21:32 AM PDT 23
Peak memory	198236 kb
Host	smart-c6e4adde-923c-4544-a51f-01f6cf8777ae
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1218940379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.1218940379
Directory	/workspace/43.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.usbdev_intr_test.517856155
Short name	T26
Test name
Test status
Simulation time	13340348 ps
CPU time	0.63 seconds
Started	May 28 03:21:25 AM PDT 23
Finished	May 28 03:21:26 AM PDT 23
Peak memory	196724 kb
Host	smart-061be36d-1b85-4a9b-ba57-9d4ebf438eac
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=517856155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.517856155
Directory	/workspace/44.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.usbdev_intr_test.2545485793
Short name	T147
Test name
Test status
Simulation time	20838099 ps
CPU time	0.67 seconds
Started	May 28 03:21:33 AM PDT 23
Finished	May 28 03:21:34 AM PDT 23
Peak memory	196760 kb
Host	smart-2df754f4-48a5-48ff-8f6b-90f1ecb3e798
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2545485793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.2545485793
Directory	/workspace/45.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.usbdev_intr_test.1397523407
Short name	T65
Test name
Test status
Simulation time	13638797 ps
CPU time	0.63 seconds
Started	May 28 03:21:36 AM PDT 23
Finished	May 28 03:21:37 AM PDT 23
Peak memory	198080 kb
Host	smart-2c85bde5-b387-4d7c-b17a-1818f60bdba9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1397523407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.1397523407
Directory	/workspace/46.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.usbdev_intr_test.2543430237
Short name	T109
Test name
Test status
Simulation time	19861037 ps
CPU time	0.6 seconds
Started	May 28 03:21:26 AM PDT 23
Finished	May 28 03:21:26 AM PDT 23
Peak memory	197880 kb
Host	smart-72d981ee-8541-4228-9842-39cee62c1ed0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2543430237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.2543430237
Directory	/workspace/48.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.usbdev_intr_test.2473059958
Short name	T94
Test name
Test status
Simulation time	57554972 ps
CPU time	0.61 seconds
Started	May 28 03:21:37 AM PDT 23
Finished	May 28 03:21:38 AM PDT 23
Peak memory	197928 kb
Host	smart-dd135dce-4ff8-47ad-9d5b-13ccfa9d9bbf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2473059958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.2473059958
Directory	/workspace/49.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.3019064381
Short name	T72
Test name
Test status
Simulation time	51125107 ps
CPU time	2.02 seconds
Started	May 28 03:20:42 AM PDT 23
Finished	May 28 03:20:44 AM PDT 23
Peak memory	209280 kb
Host	smart-23ac5835-a974-402f-80de-ce73f0ed5f4c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019064381 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_mem_rw_with_rand_reset.3019064381
Directory	/workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_csr_rw.3634905192
Short name	T127
Test name
Test status
Simulation time	71210979 ps
CPU time	1.07 seconds
Started	May 28 03:20:42 AM PDT 23
Finished	May 28 03:20:44 AM PDT 23
Peak memory	200920 kb
Host	smart-59d8dd1e-8630-4ee0-a2f6-83ebe1fb0429
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634905192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.3634905192
Directory	/workspace/5.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_intr_test.1123562856
Short name	T134
Test name
Test status
Simulation time	20068544 ps
CPU time	0.67 seconds
Started	May 28 03:20:39 AM PDT 23
Finished	May 28 03:20:40 AM PDT 23
Peak memory	196684 kb
Host	smart-b3202ee2-e538-4d4b-af8a-38464da870cc
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1123562856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.1123562856
Directory	/workspace/5.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.4054794349
Short name	T18
Test name
Test status
Simulation time	99778653 ps
CPU time	1.15 seconds
Started	May 28 03:20:47 AM PDT 23
Finished	May 28 03:20:48 AM PDT 23
Peak memory	201204 kb
Host	smart-5f02be35-094c-4ca1-a6c3-b324abffaf97
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054794349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_c sr_outstanding.4054794349
Directory	/workspace/5.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_tl_errors.3914479713
Short name	T150
Test name
Test status
Simulation time	90008738 ps
CPU time	2.85 seconds
Started	May 28 03:20:42 AM PDT 23
Finished	May 28 03:20:45 AM PDT 23
Peak memory	201292 kb
Host	smart-c7e86d72-a9ae-4e6f-903d-8f2395add7a9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3914479713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.3914479713
Directory	/workspace/5.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.927962753
Short name	T13
Test name
Test status
Simulation time	71368099 ps
CPU time	2.37 seconds
Started	May 28 03:20:42 AM PDT 23
Finished	May 28 03:20:45 AM PDT 23
Peak memory	209524 kb
Host	smart-2b6c3dd3-2c06-44d1-b656-f5db303772b8
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927962753 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_mem_rw_with_rand_reset.927962753
Directory	/workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1684663990
Short name	T19
Test name
Test status
Simulation time	60885749 ps
CPU time	0.97 seconds
Started	May 28 03:20:42 AM PDT 23
Finished	May 28 03:20:44 AM PDT 23
Peak memory	200940 kb
Host	smart-78668820-6614-4560-b631-1e9e5516aef2
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684663990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.1684663990
Directory	/workspace/6.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_intr_test.1204034388
Short name	T139
Test name
Test status
Simulation time	20765367 ps
CPU time	0.65 seconds
Started	May 28 03:20:42 AM PDT 23
Finished	May 28 03:20:43 AM PDT 23
Peak memory	198052 kb
Host	smart-36152e54-6f63-4c50-934b-c917af4c3236
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1204034388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.1204034388
Directory	/workspace/6.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.2136395973
Short name	T77
Test name
Test status
Simulation time	31311983 ps
CPU time	1.05 seconds
Started	May 28 03:20:44 AM PDT 23
Finished	May 28 03:20:46 AM PDT 23
Peak memory	201116 kb
Host	smart-b9eb8036-8384-4b94-9c72-e647a37d2cbf
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136395973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_c sr_outstanding.2136395973
Directory	/workspace/6.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_tl_errors.3030511278
Short name	T16
Test name
Test status
Simulation time	52405410 ps
CPU time	1.35 seconds
Started	May 28 03:20:42 AM PDT 23
Finished	May 28 03:20:43 AM PDT 23
Peak memory	201372 kb
Host	smart-764b5487-07b6-48b6-a209-405f4a5d9c2f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3030511278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.3030511278
Directory	/workspace/6.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1435389467
Short name	T154
Test name
Test status
Simulation time	91309779 ps
CPU time	1.56 seconds
Started	May 28 03:20:42 AM PDT 23
Finished	May 28 03:20:43 AM PDT 23
Peak memory	201328 kb
Host	smart-e22bfb9f-60ef-4d4e-9620-a74a6c2f9767
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435389467 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_mem_rw_with_rand_reset.1435389467
Directory	/workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_csr_rw.1915610827
Short name	T43
Test name
Test status
Simulation time	43866413 ps
CPU time	0.78 seconds
Started	May 28 03:20:45 AM PDT 23
Finished	May 28 03:20:46 AM PDT 23
Peak memory	200864 kb
Host	smart-d95bdffb-7f51-4ae8-ba9e-21003614236b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915610827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.1915610827
Directory	/workspace/7.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_intr_test.4153620605
Short name	T67
Test name
Test status
Simulation time	17211852 ps
CPU time	0.59 seconds
Started	May 28 03:20:42 AM PDT 23
Finished	May 28 03:20:43 AM PDT 23
Peak memory	196452 kb
Host	smart-d26d73f0-9aaa-49de-8a2b-a93a38fa09c4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4153620605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.4153620605
Directory	/workspace/7.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.2713861984
Short name	T120
Test name
Test status
Simulation time	106400122 ps
CPU time	1.53 seconds
Started	May 28 03:20:42 AM PDT 23
Finished	May 28 03:20:45 AM PDT 23
Peak memory	201224 kb
Host	smart-a37c47c5-27a0-4137-befb-c391f7225d5c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713861984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_c sr_outstanding.2713861984
Directory	/workspace/7.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_tl_errors.4164701103
Short name	T126
Test name
Test status
Simulation time	41459493 ps
CPU time	1.52 seconds
Started	May 28 03:20:43 AM PDT 23
Finished	May 28 03:20:45 AM PDT 23
Peak memory	201216 kb
Host	smart-b1f1529c-49ee-4a56-9571-48dac2f70789
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4164701103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.4164701103
Directory	/workspace/7.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.3996850888
Short name	T138
Test name
Test status
Simulation time	25139182 ps
CPU time	0.83 seconds
Started	May 28 03:20:39 AM PDT 23
Finished	May 28 03:20:40 AM PDT 23
Peak memory	201216 kb
Host	smart-06dda7f6-cdb3-4ed5-a2d6-b3aba2a4e64f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996850888 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_mem_rw_with_rand_reset.3996850888
Directory	/workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_csr_rw.3645691545
Short name	T54
Test name
Test status
Simulation time	66949489 ps
CPU time	0.97 seconds
Started	May 28 03:20:45 AM PDT 23
Finished	May 28 03:20:46 AM PDT 23
Peak memory	201040 kb
Host	smart-974dcfca-3776-428f-b933-4d5c07f81670
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645691545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.3645691545
Directory	/workspace/8.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_intr_test.1007153264
Short name	T59
Test name
Test status
Simulation time	19711315 ps
CPU time	0.61 seconds
Started	May 28 03:20:38 AM PDT 23
Finished	May 28 03:20:40 AM PDT 23
Peak memory	198028 kb
Host	smart-d5b281a8-5a93-46c1-9484-ab498152c1c7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1007153264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.1007153264
Directory	/workspace/8.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.4171399293
Short name	T119
Test name
Test status
Simulation time	72829409 ps
CPU time	0.94 seconds
Started	May 28 03:20:40 AM PDT 23
Finished	May 28 03:20:41 AM PDT 23
Peak memory	199076 kb
Host	smart-45ec6144-e9db-465a-9000-57c3a33d27dc
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171399293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_c sr_outstanding.4171399293
Directory	/workspace/8.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_tl_errors.1028107946
Short name	T87
Test name
Test status
Simulation time	128735039 ps
CPU time	1.87 seconds
Started	May 28 03:20:48 AM PDT 23
Finished	May 28 03:20:50 AM PDT 23
Peak memory	201272 kb
Host	smart-412c8c32-bf58-4546-a0c3-e189f08304ae
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1028107946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.1028107946
Directory	/workspace/8.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2087119513
Short name	T131
Test name
Test status
Simulation time	54945564 ps
CPU time	0.92 seconds
Started	May 28 03:20:43 AM PDT 23
Finished	May 28 03:20:45 AM PDT 23
Peak memory	201028 kb
Host	smart-2ba4d436-2b4f-4a8c-a947-95c0168af14b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087119513 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_mem_rw_with_rand_reset.2087119513
Directory	/workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_csr_rw.672390240
Short name	T97
Test name
Test status
Simulation time	61592948 ps
CPU time	1.03 seconds
Started	May 28 03:20:48 AM PDT 23
Finished	May 28 03:20:49 AM PDT 23
Peak memory	200944 kb
Host	smart-7a8d4a91-0333-4a3c-81f5-5599036d8a2c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672390240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.672390240
Directory	/workspace/9.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_intr_test.2709395368
Short name	T122
Test name
Test status
Simulation time	52173287 ps
CPU time	0.65 seconds
Started	May 28 03:20:43 AM PDT 23
Finished	May 28 03:20:44 AM PDT 23
Peak memory	196636 kb
Host	smart-05d932f1-4892-4a45-8f4f-ce9175334122
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2709395368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.2709395368
Directory	/workspace/9.usbdev_intr_test/latest