Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=16}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=16}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=16}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	68	0	68	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=16}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	17	0	17	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=16}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	68	0	68	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	268	1		T4	5		T10	5		T11	2
all_values[1]	268	1		T4	5		T10	5		T11	2
all_values[2]	268	1		T4	5		T10	5		T11	2
all_values[3]	268	1		T4	5		T10	5		T11	2
all_values[4]	268	1		T4	5		T10	5		T11	2
all_values[5]	268	1		T4	5		T10	5		T11	2
all_values[6]	268	1		T4	5		T10	5		T11	2
all_values[7]	268	1		T4	5		T10	5		T11	2
all_values[8]	268	1		T4	5		T10	5		T11	2
all_values[9]	268	1		T4	5		T10	5		T11	2
all_values[10]	268	1		T4	5		T10	5		T11	2
all_values[11]	268	1		T4	5		T10	5		T11	2
all_values[12]	268	1		T4	5		T10	5		T11	2
all_values[13]	268	1		T4	5		T10	5		T11	2
all_values[14]	268	1		T4	5		T10	5		T11	2
all_values[15]	268	1		T4	5		T10	5		T11	2
all_values[16]	268	1		T4	5		T10	5		T11	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2623	1		T4	47		T10	44		T11	34
auto[1]	1933	1		T4	38		T10	41		T23	62

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1204	1		T4	18		T10	10		T11	34
auto[1]	3352	1		T4	67		T10	75		T23	128

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	68	0	68	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	54	1		T11	2		T15	2		T16	2
all_values[0]	auto[0]	auto[1]	88	1		T4	4		T10	1		T23	1
all_values[0]	auto[1]	auto[0]	16	1		T10	1		T24	1		T34	1
all_values[0]	auto[1]	auto[1]	110	1		T4	1		T10	3		T23	7
all_values[1]	auto[0]	auto[0]	46	1		T4	1		T11	2		T23	1
all_values[1]	auto[0]	auto[1]	121	1		T10	4		T23	6		T24	4
all_values[1]	auto[1]	auto[0]	10	1		T24	1		T35	1		T68	1
all_values[1]	auto[1]	auto[1]	91	1		T4	4		T10	1		T23	1
all_values[2]	auto[0]	auto[0]	49	1		T4	1		T11	2		T15	2
all_values[2]	auto[0]	auto[1]	116	1		T4	3		T10	4		T23	6
all_values[2]	auto[1]	auto[0]	19	1		T35	5		T62	1		T68	1
all_values[2]	auto[1]	auto[1]	84	1		T4	1		T10	1		T23	2
all_values[3]	auto[0]	auto[0]	62	1		T4	3		T11	2		T15	2
all_values[3]	auto[0]	auto[1]	102	1		T10	4		T23	5		T24	1
all_values[3]	auto[1]	auto[0]	25	1		T4	2		T24	1		T34	1
all_values[3]	auto[1]	auto[1]	79	1		T10	1		T23	3		T24	6
all_values[4]	auto[0]	auto[0]	56	1		T11	2		T15	2		T16	2
all_values[4]	auto[0]	auto[1]	113	1		T4	5		T10	4		T23	2
all_values[4]	auto[1]	auto[0]	10	1		T24	1		T35	1		T68	3
all_values[4]	auto[1]	auto[1]	89	1		T10	1		T23	6		T24	4
all_values[5]	auto[0]	auto[0]	53	1		T4	1		T11	2		T23	2
all_values[5]	auto[0]	auto[1]	98	1		T10	4		T23	3		T24	2
all_values[5]	auto[1]	auto[0]	8	1		T4	1		T23	1		T34	1
all_values[5]	auto[1]	auto[1]	109	1		T4	3		T10	1		T23	2
all_values[6]	auto[0]	auto[0]	51	1		T11	2		T15	2		T16	2
all_values[6]	auto[0]	auto[1]	94	1		T4	4		T10	3		T23	6
all_values[6]	auto[1]	auto[0]	20	1		T4	1		T25	1		T35	1
all_values[6]	auto[1]	auto[1]	103	1		T10	2		T23	2		T24	4
all_values[7]	auto[0]	auto[0]	60	1		T10	1		T11	2		T15	2
all_values[7]	auto[0]	auto[1]	104	1		T4	4		T10	3		T23	1
all_values[7]	auto[1]	auto[0]	12	1		T10	1		T34	1		T68	1
all_values[7]	auto[1]	auto[1]	92	1		T4	1		T23	7		T24	4
all_values[8]	auto[0]	auto[0]	58	1		T11	2		T23	1		T15	2
all_values[8]	auto[0]	auto[1]	94	1		T10	1		T23	4		T24	1
all_values[8]	auto[1]	auto[0]	18	1		T34	1		T35	1		T69	1
all_values[8]	auto[1]	auto[1]	98	1		T4	5		T10	4		T23	3
all_values[9]	auto[0]	auto[0]	56	1		T11	2		T15	2		T16	2
all_values[9]	auto[0]	auto[1]	105	1		T4	2		T10	3		T23	6
all_values[9]	auto[1]	auto[0]	19	1		T24	2		T34	2		T61	1
all_values[9]	auto[1]	auto[1]	88	1		T4	3		T10	2		T23	2
all_values[10]	auto[0]	auto[0]	54	1		T11	2		T23	1		T15	2
all_values[10]	auto[0]	auto[1]	89	1		T4	2		T10	1		T23	3
all_values[10]	auto[1]	auto[0]	19	1		T10	1		T24	6		T68	1
all_values[10]	auto[1]	auto[1]	106	1		T4	3		T10	3		T23	4
all_values[11]	auto[0]	auto[0]	57	1		T4	2		T11	2		T15	2
all_values[11]	auto[0]	auto[1]	85	1		T4	3		T10	1		T23	3
all_values[11]	auto[1]	auto[0]	21	1		T23	1		T25	2		T61	4
all_values[11]	auto[1]	auto[1]	105	1		T10	4		T23	4		T24	3
all_values[12]	auto[0]	auto[0]	53	1		T4	1		T11	2		T23	1
all_values[12]	auto[0]	auto[1]	98	1		T10	3		T23	2		T24	1
all_values[12]	auto[1]	auto[0]	12	1		T4	1		T24	1		T68	1
all_values[12]	auto[1]	auto[1]	105	1		T4	3		T10	2		T23	5
all_values[13]	auto[0]	auto[0]	67	1		T4	1		T10	3		T11	2
all_values[13]	auto[0]	auto[1]	85	1		T4	3		T23	4		T25	5
all_values[13]	auto[1]	auto[0]	29	1		T4	1		T10	2		T24	2
all_values[13]	auto[1]	auto[1]	87	1		T23	4		T24	3		T25	2
all_values[14]	auto[0]	auto[0]	48	1		T4	1		T11	2		T15	2
all_values[14]	auto[0]	auto[1]	101	1		T4	3		T10	1		T23	2
all_values[14]	auto[1]	auto[0]	17	1		T10	1		T24	1		T70	1
all_values[14]	auto[1]	auto[1]	102	1		T4	1		T10	3		T23	6
all_values[15]	auto[0]	auto[0]	49	1		T11	2		T15	2		T16	2
all_values[15]	auto[0]	auto[1]	93	1		T4	1		T10	1		T23	7
all_values[15]	auto[1]	auto[0]	5	1		T69	1		T71	2		T72	1
all_values[15]	auto[1]	auto[1]	121	1		T4	4		T10	4		T23	1
all_values[16]	auto[0]	auto[0]	60	1		T4	1		T11	2		T15	2
all_values[16]	auto[0]	auto[1]	104	1		T4	1		T10	2		T23	7
all_values[16]	auto[1]	auto[0]	11	1		T73	5		T69	1		T71	1
all_values[16]	auto[1]	auto[1]	93	1		T4	3		T10	3		T23	1