Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
77.04	89.84	75.67	95.05	3.12	87.16	92.01	96.47

Total tests in report: 149

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
53.02	53.02	66.79	66.79	59.24	59.24	79.35	79.35	0.00	0.00	72.41	72.41	66.60	66.60	26.77	26.77	/workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.2393896759
64.91	11.89	88.83	22.04	71.60	12.36	88.82	9.46	3.12	3.12	86.81	14.40	87.30	20.70	27.88	1.12	/workspace/coverage/default/0.usbdev_sec_cm.3203828703
71.94	7.03	89.94	1.11	73.16	1.56	92.26	3.44	3.12	0.00	86.81	0.00	87.30	0.00	71.00	43.12	/workspace/coverage/cover_reg_top/33.usbdev_intr_test.3105948824
73.71	1.77	89.99	0.04	74.28	1.13	93.33	1.08	3.12	0.00	86.85	0.04	88.11	0.82	80.30	9.29	/workspace/coverage/cover_reg_top/17.usbdev_tl_errors.1410588467
74.76	1.04	89.99	0.00	74.28	0.00	93.55	0.22	3.12	0.00	86.85	0.00	88.32	0.20	87.17	6.88	/workspace/coverage/cover_reg_top/28.usbdev_intr_test.1958240488
75.49	0.73	90.01	0.02	75.33	1.05	94.41	0.86	3.12	0.00	86.98	0.13	91.39	3.07	87.17	0.00	/workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2098105954
76.11	0.62	90.03	0.02	75.41	0.08	95.05	0.65	3.12	0.00	87.03	0.04	91.39	0.00	90.71	3.53	/workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.898820348
76.42	0.32	90.03	0.00	75.41	0.00	95.05	0.00	3.12	0.00	87.03	0.00	91.39	0.00	92.94	2.23	/workspace/coverage/cover_reg_top/9.usbdev_intr_test.2168333583
76.58	0.16	90.03	0.00	75.41	0.00	95.05	0.00	3.12	0.00	87.03	0.00	91.39	0.00	94.05	1.12	/workspace/coverage/cover_reg_top/11.usbdev_intr_test.1623426135
76.70	0.11	90.05	0.02	75.41	0.00	95.05	0.00	3.12	0.00	87.03	0.00	91.60	0.20	94.61	0.56	/workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.2582515925
76.78	0.08	90.05	0.00	75.41	0.00	95.05	0.00	3.12	0.00	87.03	0.00	91.60	0.00	95.17	0.56	/workspace/coverage/cover_reg_top/16.usbdev_intr_test.2829215162
76.85	0.08	90.05	0.00	75.54	0.13	95.05	0.00	3.12	0.00	87.03	0.00	92.01	0.41	95.17	0.00	/workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.3177621950
76.91	0.05	90.05	0.00	75.54	0.00	95.05	0.00	3.12	0.00	87.03	0.00	92.01	0.00	95.54	0.37	/workspace/coverage/cover_reg_top/1.usbdev_intr_test.4217189164
76.96	0.05	90.05	0.00	75.54	0.00	95.05	0.00	3.12	0.00	87.03	0.00	92.01	0.00	95.91	0.37	/workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.795209662
76.99	0.03	90.05	0.00	75.54	0.00	95.05	0.00	3.12	0.00	87.03	0.00	92.01	0.00	96.10	0.19	/workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.3851044141
77.01	0.03	90.05	0.00	75.54	0.00	95.05	0.00	3.12	0.00	87.03	0.00	92.01	0.00	96.28	0.19	/workspace/coverage/cover_reg_top/42.usbdev_intr_test.3718946785
77.04	0.03	90.05	0.00	75.54	0.00	95.05	0.00	3.12	0.00	87.03	0.00	92.01	0.00	96.47	0.19	/workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.1840079369
77.06	0.02	90.22	0.17	75.54	0.00	95.05	0.00	3.12	0.00	87.03	0.00	92.01	0.00	96.47	0.00	/workspace/coverage/default/4.usbdev_sec_cm.3487959009
77.08	0.02	90.22	0.00	75.59	0.05	95.05	0.00	3.12	0.00	87.11	0.09	92.01	0.00	96.47	0.00	/workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.810389166
77.09	0.01	90.22	0.00	75.67	0.08	95.05	0.00	3.12	0.00	87.11	0.00	92.01	0.00	96.47	0.00	/workspace/coverage/cover_reg_top/1.usbdev_tl_errors.2597537768
77.10	0.01	90.22	0.00	75.67	0.00	95.05	0.00	3.12	0.00	87.16	0.04	92.01	0.00	96.47	0.00	/workspace/coverage/default/3.usbdev_sec_cm.3892532252

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.2876308025
/workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2964995164
/workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1578327659
/workspace/coverage/cover_reg_top/0.usbdev_intr_test.4156700625
/workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.986255194
/workspace/coverage/cover_reg_top/0.usbdev_mem_walk.3828237250
/workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.2434926204
/workspace/coverage/cover_reg_top/0.usbdev_tl_errors.3746647859
/workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.282242963
/workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.1323630788
/workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.111437363
/workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.1145592050
/workspace/coverage/cover_reg_top/1.usbdev_csr_rw.4278603043
/workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.3624155688
/workspace/coverage/cover_reg_top/1.usbdev_mem_walk.1436288246
/workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.3966405824
/workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.536199398
/workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3093982620
/workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.4200036951
/workspace/coverage/cover_reg_top/10.usbdev_tl_errors.253086697
/workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.705087175
/workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.1046544982
/workspace/coverage/cover_reg_top/11.usbdev_csr_rw.1823438706
/workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.971031013
/workspace/coverage/cover_reg_top/11.usbdev_tl_errors.1653627379
/workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.836881063
/workspace/coverage/cover_reg_top/12.usbdev_csr_rw.513416847
/workspace/coverage/cover_reg_top/12.usbdev_intr_test.1101870522
/workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.251397750
/workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.973636373
/workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.3521061498
/workspace/coverage/cover_reg_top/13.usbdev_csr_rw.1721311625
/workspace/coverage/cover_reg_top/13.usbdev_intr_test.138652673
/workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.825266403
/workspace/coverage/cover_reg_top/13.usbdev_tl_errors.275970678
/workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2170765536
/workspace/coverage/cover_reg_top/14.usbdev_csr_rw.1842427816
/workspace/coverage/cover_reg_top/14.usbdev_intr_test.454483462
/workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.4071657950
/workspace/coverage/cover_reg_top/14.usbdev_tl_errors.13173972
/workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.518460481
/workspace/coverage/cover_reg_top/15.usbdev_csr_rw.2942095083
/workspace/coverage/cover_reg_top/15.usbdev_intr_test.4191184099
/workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.4074408849
/workspace/coverage/cover_reg_top/15.usbdev_tl_errors.228950002
/workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.1657474566
/workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.3954172274
/workspace/coverage/cover_reg_top/16.usbdev_csr_rw.1561214133
/workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.2071792365
/workspace/coverage/cover_reg_top/16.usbdev_tl_errors.2706869276
/workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.1636137768
/workspace/coverage/cover_reg_top/17.usbdev_csr_rw.2040875842
/workspace/coverage/cover_reg_top/17.usbdev_intr_test.2759324451
/workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.693061982
/workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.4211374723
/workspace/coverage/cover_reg_top/18.usbdev_csr_rw.2203180037
/workspace/coverage/cover_reg_top/18.usbdev_intr_test.55132232
/workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.2396325215
/workspace/coverage/cover_reg_top/18.usbdev_tl_errors.4231087087
/workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.1235478324
/workspace/coverage/cover_reg_top/19.usbdev_csr_rw.3346290508
/workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.140230330
/workspace/coverage/cover_reg_top/19.usbdev_tl_errors.1676976246
/workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.77722890
/workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.3130931597
/workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.853215568
/workspace/coverage/cover_reg_top/2.usbdev_csr_rw.700867551
/workspace/coverage/cover_reg_top/2.usbdev_intr_test.2855687804
/workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.1537077189
/workspace/coverage/cover_reg_top/2.usbdev_mem_walk.2716173029
/workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.1697779316
/workspace/coverage/cover_reg_top/2.usbdev_tl_errors.3243307184
/workspace/coverage/cover_reg_top/20.usbdev_intr_test.3007525859
/workspace/coverage/cover_reg_top/21.usbdev_intr_test.4170503718
/workspace/coverage/cover_reg_top/22.usbdev_intr_test.825611762
/workspace/coverage/cover_reg_top/24.usbdev_intr_test.3572121793
/workspace/coverage/cover_reg_top/26.usbdev_intr_test.959671407
/workspace/coverage/cover_reg_top/27.usbdev_intr_test.367742632
/workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.1560003894
/workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.512156733
/workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.796854749
/workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2983942295
/workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2802913797
/workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.988893233
/workspace/coverage/cover_reg_top/3.usbdev_mem_walk.140977916
/workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3075078517
/workspace/coverage/cover_reg_top/3.usbdev_tl_errors.3366714264
/workspace/coverage/cover_reg_top/30.usbdev_intr_test.1887310404
/workspace/coverage/cover_reg_top/35.usbdev_intr_test.37078877
/workspace/coverage/cover_reg_top/38.usbdev_intr_test.2333007162
/workspace/coverage/cover_reg_top/39.usbdev_intr_test.3926208002
/workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.555633591
/workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.2259064388
/workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.357848560
/workspace/coverage/cover_reg_top/4.usbdev_csr_rw.2933002772
/workspace/coverage/cover_reg_top/4.usbdev_intr_test.3650142101
/workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2319616904
/workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.599231141
/workspace/coverage/cover_reg_top/4.usbdev_tl_errors.3463909169
/workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.3207046946
/workspace/coverage/cover_reg_top/43.usbdev_intr_test.2489175812
/workspace/coverage/cover_reg_top/44.usbdev_intr_test.480273106
/workspace/coverage/cover_reg_top/47.usbdev_intr_test.3920832967
/workspace/coverage/cover_reg_top/48.usbdev_intr_test.957634440
/workspace/coverage/cover_reg_top/49.usbdev_intr_test.2716994392
/workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.902294396
/workspace/coverage/cover_reg_top/5.usbdev_csr_rw.1827396605
/workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.2991401417
/workspace/coverage/cover_reg_top/5.usbdev_tl_errors.1296972330
/workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1642436337
/workspace/coverage/cover_reg_top/6.usbdev_intr_test.3190014369
/workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3729914345
/workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1336307182
/workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.2112377236
/workspace/coverage/cover_reg_top/7.usbdev_csr_rw.3982110373
/workspace/coverage/cover_reg_top/7.usbdev_intr_test.73519925
/workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.394229007
/workspace/coverage/cover_reg_top/7.usbdev_tl_errors.3408913603
/workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1196342219
/workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.473281062
/workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2353135127
/workspace/coverage/cover_reg_top/8.usbdev_intr_test.1821295492
/workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3216202218
/workspace/coverage/cover_reg_top/8.usbdev_tl_errors.1930458411
/workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2264004377
/workspace/coverage/cover_reg_top/9.usbdev_csr_rw.4096178860
/workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.3995669808
/workspace/coverage/cover_reg_top/9.usbdev_tl_errors.2008648590

Total test records in report: 149

tests.html | tests1.html | tests2.html

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/4.usbdev_sec_cm.3487959009	Dec 31 12:23:23 PM PST 23	Dec 31 12:23:24 PM PST 23	151832286 ps
T2	/workspace/coverage/default/3.usbdev_sec_cm.3892532252	Dec 31 12:25:46 PM PST 23	Dec 31 12:25:55 PM PST 23	116389072 ps
T3	/workspace/coverage/default/0.usbdev_sec_cm.3203828703	Dec 31 12:23:06 PM PST 23	Dec 31 12:23:08 PM PST 23	239967141 ps
T4	/workspace/coverage/cover_reg_top/47.usbdev_intr_test.3920832967	Dec 31 12:50:25 PM PST 23	Dec 31 12:50:27 PM PST 23	29275424 ps
T5	/workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.2393896759	Dec 31 12:49:55 PM PST 23	Dec 31 12:50:00 PM PST 23	53923737 ps
T6	/workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.853215568	Dec 31 12:49:45 PM PST 23	Dec 31 12:49:47 PM PST 23	31204306 ps
T7	/workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.1323630788	Dec 31 12:49:51 PM PST 23	Dec 31 12:49:55 PM PST 23	70188693 ps
T8	/workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.1537077189	Dec 31 12:49:34 PM PST 23	Dec 31 12:49:38 PM PST 23	61897259 ps
T9	/workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.4211374723	Dec 31 12:50:10 PM PST 23	Dec 31 12:50:12 PM PST 23	54763278 ps
T10	/workspace/coverage/cover_reg_top/21.usbdev_intr_test.4170503718	Dec 31 12:50:13 PM PST 23	Dec 31 12:50:14 PM PST 23	21787523 ps
T18	/workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.2582515925	Dec 31 12:49:56 PM PST 23	Dec 31 12:50:01 PM PST 23	273840778 ps
T22	/workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.3851044141	Dec 31 12:50:00 PM PST 23	Dec 31 12:50:04 PM PST 23	194132978 ps
T11	/workspace/coverage/cover_reg_top/10.usbdev_tl_errors.253086697	Dec 31 12:49:54 PM PST 23	Dec 31 12:49:59 PM PST 23	71157731 ps
T12	/workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2964995164	Dec 31 12:49:49 PM PST 23	Dec 31 12:49:52 PM PST 23	60622007 ps
T13	/workspace/coverage/cover_reg_top/0.usbdev_mem_walk.3828237250	Dec 31 12:49:23 PM PST 23	Dec 31 12:49:28 PM PST 23	363532978 ps
T14	/workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.902294396	Dec 31 12:49:52 PM PST 23	Dec 31 12:49:55 PM PST 23	51077037 ps
T23	/workspace/coverage/cover_reg_top/48.usbdev_intr_test.957634440	Dec 31 12:50:09 PM PST 23	Dec 31 12:50:11 PM PST 23	25994115 ps
T15	/workspace/coverage/cover_reg_top/17.usbdev_tl_errors.1410588467	Dec 31 12:49:56 PM PST 23	Dec 31 12:50:01 PM PST 23	85825362 ps
T16	/workspace/coverage/cover_reg_top/3.usbdev_tl_errors.3366714264	Dec 31 12:49:41 PM PST 23	Dec 31 12:49:44 PM PST 23	90317884 ps
T26	/workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.898820348	Dec 31 12:50:08 PM PST 23	Dec 31 12:50:13 PM PST 23	257701669 ps
T41	/workspace/coverage/cover_reg_top/4.usbdev_csr_rw.2933002772	Dec 31 12:50:25 PM PST 23	Dec 31 12:50:28 PM PST 23	50110217 ps
T24	/workspace/coverage/cover_reg_top/28.usbdev_intr_test.1958240488	Dec 31 12:50:05 PM PST 23	Dec 31 12:50:07 PM PST 23	38562483 ps
T27	/workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.971031013	Dec 31 12:50:03 PM PST 23	Dec 31 12:50:05 PM PST 23	59610634 ps
T25	/workspace/coverage/cover_reg_top/33.usbdev_intr_test.3105948824	Dec 31 12:50:18 PM PST 23	Dec 31 12:50:19 PM PST 23	26541896 ps
T17	/workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.3954172274	Dec 31 12:50:11 PM PST 23	Dec 31 12:50:12 PM PST 23	37744657 ps
T28	/workspace/coverage/cover_reg_top/11.usbdev_tl_errors.1653627379	Dec 31 12:49:45 PM PST 23	Dec 31 12:49:48 PM PST 23	45517329 ps
T33	/workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.512156733	Dec 31 12:49:37 PM PST 23	Dec 31 12:49:47 PM PST 23	442541989 ps
T34	/workspace/coverage/cover_reg_top/1.usbdev_intr_test.4217189164	Dec 31 12:49:43 PM PST 23	Dec 31 12:49:45 PM PST 23	23119174 ps
T35	/workspace/coverage/cover_reg_top/4.usbdev_intr_test.3650142101	Dec 31 12:50:00 PM PST 23	Dec 31 12:50:02 PM PST 23	25662600 ps
T36	/workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.4074408849	Dec 31 12:50:07 PM PST 23	Dec 31 12:50:09 PM PST 23	203319213 ps
T40	/workspace/coverage/cover_reg_top/5.usbdev_csr_rw.1827396605	Dec 31 12:49:27 PM PST 23	Dec 31 12:49:32 PM PST 23	64447218 ps
T42	/workspace/coverage/cover_reg_top/19.usbdev_csr_rw.3346290508	Dec 31 12:49:53 PM PST 23	Dec 31 12:49:56 PM PST 23	58425484 ps
T43	/workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.3177621950	Dec 31 12:49:39 PM PST 23	Dec 31 12:49:41 PM PST 23	56585606 ps
T44	/workspace/coverage/cover_reg_top/12.usbdev_csr_rw.513416847	Dec 31 12:49:47 PM PST 23	Dec 31 12:49:49 PM PST 23	44236162 ps
T62	/workspace/coverage/cover_reg_top/13.usbdev_intr_test.138652673	Dec 31 12:49:49 PM PST 23	Dec 31 12:49:50 PM PST 23	24836423 ps
T63	/workspace/coverage/cover_reg_top/1.usbdev_mem_walk.1436288246	Dec 31 12:49:39 PM PST 23	Dec 31 12:49:44 PM PST 23	364419894 ps
T54	/workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3729914345	Dec 31 12:49:50 PM PST 23	Dec 31 12:49:52 PM PST 23	39864928 ps
T55	/workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.2071792365	Dec 31 12:50:10 PM PST 23	Dec 31 12:50:12 PM PST 23	106268125 ps
T19	/workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2098105954	Dec 31 12:49:35 PM PST 23	Dec 31 12:49:37 PM PST 23	144078634 ps
T29	/workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.973636373	Dec 31 12:49:35 PM PST 23	Dec 31 12:49:40 PM PST 23	218873085 ps
T37	/workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.3966405824	Dec 31 12:49:46 PM PST 23	Dec 31 12:49:49 PM PST 23	130680854 ps
T59	/workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.518460481	Dec 31 12:49:57 PM PST 23	Dec 31 12:50:00 PM PST 23	45055971 ps
T82	/workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3093982620	Dec 31 12:50:03 PM PST 23	Dec 31 12:50:05 PM PST 23	41729349 ps
T45	/workspace/coverage/cover_reg_top/15.usbdev_csr_rw.2942095083	Dec 31 12:49:54 PM PST 23	Dec 31 12:49:57 PM PST 23	79179562 ps
T68	/workspace/coverage/cover_reg_top/16.usbdev_intr_test.2829215162	Dec 31 12:50:00 PM PST 23	Dec 31 12:50:02 PM PST 23	30988320 ps
T61	/workspace/coverage/cover_reg_top/39.usbdev_intr_test.3926208002	Dec 31 12:50:05 PM PST 23	Dec 31 12:50:07 PM PST 23	26737312 ps
T20	/workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.810389166	Dec 31 12:49:35 PM PST 23	Dec 31 12:49:37 PM PST 23	32865272 ps
T83	/workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.536199398	Dec 31 12:50:16 PM PST 23	Dec 31 12:50:17 PM PST 23	28349233 ps
T84	/workspace/coverage/cover_reg_top/1.usbdev_csr_rw.4278603043	Dec 31 12:49:39 PM PST 23	Dec 31 12:49:42 PM PST 23	40430808 ps
T46	/workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1642436337	Dec 31 12:50:03 PM PST 23	Dec 31 12:50:05 PM PST 23	40632554 ps
T47	/workspace/coverage/cover_reg_top/16.usbdev_csr_rw.1561214133	Dec 31 12:50:05 PM PST 23	Dec 31 12:50:07 PM PST 23	91744944 ps
T85	/workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.4200036951	Dec 31 12:49:56 PM PST 23	Dec 31 12:49:59 PM PST 23	169082258 ps
T38	/workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.282242963	Dec 31 12:49:32 PM PST 23	Dec 31 12:49:36 PM PST 23	300949892 ps
T30	/workspace/coverage/cover_reg_top/9.usbdev_tl_errors.2008648590	Dec 31 12:50:00 PM PST 23	Dec 31 12:50:03 PM PST 23	145788743 ps
T39	/workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.1636137768	Dec 31 12:50:03 PM PST 23	Dec 31 12:50:07 PM PST 23	136430103 ps
T86	/workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.2396325215	Dec 31 12:50:25 PM PST 23	Dec 31 12:50:28 PM PST 23	41699130 ps
T73	/workspace/coverage/cover_reg_top/7.usbdev_intr_test.73519925	Dec 31 12:49:35 PM PST 23	Dec 31 12:49:37 PM PST 23	26499915 ps
T81	/workspace/coverage/cover_reg_top/38.usbdev_intr_test.2333007162	Dec 31 12:50:16 PM PST 23	Dec 31 12:50:17 PM PST 23	22265449 ps
T31	/workspace/coverage/cover_reg_top/0.usbdev_tl_errors.3746647859	Dec 31 12:49:26 PM PST 23	Dec 31 12:49:29 PM PST 23	66177253 ps
T48	/workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.3624155688	Dec 31 12:49:54 PM PST 23	Dec 31 12:49:58 PM PST 23	69482332 ps
T87	/workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.555633591	Dec 31 12:49:30 PM PST 23	Dec 31 12:49:33 PM PST 23	69190394 ps
T64	/workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.3207046946	Dec 31 12:49:36 PM PST 23	Dec 31 12:49:40 PM PST 23	120617540 ps
T69	/workspace/coverage/cover_reg_top/9.usbdev_intr_test.2168333583	Dec 31 12:49:52 PM PST 23	Dec 31 12:49:55 PM PST 23	25870012 ps
T88	/workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.4071657950	Dec 31 12:49:45 PM PST 23	Dec 31 12:49:47 PM PST 23	41787123 ps
T89	/workspace/coverage/cover_reg_top/11.usbdev_csr_rw.1823438706	Dec 31 12:50:09 PM PST 23	Dec 31 12:50:16 PM PST 23	57167947 ps
T32	/workspace/coverage/cover_reg_top/5.usbdev_tl_errors.1296972330	Dec 31 12:49:28 PM PST 23	Dec 31 12:49:31 PM PST 23	109507439 ps
T56	/workspace/coverage/cover_reg_top/13.usbdev_tl_errors.275970678	Dec 31 12:49:51 PM PST 23	Dec 31 12:49:55 PM PST 23	243005110 ps
T60	/workspace/coverage/cover_reg_top/13.usbdev_csr_rw.1721311625	Dec 31 12:50:20 PM PST 23	Dec 31 12:50:22 PM PST 23	43523376 ps
T90	/workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2170765536	Dec 31 12:49:45 PM PST 23	Dec 31 12:49:48 PM PST 23	32322244 ps
T91	/workspace/coverage/cover_reg_top/7.usbdev_csr_rw.3982110373	Dec 31 12:49:46 PM PST 23	Dec 31 12:49:48 PM PST 23	49737819 ps
T92	/workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.394229007	Dec 31 12:49:55 PM PST 23	Dec 31 12:49:59 PM PST 23	126555953 ps
T50	/workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.77722890	Dec 31 12:50:00 PM PST 23	Dec 31 12:50:03 PM PST 23	66993681 ps
T77	/workspace/coverage/cover_reg_top/17.usbdev_intr_test.2759324451	Dec 31 12:50:17 PM PST 23	Dec 31 12:50:19 PM PST 23	47686953 ps
T93	/workspace/coverage/cover_reg_top/3.usbdev_mem_walk.140977916	Dec 31 12:49:25 PM PST 23	Dec 31 12:49:35 PM PST 23	155220658 ps
T53	/workspace/coverage/cover_reg_top/2.usbdev_csr_rw.700867551	Dec 31 12:49:34 PM PST 23	Dec 31 12:49:37 PM PST 23	61917528 ps
T94	/workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1196342219	Dec 31 12:49:41 PM PST 23	Dec 31 12:49:50 PM PST 23	262871271 ps
T57	/workspace/coverage/cover_reg_top/8.usbdev_tl_errors.1930458411	Dec 31 12:50:13 PM PST 23	Dec 31 12:50:16 PM PST 23	84512371 ps
T95	/workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.693061982	Dec 31 12:50:16 PM PST 23	Dec 31 12:50:18 PM PST 23	76460977 ps
T58	/workspace/coverage/cover_reg_top/15.usbdev_tl_errors.228950002	Dec 31 12:49:58 PM PST 23	Dec 31 12:50:02 PM PST 23	243669694 ps
T96	/workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.251397750	Dec 31 12:49:51 PM PST 23	Dec 31 12:49:54 PM PST 23	147180533 ps
T51	/workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.2259064388	Dec 31 12:49:42 PM PST 23	Dec 31 12:49:51 PM PST 23	374743399 ps
T74	/workspace/coverage/cover_reg_top/49.usbdev_intr_test.2716994392	Dec 31 12:50:34 PM PST 23	Dec 31 12:50:48 PM PST 23	22701167 ps
T52	/workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.988893233	Dec 31 12:49:29 PM PST 23	Dec 31 12:49:32 PM PST 23	64358828 ps
T76	/workspace/coverage/cover_reg_top/8.usbdev_intr_test.1821295492	Dec 31 12:49:38 PM PST 23	Dec 31 12:49:40 PM PST 23	29182305 ps
T70	/workspace/coverage/cover_reg_top/44.usbdev_intr_test.480273106	Dec 31 12:49:58 PM PST 23	Dec 31 12:50:00 PM PST 23	28404943 ps
T71	/workspace/coverage/cover_reg_top/42.usbdev_intr_test.3718946785	Dec 31 12:50:20 PM PST 23	Dec 31 12:50:22 PM PST 23	27488504 ps
T78	/workspace/coverage/cover_reg_top/24.usbdev_intr_test.3572121793	Dec 31 12:50:08 PM PST 23	Dec 31 12:50:10 PM PST 23	30749642 ps
T97	/workspace/coverage/cover_reg_top/2.usbdev_tl_errors.3243307184	Dec 31 12:49:50 PM PST 23	Dec 31 12:49:55 PM PST 23	340864994 ps
T21	/workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.111437363	Dec 31 12:49:53 PM PST 23	Dec 31 12:49:55 PM PST 23	29854858 ps
T98	/workspace/coverage/cover_reg_top/14.usbdev_intr_test.454483462	Dec 31 12:49:49 PM PST 23	Dec 31 12:49:51 PM PST 23	23569013 ps
T99	/workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.705087175	Dec 31 12:49:52 PM PST 23	Dec 31 12:49:59 PM PST 23	273637275 ps
T100	/workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.1697779316	Dec 31 12:49:35 PM PST 23	Dec 31 12:49:37 PM PST 23	71857849 ps
T101	/workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.357848560	Dec 31 12:49:56 PM PST 23	Dec 31 12:50:00 PM PST 23	68953153 ps
T102	/workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2802913797	Dec 31 12:49:44 PM PST 23	Dec 31 12:49:46 PM PST 23	79883344 ps
T80	/workspace/coverage/cover_reg_top/18.usbdev_intr_test.55132232	Dec 31 12:50:26 PM PST 23	Dec 31 12:50:28 PM PST 23	48102393 ps
T103	/workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.2991401417	Dec 31 12:49:52 PM PST 23	Dec 31 12:49:56 PM PST 23	87014457 ps
T104	/workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2264004377	Dec 31 12:49:53 PM PST 23	Dec 31 12:49:57 PM PST 23	60335660 ps
T105	/workspace/coverage/cover_reg_top/1.usbdev_tl_errors.2597537768	Dec 31 12:49:53 PM PST 23	Dec 31 12:49:58 PM PST 23	359583351 ps
T106	/workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.3521061498	Dec 31 12:50:21 PM PST 23	Dec 31 12:50:24 PM PST 23	37986299 ps
T107	/workspace/coverage/cover_reg_top/17.usbdev_csr_rw.2040875842	Dec 31 12:50:07 PM PST 23	Dec 31 12:50:09 PM PST 23	34846019 ps
T79	/workspace/coverage/cover_reg_top/11.usbdev_intr_test.1623426135	Dec 31 12:49:57 PM PST 23	Dec 31 12:50:00 PM PST 23	28230253 ps
T108	/workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.986255194	Dec 31 12:49:47 PM PST 23	Dec 31 12:49:49 PM PST 23	85165999 ps
T109	/workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.1145592050	Dec 31 12:49:32 PM PST 23	Dec 31 12:49:34 PM PST 23	55160454 ps
T110	/workspace/coverage/cover_reg_top/18.usbdev_tl_errors.4231087087	Dec 31 12:50:06 PM PST 23	Dec 31 12:50:09 PM PST 23	90617453 ps
T111	/workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2353135127	Dec 31 12:49:53 PM PST 23	Dec 31 12:49:56 PM PST 23	55355177 ps
T65	/workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.795209662	Dec 31 12:49:49 PM PST 23	Dec 31 12:49:52 PM PST 23	324508951 ps
T112	/workspace/coverage/cover_reg_top/2.usbdev_mem_walk.2716173029	Dec 31 12:49:49 PM PST 23	Dec 31 12:49:58 PM PST 23	472352151 ps
T113	/workspace/coverage/cover_reg_top/35.usbdev_intr_test.37078877	Dec 31 12:49:51 PM PST 23	Dec 31 12:49:53 PM PST 23	29938792 ps
T114	/workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.3995669808	Dec 31 12:49:52 PM PST 23	Dec 31 12:49:55 PM PST 23	42119191 ps
T72	/workspace/coverage/cover_reg_top/43.usbdev_intr_test.2489175812	Dec 31 12:50:13 PM PST 23	Dec 31 12:50:15 PM PST 23	27618401 ps
T115	/workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.1046544982	Dec 31 12:49:50 PM PST 23	Dec 31 12:49:53 PM PST 23	37759278 ps
T67	/workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.1840079369	Dec 31 12:49:51 PM PST 23	Dec 31 12:49:57 PM PST 23	312959291 ps
T116	/workspace/coverage/cover_reg_top/30.usbdev_intr_test.1887310404	Dec 31 12:50:21 PM PST 23	Dec 31 12:50:23 PM PST 23	45748107 ps
T117	/workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.473281062	Dec 31 12:49:54 PM PST 23	Dec 31 12:49:58 PM PST 23	23746047 ps
T118	/workspace/coverage/cover_reg_top/26.usbdev_intr_test.959671407	Dec 31 12:50:15 PM PST 23	Dec 31 12:50:16 PM PST 23	23035074 ps
T119	/workspace/coverage/cover_reg_top/4.usbdev_tl_errors.3463909169	Dec 31 12:49:41 PM PST 23	Dec 31 12:49:44 PM PST 23	55856288 ps
T120	/workspace/coverage/cover_reg_top/12.usbdev_intr_test.1101870522	Dec 31 12:50:15 PM PST 23	Dec 31 12:50:17 PM PST 23	121725150 ps
T121	/workspace/coverage/cover_reg_top/19.usbdev_tl_errors.1676976246	Dec 31 12:50:27 PM PST 23	Dec 31 12:50:32 PM PST 23	72598120 ps
T75	/workspace/coverage/cover_reg_top/20.usbdev_intr_test.3007525859	Dec 31 12:49:52 PM PST 23	Dec 31 12:49:55 PM PST 23	24331083 ps
T122	/workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.2876308025	Dec 31 12:49:45 PM PST 23	Dec 31 12:49:49 PM PST 23	116168369 ps
T123	/workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1578327659	Dec 31 12:49:26 PM PST 23	Dec 31 12:49:28 PM PST 23	60488568 ps
T124	/workspace/coverage/cover_reg_top/18.usbdev_csr_rw.2203180037	Dec 31 12:50:20 PM PST 23	Dec 31 12:50:23 PM PST 23	33725674 ps
T125	/workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.825266403	Dec 31 12:50:20 PM PST 23	Dec 31 12:50:24 PM PST 23	179138666 ps
T126	/workspace/coverage/cover_reg_top/22.usbdev_intr_test.825611762	Dec 31 12:50:15 PM PST 23	Dec 31 12:50:17 PM PST 23	100734936 ps
T127	/workspace/coverage/cover_reg_top/14.usbdev_csr_rw.1842427816	Dec 31 12:49:49 PM PST 23	Dec 31 12:49:51 PM PST 23	54095986 ps
T128	/workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3216202218	Dec 31 12:49:31 PM PST 23	Dec 31 12:49:33 PM PST 23	38754192 ps
T129	/workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.796854749	Dec 31 12:49:47 PM PST 23	Dec 31 12:49:49 PM PST 23	29154886 ps
T66	/workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.1657474566	Dec 31 12:49:48 PM PST 23	Dec 31 12:49:51 PM PST 23	123155062 ps
T130	/workspace/coverage/cover_reg_top/9.usbdev_csr_rw.4096178860	Dec 31 12:49:48 PM PST 23	Dec 31 12:49:50 PM PST 23	108102031 ps
T131	/workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2983942295	Dec 31 12:49:56 PM PST 23	Dec 31 12:50:00 PM PST 23	77251460 ps
T132	/workspace/coverage/cover_reg_top/16.usbdev_tl_errors.2706869276	Dec 31 12:50:23 PM PST 23	Dec 31 12:50:27 PM PST 23	170495247 ps
T49	/workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.1560003894	Dec 31 12:49:28 PM PST 23	Dec 31 12:49:37 PM PST 23	346374784 ps
T133	/workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.2112377236	Dec 31 12:49:49 PM PST 23	Dec 31 12:49:52 PM PST 23	50951570 ps
T134	/workspace/coverage/cover_reg_top/15.usbdev_intr_test.4191184099	Dec 31 12:50:20 PM PST 23	Dec 31 12:50:22 PM PST 23	24072548 ps
T135	/workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.3130931597	Dec 31 12:49:51 PM PST 23	Dec 31 12:50:02 PM PST 23	388042949 ps
T136	/workspace/coverage/cover_reg_top/27.usbdev_intr_test.367742632	Dec 31 12:50:19 PM PST 23	Dec 31 12:50:21 PM PST 23	42234954 ps
T137	/workspace/coverage/cover_reg_top/14.usbdev_tl_errors.13173972	Dec 31 12:49:57 PM PST 23	Dec 31 12:50:02 PM PST 23	113436915 ps
T138	/workspace/coverage/cover_reg_top/0.usbdev_intr_test.4156700625	Dec 31 12:49:50 PM PST 23	Dec 31 12:49:52 PM PST 23	48042023 ps
T139	/workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.836881063	Dec 31 12:49:39 PM PST 23	Dec 31 12:49:42 PM PST 23	36300251 ps
T140	/workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.2434926204	Dec 31 12:49:36 PM PST 23	Dec 31 12:49:38 PM PST 23	73420612 ps
T141	/workspace/coverage/cover_reg_top/6.usbdev_intr_test.3190014369	Dec 31 12:49:50 PM PST 23	Dec 31 12:49:52 PM PST 23	32499177 ps
T142	/workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2319616904	Dec 31 12:49:55 PM PST 23	Dec 31 12:49:59 PM PST 23	139488215 ps
T143	/workspace/coverage/cover_reg_top/2.usbdev_intr_test.2855687804	Dec 31 12:49:35 PM PST 23	Dec 31 12:49:37 PM PST 23	29562190 ps
T144	/workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3075078517	Dec 31 12:49:44 PM PST 23	Dec 31 12:49:55 PM PST 23	126791330 ps
T145	/workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.599231141	Dec 31 12:49:55 PM PST 23	Dec 31 12:49:59 PM PST 23	138649940 ps
T146	/workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.140230330	Dec 31 12:50:10 PM PST 23	Dec 31 12:50:12 PM PST 23	37702700 ps
T147	/workspace/coverage/cover_reg_top/7.usbdev_tl_errors.3408913603	Dec 31 12:50:00 PM PST 23	Dec 31 12:50:03 PM PST 23	144968926 ps
T148	/workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1336307182	Dec 31 12:50:03 PM PST 23	Dec 31 12:50:06 PM PST 23	163484183 ps
T149	/workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.1235478324	Dec 31 12:50:01 PM PST 23	Dec 31 12:50:03 PM PST 23	28301414 ps

Test location	/workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.2393896759
Short name	T5
Test name
Test status
Simulation time	53923737 ps
CPU time	2.13 seconds
Started	Dec 31 12:49:55 PM PST 23
Finished	Dec 31 12:50:00 PM PST 23
Peak memory	217968 kb
Host	smart-5bd95f81-b30b-499e-83a5-5de39d7e9557
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393896759 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_mem_rw_with_rand_reset.2393896759
Directory	/workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/default/0.usbdev_sec_cm.3203828703
Short name	T3
Test name
Test status
Simulation time	239967141 ps
CPU time	1.01 seconds
Started	Dec 31 12:23:06 PM PST 23
Finished	Dec 31 12:23:08 PM PST 23
Peak memory	216900 kb
Host	smart-140a352c-f71e-4e21-b862-397979bbf2b2
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3203828703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.3203828703
Directory	/workspace/0.usbdev_sec_cm/latest

Test location	/workspace/coverage/cover_reg_top/33.usbdev_intr_test.3105948824
Short name	T25
Test name
Test status
Simulation time	26541896 ps
CPU time	0.64 seconds
Started	Dec 31 12:50:18 PM PST 23
Finished	Dec 31 12:50:19 PM PST 23
Peak memory	200708 kb
Host	smart-7fa4db36-1888-4fba-bbda-053280423a92
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3105948824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.3105948824
Directory	/workspace/33.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_tl_errors.1410588467
Short name	T15
Test name
Test status
Simulation time	85825362 ps
CPU time	2.35 seconds
Started	Dec 31 12:49:56 PM PST 23
Finished	Dec 31 12:50:01 PM PST 23
Peak memory	201708 kb
Host	smart-53530b6d-8148-4358-beaf-9f72c902044b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1410588467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.1410588467
Directory	/workspace/17.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/28.usbdev_intr_test.1958240488
Short name	T24
Test name
Test status
Simulation time	38562483 ps
CPU time	0.66 seconds
Started	Dec 31 12:50:05 PM PST 23
Finished	Dec 31 12:50:07 PM PST 23
Peak memory	200736 kb
Host	smart-1d187f46-11da-40b0-8755-ea5a670f39be
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1958240488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.1958240488
Directory	/workspace/28.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2098105954
Short name	T19
Test name
Test status
Simulation time	144078634 ps
CPU time	0.86 seconds
Started	Dec 31 12:49:35 PM PST 23
Finished	Dec 31 12:49:37 PM PST 23
Peak memory	201304 kb
Host	smart-ec263a30-fdd6-43f4-b3ce-ec975297ea7b
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098105954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.2098105954
Directory	/workspace/4.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.898820348
Short name	T26
Test name
Test status
Simulation time	257701669 ps
CPU time	4.43 seconds
Started	Dec 31 12:50:08 PM PST 23
Finished	Dec 31 12:50:13 PM PST 23
Peak memory	201760 kb
Host	smart-a5066c96-8ffd-4a5c-a4f3-e462d57ea88c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=898820348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.898820348
Directory	/workspace/11.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_intr_test.2168333583
Short name	T69
Test name
Test status
Simulation time	25870012 ps
CPU time	0.61 seconds
Started	Dec 31 12:49:52 PM PST 23
Finished	Dec 31 12:49:55 PM PST 23
Peak memory	200564 kb
Host	smart-4041e6fd-773c-40d8-87e2-8f3bd37cc6b7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2168333583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.2168333583
Directory	/workspace/9.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_intr_test.1623426135
Short name	T79
Test name
Test status
Simulation time	28230253 ps
CPU time	0.64 seconds
Started	Dec 31 12:49:57 PM PST 23
Finished	Dec 31 12:50:00 PM PST 23
Peak memory	200784 kb
Host	smart-6db02507-d1c7-4dcd-982c-7c1116ed0c53
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1623426135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.1623426135
Directory	/workspace/11.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.2582515925
Short name	T18
Test name
Test status
Simulation time	273840778 ps
CPU time	2.47 seconds
Started	Dec 31 12:49:56 PM PST 23
Finished	Dec 31 12:50:01 PM PST 23
Peak memory	201616 kb
Host	smart-93deae0a-20a9-446c-8712-bbfc67ea4506
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2582515925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.2582515925
Directory	/workspace/8.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_intr_test.2829215162
Short name	T68
Test name
Test status
Simulation time	30988320 ps
CPU time	0.65 seconds
Started	Dec 31 12:50:00 PM PST 23
Finished	Dec 31 12:50:02 PM PST 23
Peak memory	200720 kb
Host	smart-5cb4e503-711f-4063-a8c7-4a7fe8b7bc44
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2829215162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.2829215162
Directory	/workspace/16.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.3177621950
Short name	T43
Test name
Test status
Simulation time	56585606 ps
CPU time	1.31 seconds
Started	Dec 31 12:49:39 PM PST 23
Finished	Dec 31 12:49:41 PM PST 23
Peak memory	201628 kb
Host	smart-321ed534-30eb-438b-824c-1e453ead5f68
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177621950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_c sr_outstanding.3177621950
Directory	/workspace/1.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_intr_test.4217189164
Short name	T34
Test name
Test status
Simulation time	23119174 ps
CPU time	0.65 seconds
Started	Dec 31 12:49:43 PM PST 23
Finished	Dec 31 12:49:45 PM PST 23
Peak memory	200632 kb
Host	smart-49447723-f457-4b5d-a955-5cd55beb496f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4217189164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.4217189164
Directory	/workspace/1.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.795209662
Short name	T65
Test name
Test status
Simulation time	324508951 ps
CPU time	2.84 seconds
Started	Dec 31 12:49:49 PM PST 23
Finished	Dec 31 12:49:52 PM PST 23
Peak memory	201684 kb
Host	smart-b30add9e-ff26-4490-8a23-9df5642f1a06
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=795209662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.795209662
Directory	/workspace/2.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.3851044141
Short name	T22
Test name
Test status
Simulation time	194132978 ps
CPU time	2.47 seconds
Started	Dec 31 12:50:00 PM PST 23
Finished	Dec 31 12:50:04 PM PST 23
Peak memory	201968 kb
Host	smart-6116e0d4-ceab-4f5a-9e86-e1455950d133
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3851044141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.3851044141
Directory	/workspace/13.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/42.usbdev_intr_test.3718946785
Short name	T71
Test name
Test status
Simulation time	27488504 ps
CPU time	0.66 seconds
Started	Dec 31 12:50:20 PM PST 23
Finished	Dec 31 12:50:22 PM PST 23
Peak memory	200824 kb
Host	smart-0c9f3fea-7f4b-414d-ac60-b80065aa8d3d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3718946785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.3718946785
Directory	/workspace/42.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.1840079369
Short name	T67
Test name
Test status
Simulation time	312959291 ps
CPU time	4.05 seconds
Started	Dec 31 12:49:51 PM PST 23
Finished	Dec 31 12:49:57 PM PST 23
Peak memory	201732 kb
Host	smart-c699a712-af25-4658-aca7-6046ce823fc0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1840079369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.1840079369
Directory	/workspace/9.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/default/4.usbdev_sec_cm.3487959009
Short name	T1
Test name
Test status
Simulation time	151832286 ps
CPU time	0.92 seconds
Started	Dec 31 12:23:23 PM PST 23
Finished	Dec 31 12:23:24 PM PST 23
Peak memory	221072 kb
Host	smart-f8fa144b-6711-4172-8611-b7d4ef574c38
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3487959009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.3487959009
Directory	/workspace/4.usbdev_sec_cm/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.810389166
Short name	T20
Test name
Test status
Simulation time	32865272 ps
CPU time	0.74 seconds
Started	Dec 31 12:49:35 PM PST 23
Finished	Dec 31 12:49:37 PM PST 23
Peak memory	201432 kb
Host	smart-771520e5-a4ad-4b37-ad11-13268b0f0d7a
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810389166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.810389166
Directory	/workspace/0.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_tl_errors.2597537768
Short name	T105
Test name
Test status
Simulation time	359583351 ps
CPU time	3.67 seconds
Started	Dec 31 12:49:53 PM PST 23
Finished	Dec 31 12:49:58 PM PST 23
Peak memory	201616 kb
Host	smart-f705dc4b-6d40-47a2-9f9b-73848e9dfee3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2597537768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.2597537768
Directory	/workspace/1.usbdev_tl_errors/latest

Test location	/workspace/coverage/default/3.usbdev_sec_cm.3892532252
Short name	T2
Test name
Test status
Simulation time	116389072 ps
CPU time	0.89 seconds
Started	Dec 31 12:25:46 PM PST 23
Finished	Dec 31 12:25:55 PM PST 23
Peak memory	221116 kb
Host	smart-f563ba36-5687-440a-9f9e-0489fbb5728e
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3892532252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.3892532252
Directory	/workspace/3.usbdev_sec_cm/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.2876308025
Short name	T122
Test name
Test status
Simulation time	116168369 ps
CPU time	3.11 seconds
Started	Dec 31 12:49:45 PM PST 23
Finished	Dec 31 12:49:49 PM PST 23
Peak memory	201612 kb
Host	smart-17f9d9c6-9340-498e-b4c0-e310dbc85d3a
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876308025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.2876308025
Directory	/workspace/0.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2964995164
Short name	T12
Test name
Test status
Simulation time	60622007 ps
CPU time	1.51 seconds
Started	Dec 31 12:49:49 PM PST 23
Finished	Dec 31 12:49:52 PM PST 23
Peak memory	209956 kb
Host	smart-2d3d8aad-d00c-42c6-93be-45c60f89faf9
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964995164 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_mem_rw_with_rand_reset.2964995164
Directory	/workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1578327659
Short name	T123
Test name
Test status
Simulation time	60488568 ps
CPU time	0.9 seconds
Started	Dec 31 12:49:26 PM PST 23
Finished	Dec 31 12:49:28 PM PST 23
Peak memory	201652 kb
Host	smart-8ab91fd3-cf96-4611-8b05-1e66da091604
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578327659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.1578327659
Directory	/workspace/0.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_intr_test.4156700625
Short name	T138
Test name
Test status
Simulation time	48042023 ps
CPU time	0.65 seconds
Started	Dec 31 12:49:50 PM PST 23
Finished	Dec 31 12:49:52 PM PST 23
Peak memory	200604 kb
Host	smart-5a98e7af-6588-45e0-baae-99bd54af02e9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4156700625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.4156700625
Directory	/workspace/0.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.986255194
Short name	T108
Test name
Test status
Simulation time	85165999 ps
CPU time	1.32 seconds
Started	Dec 31 12:49:47 PM PST 23
Finished	Dec 31 12:49:49 PM PST 23
Peak memory	201580 kb
Host	smart-dd5081d6-b630-49e5-9b64-01bd3014f8f1
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=986255194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.986255194
Directory	/workspace/0.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_mem_walk.3828237250
Short name	T13
Test name
Test status
Simulation time	363532978 ps
CPU time	2.51 seconds
Started	Dec 31 12:49:23 PM PST 23
Finished	Dec 31 12:49:28 PM PST 23
Peak memory	201536 kb
Host	smart-72736446-c9db-4de1-a012-3719d9e18aac
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3828237250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.3828237250
Directory	/workspace/0.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.2434926204
Short name	T140
Test name
Test status
Simulation time	73420612 ps
CPU time	0.95 seconds
Started	Dec 31 12:49:36 PM PST 23
Finished	Dec 31 12:49:38 PM PST 23
Peak memory	201592 kb
Host	smart-cff934df-47f6-45d6-9c6d-b7b7864ca460
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434926204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_c sr_outstanding.2434926204
Directory	/workspace/0.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_tl_errors.3746647859
Short name	T31
Test name
Test status
Simulation time	66177253 ps
CPU time	1.75 seconds
Started	Dec 31 12:49:26 PM PST 23
Finished	Dec 31 12:49:29 PM PST 23
Peak memory	201728 kb
Host	smart-4899d1ad-a821-4fbd-b92b-148941fa77d0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3746647859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.3746647859
Directory	/workspace/0.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.282242963
Short name	T38
Test name
Test status
Simulation time	300949892 ps
CPU time	2.66 seconds
Started	Dec 31 12:49:32 PM PST 23
Finished	Dec 31 12:49:36 PM PST 23
Peak memory	201648 kb
Host	smart-9d51cf53-bea8-4c44-8725-8bba9eed1fe5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=282242963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.282242963
Directory	/workspace/0.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.1323630788
Short name	T7
Test name
Test status
Simulation time	70188693 ps
CPU time	1.9 seconds
Started	Dec 31 12:49:51 PM PST 23
Finished	Dec 31 12:49:55 PM PST 23
Peak memory	201676 kb
Host	smart-db77f3b3-da6b-4099-957a-1c827a334a59
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323630788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.1323630788
Directory	/workspace/1.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.111437363
Short name	T21
Test name
Test status
Simulation time	29854858 ps
CPU time	0.72 seconds
Started	Dec 31 12:49:53 PM PST 23
Finished	Dec 31 12:49:55 PM PST 23
Peak memory	201416 kb
Host	smart-a8ac2261-1022-4407-9cd4-85fd22ce6487
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111437363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.111437363
Directory	/workspace/1.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.1145592050
Short name	T109
Test name
Test status
Simulation time	55160454 ps
CPU time	1.28 seconds
Started	Dec 31 12:49:32 PM PST 23
Finished	Dec 31 12:49:34 PM PST 23
Peak memory	209916 kb
Host	smart-6bfec357-d89f-4bf7-a2a9-5797a48c8e61
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145592050 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_mem_rw_with_rand_reset.1145592050
Directory	/workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_rw.4278603043
Short name	T84
Test name
Test status
Simulation time	40430808 ps
CPU time	0.81 seconds
Started	Dec 31 12:49:39 PM PST 23
Finished	Dec 31 12:49:42 PM PST 23
Peak memory	201348 kb
Host	smart-7d02498e-5f15-474e-bc4b-ee21ebb0e527
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278603043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.4278603043
Directory	/workspace/1.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.3624155688
Short name	T48
Test name
Test status
Simulation time	69482332 ps
CPU time	2.1 seconds
Started	Dec 31 12:49:54 PM PST 23
Finished	Dec 31 12:49:58 PM PST 23
Peak memory	201592 kb
Host	smart-9f769f6e-f185-40fc-9c26-d08c17f64e44
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3624155688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.3624155688
Directory	/workspace/1.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_mem_walk.1436288246
Short name	T63
Test name
Test status
Simulation time	364419894 ps
CPU time	2.6 seconds
Started	Dec 31 12:49:39 PM PST 23
Finished	Dec 31 12:49:44 PM PST 23
Peak memory	201696 kb
Host	smart-2b3ee904-3d02-4a44-aa0d-c97375087ccd
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1436288246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.1436288246
Directory	/workspace/1.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.3966405824
Short name	T37
Test name
Test status
Simulation time	130680854 ps
CPU time	2.4 seconds
Started	Dec 31 12:49:46 PM PST 23
Finished	Dec 31 12:49:49 PM PST 23
Peak memory	201716 kb
Host	smart-60c6544f-4aff-4e71-b60c-845583964bfe
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3966405824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.3966405824
Directory	/workspace/1.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.536199398
Short name	T83
Test name
Test status
Simulation time	28349233 ps
CPU time	0.91 seconds
Started	Dec 31 12:50:16 PM PST 23
Finished	Dec 31 12:50:17 PM PST 23
Peak memory	201644 kb
Host	smart-7d65391b-7ba3-42e6-b7bc-5bfe33009cb8
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536199398 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_mem_rw_with_rand_reset.536199398
Directory	/workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3093982620
Short name	T82
Test name
Test status
Simulation time	41729349 ps
CPU time	0.81 seconds
Started	Dec 31 12:50:03 PM PST 23
Finished	Dec 31 12:50:05 PM PST 23
Peak memory	201372 kb
Host	smart-d08da97e-61d1-4582-9693-e0ebfcdebcb2
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093982620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.3093982620
Directory	/workspace/10.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.4200036951
Short name	T85
Test name
Test status
Simulation time	169082258 ps
CPU time	1.13 seconds
Started	Dec 31 12:49:56 PM PST 23
Finished	Dec 31 12:49:59 PM PST 23
Peak memory	201544 kb
Host	smart-bddd6e95-213d-4f45-8b3e-a0101b61fd83
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200036951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_ csr_outstanding.4200036951
Directory	/workspace/10.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_tl_errors.253086697
Short name	T11
Test name
Test status
Simulation time	71157731 ps
CPU time	2.12 seconds
Started	Dec 31 12:49:54 PM PST 23
Finished	Dec 31 12:49:59 PM PST 23
Peak memory	201480 kb
Host	smart-808781b6-7398-4dc6-873e-f0e5b9835bac
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=253086697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.253086697
Directory	/workspace/10.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.705087175
Short name	T99
Test name
Test status
Simulation time	273637275 ps
CPU time	4.43 seconds
Started	Dec 31 12:49:52 PM PST 23
Finished	Dec 31 12:49:59 PM PST 23
Peak memory	201552 kb
Host	smart-e5c44c74-9c48-4c94-86ce-1cf239fef5d3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=705087175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.705087175
Directory	/workspace/10.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.1046544982
Short name	T115
Test name
Test status
Simulation time	37759278 ps
CPU time	1.47 seconds
Started	Dec 31 12:49:50 PM PST 23
Finished	Dec 31 12:49:53 PM PST 23
Peak memory	211540 kb
Host	smart-269f34ca-a3fb-438a-98d1-94b069407a62
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046544982 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_mem_rw_with_rand_reset.1046544982
Directory	/workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_csr_rw.1823438706
Short name	T89
Test name
Test status
Simulation time	57167947 ps
CPU time	0.99 seconds
Started	Dec 31 12:50:09 PM PST 23
Finished	Dec 31 12:50:16 PM PST 23
Peak memory	201704 kb
Host	smart-d4861614-48e1-43a9-ac9b-393ead30c5c6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823438706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.1823438706
Directory	/workspace/11.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.971031013
Short name	T27
Test name
Test status
Simulation time	59610634 ps
CPU time	1 seconds
Started	Dec 31 12:50:03 PM PST 23
Finished	Dec 31 12:50:05 PM PST 23
Peak memory	201592 kb
Host	smart-97466acc-e6c6-4326-9320-29200c5ccd54
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971031013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_c sr_outstanding.971031013
Directory	/workspace/11.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_tl_errors.1653627379
Short name	T28
Test name
Test status
Simulation time	45517329 ps
CPU time	1.41 seconds
Started	Dec 31 12:49:45 PM PST 23
Finished	Dec 31 12:49:48 PM PST 23
Peak memory	201712 kb
Host	smart-63e6d93f-df23-4aee-aae4-ef4dd5b1afe5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1653627379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.1653627379
Directory	/workspace/11.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.836881063
Short name	T139
Test name
Test status
Simulation time	36300251 ps
CPU time	1.57 seconds
Started	Dec 31 12:49:39 PM PST 23
Finished	Dec 31 12:49:42 PM PST 23
Peak memory	209852 kb
Host	smart-adfccdf9-b930-4021-8933-f8c503ac7659
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836881063 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_mem_rw_with_rand_reset.836881063
Directory	/workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_csr_rw.513416847
Short name	T44
Test name
Test status
Simulation time	44236162 ps
CPU time	0.77 seconds
Started	Dec 31 12:49:47 PM PST 23
Finished	Dec 31 12:49:49 PM PST 23
Peak memory	201316 kb
Host	smart-ec583d75-b6d1-4147-8ed9-68d0bdc1b5ec
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513416847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.513416847
Directory	/workspace/12.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_intr_test.1101870522
Short name	T120
Test name
Test status
Simulation time	121725150 ps
CPU time	0.72 seconds
Started	Dec 31 12:50:15 PM PST 23
Finished	Dec 31 12:50:17 PM PST 23
Peak memory	200596 kb
Host	smart-70971d70-372b-480b-9577-16b4141a24b5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1101870522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.1101870522
Directory	/workspace/12.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.251397750
Short name	T96
Test name
Test status
Simulation time	147180533 ps
CPU time	1.5 seconds
Started	Dec 31 12:49:51 PM PST 23
Finished	Dec 31 12:49:54 PM PST 23
Peak memory	201476 kb
Host	smart-67c0e0a1-9a7a-45d3-be49-c870d013c4c7
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251397750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_c sr_outstanding.251397750
Directory	/workspace/12.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.973636373
Short name	T29
Test name
Test status
Simulation time	218873085 ps
CPU time	4.02 seconds
Started	Dec 31 12:49:35 PM PST 23
Finished	Dec 31 12:49:40 PM PST 23
Peak memory	201748 kb
Host	smart-1e76cbd0-889b-4f07-a83b-8286b7a6bc1c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=973636373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.973636373
Directory	/workspace/12.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.3521061498
Short name	T106
Test name
Test status
Simulation time	37986299 ps
CPU time	0.94 seconds
Started	Dec 31 12:50:21 PM PST 23
Finished	Dec 31 12:50:24 PM PST 23
Peak memory	201756 kb
Host	smart-6b784532-a7af-43b8-844a-14be8ba7cffb
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521061498 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_mem_rw_with_rand_reset.3521061498
Directory	/workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_csr_rw.1721311625
Short name	T60
Test name
Test status
Simulation time	43523376 ps
CPU time	0.8 seconds
Started	Dec 31 12:50:20 PM PST 23
Finished	Dec 31 12:50:22 PM PST 23
Peak memory	201452 kb
Host	smart-32c656e6-075a-48b4-a9e5-ae34689177c5
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721311625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.1721311625
Directory	/workspace/13.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_intr_test.138652673
Short name	T62
Test name
Test status
Simulation time	24836423 ps
CPU time	0.64 seconds
Started	Dec 31 12:49:49 PM PST 23
Finished	Dec 31 12:49:50 PM PST 23
Peak memory	200736 kb
Host	smart-a492cda9-3246-4b3c-9365-ad6680106803
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=138652673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.138652673
Directory	/workspace/13.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.825266403
Short name	T125
Test name
Test status
Simulation time	179138666 ps
CPU time	1.55 seconds
Started	Dec 31 12:50:20 PM PST 23
Finished	Dec 31 12:50:24 PM PST 23
Peak memory	201524 kb
Host	smart-9c3ecc06-2805-4133-9458-38b1561c7c95
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825266403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_c sr_outstanding.825266403
Directory	/workspace/13.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_tl_errors.275970678
Short name	T56
Test name
Test status
Simulation time	243005110 ps
CPU time	2.59 seconds
Started	Dec 31 12:49:51 PM PST 23
Finished	Dec 31 12:49:55 PM PST 23
Peak memory	201684 kb
Host	smart-8944f3d4-4a2a-4f0b-b1b6-537e4b2915b2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=275970678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.275970678
Directory	/workspace/13.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2170765536
Short name	T90
Test name
Test status
Simulation time	32322244 ps
CPU time	1.21 seconds
Started	Dec 31 12:49:45 PM PST 23
Finished	Dec 31 12:49:48 PM PST 23
Peak memory	201792 kb
Host	smart-98e80101-8d8c-453f-82ac-439e2cc9914c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170765536 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_mem_rw_with_rand_reset.2170765536
Directory	/workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_csr_rw.1842427816
Short name	T127
Test name
Test status
Simulation time	54095986 ps
CPU time	0.81 seconds
Started	Dec 31 12:49:49 PM PST 23
Finished	Dec 31 12:49:51 PM PST 23
Peak memory	201448 kb
Host	smart-221376d3-3fd9-4b78-8a6e-5c607a693e1b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842427816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.1842427816
Directory	/workspace/14.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_intr_test.454483462
Short name	T98
Test name
Test status
Simulation time	23569013 ps
CPU time	0.65 seconds
Started	Dec 31 12:49:49 PM PST 23
Finished	Dec 31 12:49:51 PM PST 23
Peak memory	200788 kb
Host	smart-ef71e5d8-872d-45e8-b304-f14669d499fb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=454483462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.454483462
Directory	/workspace/14.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.4071657950
Short name	T88
Test name
Test status
Simulation time	41787123 ps
CPU time	1 seconds
Started	Dec 31 12:49:45 PM PST 23
Finished	Dec 31 12:49:47 PM PST 23
Peak memory	201620 kb
Host	smart-bacd633d-898a-42d8-b22b-9ce875e2aa5b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071657950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_ csr_outstanding.4071657950
Directory	/workspace/14.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_tl_errors.13173972
Short name	T137
Test name
Test status
Simulation time	113436915 ps
CPU time	3.33 seconds
Started	Dec 31 12:49:57 PM PST 23
Finished	Dec 31 12:50:02 PM PST 23
Peak memory	201740 kb
Host	smart-685690ba-b34c-4676-83d1-c9910211f2a9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=13173972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.13173972
Directory	/workspace/14.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.518460481
Short name	T59
Test name
Test status
Simulation time	45055971 ps
CPU time	0.98 seconds
Started	Dec 31 12:49:57 PM PST 23
Finished	Dec 31 12:50:00 PM PST 23
Peak memory	201700 kb
Host	smart-af25b178-5cdf-4698-89f1-9f94c334a03d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518460481 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_mem_rw_with_rand_reset.518460481
Directory	/workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_csr_rw.2942095083
Short name	T45
Test name
Test status
Simulation time	79179562 ps
CPU time	1.06 seconds
Started	Dec 31 12:49:54 PM PST 23
Finished	Dec 31 12:49:57 PM PST 23
Peak memory	201800 kb
Host	smart-4aef1114-2b55-4a77-9002-5d85e1167044
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942095083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.2942095083
Directory	/workspace/15.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_intr_test.4191184099
Short name	T134
Test name
Test status
Simulation time	24072548 ps
CPU time	0.61 seconds
Started	Dec 31 12:50:20 PM PST 23
Finished	Dec 31 12:50:22 PM PST 23
Peak memory	200728 kb
Host	smart-8c5f80dd-8cc8-4ac5-a353-ba24bc7b5518
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4191184099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.4191184099
Directory	/workspace/15.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.4074408849
Short name	T36
Test name
Test status
Simulation time	203319213 ps
CPU time	1.41 seconds
Started	Dec 31 12:50:07 PM PST 23
Finished	Dec 31 12:50:09 PM PST 23
Peak memory	201692 kb
Host	smart-ce4b33dc-75c3-4774-80ff-135d30aca025
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074408849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_ csr_outstanding.4074408849
Directory	/workspace/15.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_tl_errors.228950002
Short name	T58
Test name
Test status
Simulation time	243669694 ps
CPU time	2.47 seconds
Started	Dec 31 12:49:58 PM PST 23
Finished	Dec 31 12:50:02 PM PST 23
Peak memory	201636 kb
Host	smart-010811a2-e985-4527-a2b9-27196231a616
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=228950002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.228950002
Directory	/workspace/15.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.1657474566
Short name	T66
Test name
Test status
Simulation time	123155062 ps
CPU time	2.5 seconds
Started	Dec 31 12:49:48 PM PST 23
Finished	Dec 31 12:49:51 PM PST 23
Peak memory	201768 kb
Host	smart-2c6a525b-9701-4ce4-a4ea-13614f7beb69
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1657474566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.1657474566
Directory	/workspace/15.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.3954172274
Short name	T17
Test name
Test status
Simulation time	37744657 ps
CPU time	1.01 seconds
Started	Dec 31 12:50:11 PM PST 23
Finished	Dec 31 12:50:12 PM PST 23
Peak memory	201732 kb
Host	smart-cd083fa1-1fa1-4157-9144-794f0123df57
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954172274 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_mem_rw_with_rand_reset.3954172274
Directory	/workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_csr_rw.1561214133
Short name	T47
Test name
Test status
Simulation time	91744944 ps
CPU time	0.99 seconds
Started	Dec 31 12:50:05 PM PST 23
Finished	Dec 31 12:50:07 PM PST 23
Peak memory	201784 kb
Host	smart-b0e7b84c-b429-47ef-82c0-2d4f40e0d4df
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561214133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.1561214133
Directory	/workspace/16.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.2071792365
Short name	T55
Test name
Test status
Simulation time	106268125 ps
CPU time	1.37 seconds
Started	Dec 31 12:50:10 PM PST 23
Finished	Dec 31 12:50:12 PM PST 23
Peak memory	201540 kb
Host	smart-4e78cfd6-61e3-4e0c-b073-40c1a462657d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071792365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_ csr_outstanding.2071792365
Directory	/workspace/16.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_tl_errors.2706869276
Short name	T132
Test name
Test status
Simulation time	170495247 ps
CPU time	1.94 seconds
Started	Dec 31 12:50:23 PM PST 23
Finished	Dec 31 12:50:27 PM PST 23
Peak memory	201604 kb
Host	smart-ff17dc09-e68f-4369-a594-569e59309ea8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2706869276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.2706869276
Directory	/workspace/16.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.1636137768
Short name	T39
Test name
Test status
Simulation time	136430103 ps
CPU time	2.36 seconds
Started	Dec 31 12:50:03 PM PST 23
Finished	Dec 31 12:50:07 PM PST 23
Peak memory	201748 kb
Host	smart-acad16ee-a0a6-45ec-a1a8-ddb5b6f34215
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1636137768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.1636137768
Directory	/workspace/16.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_csr_rw.2040875842
Short name	T107
Test name
Test status
Simulation time	34846019 ps
CPU time	0.92 seconds
Started	Dec 31 12:50:07 PM PST 23
Finished	Dec 31 12:50:09 PM PST 23
Peak memory	201696 kb
Host	smart-cdc63fc2-778e-4cb9-8f05-ca6023e1ba62
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040875842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.2040875842
Directory	/workspace/17.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_intr_test.2759324451
Short name	T77
Test name
Test status
Simulation time	47686953 ps
CPU time	0.64 seconds
Started	Dec 31 12:50:17 PM PST 23
Finished	Dec 31 12:50:19 PM PST 23
Peak memory	200756 kb
Host	smart-9b2fa316-6dcb-4b44-bd52-b8d00e08885f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2759324451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.2759324451
Directory	/workspace/17.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.693061982
Short name	T95
Test name
Test status
Simulation time	76460977 ps
CPU time	0.97 seconds
Started	Dec 31 12:50:16 PM PST 23
Finished	Dec 31 12:50:18 PM PST 23
Peak memory	201596 kb
Host	smart-a4fa0c31-e6e1-48fc-87e1-be90a205deb0
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693061982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_c sr_outstanding.693061982
Directory	/workspace/17.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.4211374723
Short name	T9
Test name
Test status
Simulation time	54763278 ps
CPU time	1.13 seconds
Started	Dec 31 12:50:10 PM PST 23
Finished	Dec 31 12:50:12 PM PST 23
Peak memory	201780 kb
Host	smart-45216da7-1b2b-4ef7-8293-4707acb975f2
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211374723 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_mem_rw_with_rand_reset.4211374723
Directory	/workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_csr_rw.2203180037
Short name	T124
Test name
Test status
Simulation time	33725674 ps
CPU time	0.79 seconds
Started	Dec 31 12:50:20 PM PST 23
Finished	Dec 31 12:50:23 PM PST 23
Peak memory	201372 kb
Host	smart-32596382-e879-4679-821f-d9cf8bf618bb
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203180037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.2203180037
Directory	/workspace/18.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_intr_test.55132232
Short name	T80
Test name
Test status
Simulation time	48102393 ps
CPU time	0.66 seconds
Started	Dec 31 12:50:26 PM PST 23
Finished	Dec 31 12:50:28 PM PST 23
Peak memory	200788 kb
Host	smart-dafce96c-120f-4bbb-b52a-7bff4edd5040
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=55132232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.55132232
Directory	/workspace/18.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.2396325215
Short name	T86
Test name
Test status
Simulation time	41699130 ps
CPU time	0.97 seconds
Started	Dec 31 12:50:25 PM PST 23
Finished	Dec 31 12:50:28 PM PST 23
Peak memory	201608 kb
Host	smart-52260315-0210-463f-bd12-4d24bd346e6f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396325215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_ csr_outstanding.2396325215
Directory	/workspace/18.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_tl_errors.4231087087
Short name	T110
Test name
Test status
Simulation time	90617453 ps
CPU time	1.34 seconds
Started	Dec 31 12:50:06 PM PST 23
Finished	Dec 31 12:50:09 PM PST 23
Peak memory	201640 kb
Host	smart-fcdfca5d-97d6-4086-b9a0-a9bf4f9985ea
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4231087087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.4231087087
Directory	/workspace/18.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.1235478324
Short name	T149
Test name
Test status
Simulation time	28301414 ps
CPU time	0.94 seconds
Started	Dec 31 12:50:01 PM PST 23
Finished	Dec 31 12:50:03 PM PST 23
Peak memory	201728 kb
Host	smart-69eae886-232e-43a0-9ca9-8d7100c2678a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235478324 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_mem_rw_with_rand_reset.1235478324
Directory	/workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_csr_rw.3346290508
Short name	T42
Test name
Test status
Simulation time	58425484 ps
CPU time	0.8 seconds
Started	Dec 31 12:49:53 PM PST 23
Finished	Dec 31 12:49:56 PM PST 23
Peak memory	201448 kb
Host	smart-6d50e3fa-77f7-4bb4-a87f-c0852debe3e6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346290508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.3346290508
Directory	/workspace/19.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.140230330
Short name	T146
Test name
Test status
Simulation time	37702700 ps
CPU time	0.96 seconds
Started	Dec 31 12:50:10 PM PST 23
Finished	Dec 31 12:50:12 PM PST 23
Peak memory	201600 kb
Host	smart-aa8c7093-8cfd-4ffd-b630-66d8d748dc2e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140230330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_c sr_outstanding.140230330
Directory	/workspace/19.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_tl_errors.1676976246
Short name	T121
Test name
Test status
Simulation time	72598120 ps
CPU time	2.21 seconds
Started	Dec 31 12:50:27 PM PST 23
Finished	Dec 31 12:50:32 PM PST 23
Peak memory	201652 kb
Host	smart-98b14193-8be2-4486-8b10-a8aba6fb8b6f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1676976246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.1676976246
Directory	/workspace/19.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.77722890
Short name	T50
Test name
Test status
Simulation time	66993681 ps
CPU time	1.77 seconds
Started	Dec 31 12:50:00 PM PST 23
Finished	Dec 31 12:50:03 PM PST 23
Peak memory	201556 kb
Host	smart-c938410d-5451-42f0-a3b0-cd15f893fa3e
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77722890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.77722890
Directory	/workspace/2.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.3130931597
Short name	T135
Test name
Test status
Simulation time	388042949 ps
CPU time	8.85 seconds
Started	Dec 31 12:49:51 PM PST 23
Finished	Dec 31 12:50:02 PM PST 23
Peak memory	201776 kb
Host	smart-397a66a2-a0da-4c0b-8a18-030a66b09f7a
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130931597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.3130931597
Directory	/workspace/2.usbdev_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.853215568
Short name	T6
Test name
Test status
Simulation time	31204306 ps
CPU time	0.73 seconds
Started	Dec 31 12:49:45 PM PST 23
Finished	Dec 31 12:49:47 PM PST 23
Peak memory	201480 kb
Host	smart-6099fcdd-9669-4f52-802d-a7ae6ed75eef
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853215568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.853215568
Directory	/workspace/2.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_rw.700867551
Short name	T53
Test name
Test status
Simulation time	61917528 ps
CPU time	0.97 seconds
Started	Dec 31 12:49:34 PM PST 23
Finished	Dec 31 12:49:37 PM PST 23
Peak memory	201732 kb
Host	smart-63e6a191-5dec-4eb9-88fe-0ef6ca8563ab
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700867551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.700867551
Directory	/workspace/2.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_intr_test.2855687804
Short name	T143
Test name
Test status
Simulation time	29562190 ps
CPU time	0.68 seconds
Started	Dec 31 12:49:35 PM PST 23
Finished	Dec 31 12:49:37 PM PST 23
Peak memory	200736 kb
Host	smart-bc5f9214-f1f9-46a6-a734-cd4c54c02147
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2855687804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.2855687804
Directory	/workspace/2.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.1537077189
Short name	T8
Test name
Test status
Simulation time	61897259 ps
CPU time	2.07 seconds
Started	Dec 31 12:49:34 PM PST 23
Finished	Dec 31 12:49:38 PM PST 23
Peak memory	201620 kb
Host	smart-c0ed9c01-ff94-427b-a971-9b46a05655c6
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1537077189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.1537077189
Directory	/workspace/2.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_mem_walk.2716173029
Short name	T112
Test name
Test status
Simulation time	472352151 ps
CPU time	4.11 seconds
Started	Dec 31 12:49:49 PM PST 23
Finished	Dec 31 12:49:58 PM PST 23
Peak memory	201628 kb
Host	smart-a9eda16c-9dd9-4274-ab1a-bc946b4351c5
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2716173029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.2716173029
Directory	/workspace/2.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.1697779316
Short name	T100
Test name
Test status
Simulation time	71857849 ps
CPU time	0.98 seconds
Started	Dec 31 12:49:35 PM PST 23
Finished	Dec 31 12:49:37 PM PST 23
Peak memory	201592 kb
Host	smart-a116081f-df64-4d25-b7b1-06ed12e4d7f9
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697779316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_c sr_outstanding.1697779316
Directory	/workspace/2.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_tl_errors.3243307184
Short name	T97
Test name
Test status
Simulation time	340864994 ps
CPU time	3.23 seconds
Started	Dec 31 12:49:50 PM PST 23
Finished	Dec 31 12:49:55 PM PST 23
Peak memory	201644 kb
Host	smart-94ffeaf8-3432-407c-af02-af3775aea007
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3243307184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.3243307184
Directory	/workspace/2.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/20.usbdev_intr_test.3007525859
Short name	T75
Test name
Test status
Simulation time	24331083 ps
CPU time	0.62 seconds
Started	Dec 31 12:49:52 PM PST 23
Finished	Dec 31 12:49:55 PM PST 23
Peak memory	200692 kb
Host	smart-efbe9e7e-d0e0-4c3d-9cd1-b8c962ef59f9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3007525859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.3007525859
Directory	/workspace/20.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.usbdev_intr_test.4170503718
Short name	T10
Test name
Test status
Simulation time	21787523 ps
CPU time	0.62 seconds
Started	Dec 31 12:50:13 PM PST 23
Finished	Dec 31 12:50:14 PM PST 23
Peak memory	200744 kb
Host	smart-22fd6564-e6e3-4bcc-9ee1-86437d8523a1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4170503718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.4170503718
Directory	/workspace/21.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.usbdev_intr_test.825611762
Short name	T126
Test name
Test status
Simulation time	100734936 ps
CPU time	0.67 seconds
Started	Dec 31 12:50:15 PM PST 23
Finished	Dec 31 12:50:17 PM PST 23
Peak memory	200784 kb
Host	smart-a52b50d7-30e9-49c3-bef7-aa8fd69df81f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=825611762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.825611762
Directory	/workspace/22.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.usbdev_intr_test.3572121793
Short name	T78
Test name
Test status
Simulation time	30749642 ps
CPU time	0.64 seconds
Started	Dec 31 12:50:08 PM PST 23
Finished	Dec 31 12:50:10 PM PST 23
Peak memory	200712 kb
Host	smart-d38df0d5-66c8-43d5-8f29-cf9f876decb9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3572121793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.3572121793
Directory	/workspace/24.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.usbdev_intr_test.959671407
Short name	T118
Test name
Test status
Simulation time	23035074 ps
CPU time	0.61 seconds
Started	Dec 31 12:50:15 PM PST 23
Finished	Dec 31 12:50:16 PM PST 23
Peak memory	200788 kb
Host	smart-ffb09c90-772d-43b6-9fa1-bb9c65c13456
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=959671407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.959671407
Directory	/workspace/26.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.usbdev_intr_test.367742632
Short name	T136
Test name
Test status
Simulation time	42234954 ps
CPU time	0.64 seconds
Started	Dec 31 12:50:19 PM PST 23
Finished	Dec 31 12:50:21 PM PST 23
Peak memory	200792 kb
Host	smart-a4397796-74cc-42bd-a4e6-cd2211d51557
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=367742632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.367742632
Directory	/workspace/27.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.1560003894
Short name	T49
Test name
Test status
Simulation time	346374784 ps
CPU time	3.39 seconds
Started	Dec 31 12:49:28 PM PST 23
Finished	Dec 31 12:49:37 PM PST 23
Peak memory	201708 kb
Host	smart-af6eba38-374c-4796-bfcd-42c3543e46c7
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560003894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.1560003894
Directory	/workspace/3.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.512156733
Short name	T33
Test name
Test status
Simulation time	442541989 ps
CPU time	8.81 seconds
Started	Dec 31 12:49:37 PM PST 23
Finished	Dec 31 12:49:47 PM PST 23
Peak memory	201664 kb
Host	smart-3ab4e85b-3ff8-4911-831f-751174b41129
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512156733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.512156733
Directory	/workspace/3.usbdev_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.796854749
Short name	T129
Test name
Test status
Simulation time	29154886 ps
CPU time	0.69 seconds
Started	Dec 31 12:49:47 PM PST 23
Finished	Dec 31 12:49:49 PM PST 23
Peak memory	201428 kb
Host	smart-fb7de569-84dc-48d7-b5ea-097f7f4b55fc
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796854749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.796854749
Directory	/workspace/3.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2983942295
Short name	T131
Test name
Test status
Simulation time	77251460 ps
CPU time	1.39 seconds
Started	Dec 31 12:49:56 PM PST 23
Finished	Dec 31 12:50:00 PM PST 23
Peak memory	209900 kb
Host	smart-560bbf4d-e06c-493a-8f65-e39409de873f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983942295 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_mem_rw_with_rand_reset.2983942295
Directory	/workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2802913797
Short name	T102
Test name
Test status
Simulation time	79883344 ps
CPU time	1.13 seconds
Started	Dec 31 12:49:44 PM PST 23
Finished	Dec 31 12:49:46 PM PST 23
Peak memory	201776 kb
Host	smart-37fa214e-4f77-412a-8c63-739dd5a1149e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802913797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.2802913797
Directory	/workspace/3.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.988893233
Short name	T52
Test name
Test status
Simulation time	64358828 ps
CPU time	2.13 seconds
Started	Dec 31 12:49:29 PM PST 23
Finished	Dec 31 12:49:32 PM PST 23
Peak memory	201616 kb
Host	smart-4554d351-e2ad-4ab9-8d1b-3f37daec8d4b
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=988893233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.988893233
Directory	/workspace/3.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_mem_walk.140977916
Short name	T93
Test name
Test status
Simulation time	155220658 ps
CPU time	3.73 seconds
Started	Dec 31 12:49:25 PM PST 23
Finished	Dec 31 12:49:35 PM PST 23
Peak memory	201664 kb
Host	smart-838516e9-ff9f-40ae-9551-85c94f4d1223
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=140977916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.140977916
Directory	/workspace/3.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3075078517
Short name	T144
Test name
Test status
Simulation time	126791330 ps
CPU time	1.06 seconds
Started	Dec 31 12:49:44 PM PST 23
Finished	Dec 31 12:49:55 PM PST 23
Peak memory	201520 kb
Host	smart-5b1bc3cd-438c-4e0c-90f0-c37c84ba4506
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075078517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_c sr_outstanding.3075078517
Directory	/workspace/3.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_tl_errors.3366714264
Short name	T16
Test name
Test status
Simulation time	90317884 ps
CPU time	2.13 seconds
Started	Dec 31 12:49:41 PM PST 23
Finished	Dec 31 12:49:44 PM PST 23
Peak memory	201672 kb
Host	smart-80f48370-38bf-4fd2-b9b6-6c4aebf6b27e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3366714264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.3366714264
Directory	/workspace/3.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/30.usbdev_intr_test.1887310404
Short name	T116
Test name
Test status
Simulation time	45748107 ps
CPU time	0.63 seconds
Started	Dec 31 12:50:21 PM PST 23
Finished	Dec 31 12:50:23 PM PST 23
Peak memory	200660 kb
Host	smart-3f54a10b-b16a-4ffa-9932-b4389e8e9033
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1887310404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.1887310404
Directory	/workspace/30.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.usbdev_intr_test.37078877
Short name	T113
Test name
Test status
Simulation time	29938792 ps
CPU time	0.64 seconds
Started	Dec 31 12:49:51 PM PST 23
Finished	Dec 31 12:49:53 PM PST 23
Peak memory	200808 kb
Host	smart-971295f1-c5b3-4aeb-a035-bdcc9fa3dbcd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=37078877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.37078877
Directory	/workspace/35.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.usbdev_intr_test.2333007162
Short name	T81
Test name
Test status
Simulation time	22265449 ps
CPU time	0.63 seconds
Started	Dec 31 12:50:16 PM PST 23
Finished	Dec 31 12:50:17 PM PST 23
Peak memory	200820 kb
Host	smart-eee5eee4-3b4c-4e8a-b721-b89cd529e83b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2333007162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.2333007162
Directory	/workspace/38.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.usbdev_intr_test.3926208002
Short name	T61
Test name
Test status
Simulation time	26737312 ps
CPU time	0.61 seconds
Started	Dec 31 12:50:05 PM PST 23
Finished	Dec 31 12:50:07 PM PST 23
Peak memory	200712 kb
Host	smart-0c4a288a-88ca-4c83-b02f-86caeb6a445b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3926208002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.3926208002
Directory	/workspace/39.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.555633591
Short name	T87
Test name
Test status
Simulation time	69190394 ps
CPU time	1.78 seconds
Started	Dec 31 12:49:30 PM PST 23
Finished	Dec 31 12:49:33 PM PST 23
Peak memory	201752 kb
Host	smart-a9be1712-4e50-42bc-bbe4-d3aaaeb3c80e
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555633591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.555633591
Directory	/workspace/4.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.2259064388
Short name	T51
Test name
Test status
Simulation time	374743399 ps
CPU time	8.75 seconds
Started	Dec 31 12:49:42 PM PST 23
Finished	Dec 31 12:49:51 PM PST 23
Peak memory	201968 kb
Host	smart-3af5a734-8792-4616-9497-9b3761a73964
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259064388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.2259064388
Directory	/workspace/4.usbdev_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.357848560
Short name	T101
Test name
Test status
Simulation time	68953153 ps
CPU time	2.02 seconds
Started	Dec 31 12:49:56 PM PST 23
Finished	Dec 31 12:50:00 PM PST 23
Peak memory	209956 kb
Host	smart-71e3c370-0c2b-4786-93c8-ff287435aa26
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357848560 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_mem_rw_with_rand_reset.357848560
Directory	/workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_rw.2933002772
Short name	T41
Test name
Test status
Simulation time	50110217 ps
CPU time	0.84 seconds
Started	Dec 31 12:50:25 PM PST 23
Finished	Dec 31 12:50:28 PM PST 23
Peak memory	201412 kb
Host	smart-2019b441-6766-43e5-9116-80d4f4286a01
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933002772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.2933002772
Directory	/workspace/4.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_intr_test.3650142101
Short name	T35
Test name
Test status
Simulation time	25662600 ps
CPU time	0.63 seconds
Started	Dec 31 12:50:00 PM PST 23
Finished	Dec 31 12:50:02 PM PST 23
Peak memory	200692 kb
Host	smart-46e0d0ba-fce7-4b3e-8df7-f33b3fde6709
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3650142101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.3650142101
Directory	/workspace/4.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2319616904
Short name	T142
Test name
Test status
Simulation time	139488215 ps
CPU time	1.37 seconds
Started	Dec 31 12:49:55 PM PST 23
Finished	Dec 31 12:49:59 PM PST 23
Peak memory	201636 kb
Host	smart-c708c65f-1368-4d4c-b87f-052652a4df30
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2319616904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.2319616904
Directory	/workspace/4.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.599231141
Short name	T145
Test name
Test status
Simulation time	138649940 ps
CPU time	1.42 seconds
Started	Dec 31 12:49:55 PM PST 23
Finished	Dec 31 12:49:59 PM PST 23
Peak memory	201628 kb
Host	smart-78e79829-7452-4ae0-b7c9-4742f13ae517
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599231141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_cs r_outstanding.599231141
Directory	/workspace/4.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_tl_errors.3463909169
Short name	T119
Test name
Test status
Simulation time	55856288 ps
CPU time	1.6 seconds
Started	Dec 31 12:49:41 PM PST 23
Finished	Dec 31 12:49:44 PM PST 23
Peak memory	201728 kb
Host	smart-8f9640ee-23e7-44dd-bed9-e8acd05cf302
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3463909169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.3463909169
Directory	/workspace/4.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.3207046946
Short name	T64
Test name
Test status
Simulation time	120617540 ps
CPU time	2.34 seconds
Started	Dec 31 12:49:36 PM PST 23
Finished	Dec 31 12:49:40 PM PST 23
Peak memory	201668 kb
Host	smart-c916488e-37fb-418a-a3a9-8cf1640d7a12
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3207046946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.3207046946
Directory	/workspace/4.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/43.usbdev_intr_test.2489175812
Short name	T72
Test name
Test status
Simulation time	27618401 ps
CPU time	0.63 seconds
Started	Dec 31 12:50:13 PM PST 23
Finished	Dec 31 12:50:15 PM PST 23
Peak memory	200772 kb
Host	smart-a7f721e8-24b9-431a-a6e5-2513827174b2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2489175812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.2489175812
Directory	/workspace/43.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.usbdev_intr_test.480273106
Short name	T70
Test name
Test status
Simulation time	28404943 ps
CPU time	0.65 seconds
Started	Dec 31 12:49:58 PM PST 23
Finished	Dec 31 12:50:00 PM PST 23
Peak memory	200764 kb
Host	smart-ea9786a5-1564-4e2f-a6b9-478de65a107c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=480273106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.480273106
Directory	/workspace/44.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.usbdev_intr_test.3920832967
Short name	T4
Test name
Test status
Simulation time	29275424 ps
CPU time	0.62 seconds
Started	Dec 31 12:50:25 PM PST 23
Finished	Dec 31 12:50:27 PM PST 23
Peak memory	201044 kb
Host	smart-7d04ce00-552d-403a-8ccb-41e389d4fe55
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3920832967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.3920832967
Directory	/workspace/47.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.usbdev_intr_test.957634440
Short name	T23
Test name
Test status
Simulation time	25994115 ps
CPU time	0.62 seconds
Started	Dec 31 12:50:09 PM PST 23
Finished	Dec 31 12:50:11 PM PST 23
Peak memory	200812 kb
Host	smart-b510adaf-3888-42b4-a1bb-0f7bd0a6e0ad
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=957634440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.957634440
Directory	/workspace/48.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.usbdev_intr_test.2716994392
Short name	T74
Test name
Test status
Simulation time	22701167 ps
CPU time	0.63 seconds
Started	Dec 31 12:50:34 PM PST 23
Finished	Dec 31 12:50:48 PM PST 23
Peak memory	200732 kb
Host	smart-1cd19a3e-5aea-42ba-9d8b-fb9e5c457cad
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2716994392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.2716994392
Directory	/workspace/49.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.902294396
Short name	T14
Test name
Test status
Simulation time	51077037 ps
CPU time	1.35 seconds
Started	Dec 31 12:49:52 PM PST 23
Finished	Dec 31 12:49:55 PM PST 23
Peak memory	209956 kb
Host	smart-605a65ec-a6a9-44d6-b2df-339aa3a3f974
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902294396 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_mem_rw_with_rand_reset.902294396
Directory	/workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_csr_rw.1827396605
Short name	T40
Test name
Test status
Simulation time	64447218 ps
CPU time	0.79 seconds
Started	Dec 31 12:49:27 PM PST 23
Finished	Dec 31 12:49:32 PM PST 23
Peak memory	201456 kb
Host	smart-e750b550-90c5-4420-bef5-fe4faaa2cab2
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827396605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.1827396605
Directory	/workspace/5.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.2991401417
Short name	T103
Test name
Test status
Simulation time	87014457 ps
CPU time	1.45 seconds
Started	Dec 31 12:49:52 PM PST 23
Finished	Dec 31 12:49:56 PM PST 23
Peak memory	201664 kb
Host	smart-e07d79f2-5a9a-4819-8527-356323ef1510
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991401417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_c sr_outstanding.2991401417
Directory	/workspace/5.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_tl_errors.1296972330
Short name	T32
Test name
Test status
Simulation time	109507439 ps
CPU time	1.66 seconds
Started	Dec 31 12:49:28 PM PST 23
Finished	Dec 31 12:49:31 PM PST 23
Peak memory	201764 kb
Host	smart-52493a68-8317-4aaa-817d-229ea999510a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1296972330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.1296972330
Directory	/workspace/5.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1642436337
Short name	T46
Test name
Test status
Simulation time	40632554 ps
CPU time	0.96 seconds
Started	Dec 31 12:50:03 PM PST 23
Finished	Dec 31 12:50:05 PM PST 23
Peak memory	201620 kb
Host	smart-a78e3e97-fcbf-4375-9a44-4b79808019af
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642436337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.1642436337
Directory	/workspace/6.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_intr_test.3190014369
Short name	T141
Test name
Test status
Simulation time	32499177 ps
CPU time	0.61 seconds
Started	Dec 31 12:49:50 PM PST 23
Finished	Dec 31 12:49:52 PM PST 23
Peak memory	200708 kb
Host	smart-89a433fa-a472-4cce-97f6-f110168c5d76
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3190014369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.3190014369
Directory	/workspace/6.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3729914345
Short name	T54
Test name
Test status
Simulation time	39864928 ps
CPU time	0.98 seconds
Started	Dec 31 12:49:50 PM PST 23
Finished	Dec 31 12:49:52 PM PST 23
Peak memory	201492 kb
Host	smart-3d4b7a77-409c-4650-a4f3-b690bb11eefe
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729914345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_c sr_outstanding.3729914345
Directory	/workspace/6.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1336307182
Short name	T148
Test name
Test status
Simulation time	163484183 ps
CPU time	1.87 seconds
Started	Dec 31 12:50:03 PM PST 23
Finished	Dec 31 12:50:06 PM PST 23
Peak memory	201660 kb
Host	smart-6034b6e6-efd7-44b7-924f-43e13599c0db
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1336307182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.1336307182
Directory	/workspace/6.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.2112377236
Short name	T133
Test name
Test status
Simulation time	50951570 ps
CPU time	2.01 seconds
Started	Dec 31 12:49:49 PM PST 23
Finished	Dec 31 12:49:52 PM PST 23
Peak memory	209928 kb
Host	smart-cf9b6d8b-95c1-438b-8d62-baad57802dfd
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112377236 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_mem_rw_with_rand_reset.2112377236
Directory	/workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_csr_rw.3982110373
Short name	T91
Test name
Test status
Simulation time	49737819 ps
CPU time	0.85 seconds
Started	Dec 31 12:49:46 PM PST 23
Finished	Dec 31 12:49:48 PM PST 23
Peak memory	201404 kb
Host	smart-39ed60e5-1744-4468-ad9d-eaf72137c6cc
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982110373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.3982110373
Directory	/workspace/7.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_intr_test.73519925
Short name	T73
Test name
Test status
Simulation time	26499915 ps
CPU time	0.65 seconds
Started	Dec 31 12:49:35 PM PST 23
Finished	Dec 31 12:49:37 PM PST 23
Peak memory	200696 kb
Host	smart-0c7f7544-08fa-4949-b18c-70597e1b3d0a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=73519925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.73519925
Directory	/workspace/7.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.394229007
Short name	T92
Test name
Test status
Simulation time	126555953 ps
CPU time	1.45 seconds
Started	Dec 31 12:49:55 PM PST 23
Finished	Dec 31 12:49:59 PM PST 23
Peak memory	201588 kb
Host	smart-2568eeb9-9c64-4a0f-afe8-7dc842324608
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394229007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_cs r_outstanding.394229007
Directory	/workspace/7.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_tl_errors.3408913603
Short name	T147
Test name
Test status
Simulation time	144968926 ps
CPU time	1.7 seconds
Started	Dec 31 12:50:00 PM PST 23
Finished	Dec 31 12:50:03 PM PST 23
Peak memory	201660 kb
Host	smart-ce107cf2-4c5b-41cc-ba89-18d75add54d8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3408913603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.3408913603
Directory	/workspace/7.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1196342219
Short name	T94
Test name
Test status
Simulation time	262871271 ps
CPU time	2.7 seconds
Started	Dec 31 12:49:41 PM PST 23
Finished	Dec 31 12:49:50 PM PST 23
Peak memory	201652 kb
Host	smart-01350573-81c0-4a0e-8b1a-f951cfd86efe
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1196342219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.1196342219
Directory	/workspace/7.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.473281062
Short name	T117
Test name
Test status
Simulation time	23746047 ps
CPU time	0.86 seconds
Started	Dec 31 12:49:54 PM PST 23
Finished	Dec 31 12:49:58 PM PST 23
Peak memory	201672 kb
Host	smart-9ff3d1cc-1ec4-425e-94be-525c2a7975e2
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473281062 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_mem_rw_with_rand_reset.473281062
Directory	/workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2353135127
Short name	T111
Test name
Test status
Simulation time	55355177 ps
CPU time	0.83 seconds
Started	Dec 31 12:49:53 PM PST 23
Finished	Dec 31 12:49:56 PM PST 23
Peak memory	201348 kb
Host	smart-6e54dd9f-a251-4adf-9087-6aeb6e7e5542
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353135127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.2353135127
Directory	/workspace/8.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_intr_test.1821295492
Short name	T76
Test name
Test status
Simulation time	29182305 ps
CPU time	0.69 seconds
Started	Dec 31 12:49:38 PM PST 23
Finished	Dec 31 12:49:40 PM PST 23
Peak memory	200680 kb
Host	smart-f6d34d74-9770-4f01-8d3a-44d1cc66a35d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1821295492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.1821295492
Directory	/workspace/8.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3216202218
Short name	T128
Test name
Test status
Simulation time	38754192 ps
CPU time	0.94 seconds
Started	Dec 31 12:49:31 PM PST 23
Finished	Dec 31 12:49:33 PM PST 23
Peak memory	201520 kb
Host	smart-c56ca7c1-bcba-482e-9494-79f375db717d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216202218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_c sr_outstanding.3216202218
Directory	/workspace/8.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_tl_errors.1930458411
Short name	T57
Test name
Test status
Simulation time	84512371 ps
CPU time	1.9 seconds
Started	Dec 31 12:50:13 PM PST 23
Finished	Dec 31 12:50:16 PM PST 23
Peak memory	201620 kb
Host	smart-fdd19ede-eb31-4703-b09a-90637d767e82
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1930458411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.1930458411
Directory	/workspace/8.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2264004377
Short name	T104
Test name
Test status
Simulation time	60335660 ps
CPU time	1.16 seconds
Started	Dec 31 12:49:53 PM PST 23
Finished	Dec 31 12:49:57 PM PST 23
Peak memory	209956 kb
Host	smart-36a09588-686f-44cd-80a4-17121a62e172
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264004377 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_mem_rw_with_rand_reset.2264004377
Directory	/workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_csr_rw.4096178860
Short name	T130
Test name
Test status
Simulation time	108102031 ps
CPU time	1.07 seconds
Started	Dec 31 12:49:48 PM PST 23
Finished	Dec 31 12:49:50 PM PST 23
Peak memory	201668 kb
Host	smart-3bb5fa0b-cc80-43b2-bd17-810cd379a2b3
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096178860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.4096178860
Directory	/workspace/9.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.3995669808
Short name	T114
Test name
Test status
Simulation time	42119191 ps
CPU time	1.02 seconds
Started	Dec 31 12:49:52 PM PST 23
Finished	Dec 31 12:49:55 PM PST 23
Peak memory	201428 kb
Host	smart-5f547e25-ab67-448d-b196-22b828f534e2
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995669808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_c sr_outstanding.3995669808
Directory	/workspace/9.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_tl_errors.2008648590
Short name	T30
Test name
Test status
Simulation time	145788743 ps
CPU time	1.82 seconds
Started	Dec 31 12:50:00 PM PST 23
Finished	Dec 31 12:50:03 PM PST 23
Peak memory	201480 kb
Host	smart-82a71edf-f5ec-47e6-b9e6-551ebbbc7941
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2008648590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.2008648590
Directory	/workspace/9.usbdev_tl_errors/latest