Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=16}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=16}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=16}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	68	0	68	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=16}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	17	0	17	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=16}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	68	0	68	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	268	1		T4	5		T10	5		T11	2
all_pins[1]	268	1		T4	5		T10	5		T11	2
all_pins[2]	268	1		T4	5		T10	5		T11	2
all_pins[3]	268	1		T4	5		T10	5		T11	2
all_pins[4]	268	1		T4	5		T10	5		T11	2
all_pins[5]	268	1		T4	5		T10	5		T11	2
all_pins[6]	268	1		T4	5		T10	5		T11	2
all_pins[7]	268	1		T4	5		T10	5		T11	2
all_pins[8]	268	1		T4	5		T10	5		T11	2
all_pins[9]	268	1		T4	5		T10	5		T11	2
all_pins[10]	268	1		T4	5		T10	5		T11	2
all_pins[11]	268	1		T4	5		T10	5		T11	2
all_pins[12]	268	1		T4	5		T10	5		T11	2
all_pins[13]	268	1		T4	5		T10	5		T11	2
all_pins[14]	268	1		T4	5		T10	5		T11	2
all_pins[15]	268	1		T4	5		T10	5		T11	2
all_pins[16]	268	1		T4	5		T10	5		T11	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	3713	1		T4	63		T10	74		T11	34
values[0x1]	843	1		T4	22		T10	11		T23	34
transitions[0x0=>0x1]	619	1		T4	14		T10	9		T23	23
transitions[0x1=>0x0]	626	1		T4	14		T10	9		T23	23

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	68	0	68	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	210	1		T4	4		T10	3		T11	2
all_pins[0]	values[0x1]	58	1		T4	1		T10	2		T23	4
all_pins[0]	transitions[0x0=>0x1]	43	1		T10	2		T23	3		T24	1
all_pins[0]	transitions[0x1=>0x0]	29	1		T4	2		T10	1		T34	1
all_pins[1]	values[0x0]	224	1		T4	2		T10	4		T11	2
all_pins[1]	values[0x1]	44	1		T4	3		T10	1		T23	1
all_pins[1]	transitions[0x0=>0x1]	35	1		T4	2		T10	1		T24	1
all_pins[1]	transitions[0x1=>0x0]	40	1		T23	1		T25	5		T61	1
all_pins[2]	values[0x0]	219	1		T4	4		T10	5		T11	2
all_pins[2]	values[0x1]	49	1		T4	1		T23	2		T25	5
all_pins[2]	transitions[0x0=>0x1]	41	1		T4	1		T25	5		T61	1
all_pins[2]	transitions[0x1=>0x0]	32	1		T10	1		T24	2		T34	1
all_pins[3]	values[0x0]	228	1		T4	5		T10	4		T11	2
all_pins[3]	values[0x1]	40	1		T10	1		T23	2		T24	2
all_pins[3]	transitions[0x0=>0x1]	30	1		T23	2		T24	2		T34	1
all_pins[3]	transitions[0x1=>0x0]	36	1		T23	1		T24	2		T25	1
all_pins[4]	values[0x0]	222	1		T4	5		T10	4		T11	2
all_pins[4]	values[0x1]	46	1		T10	1		T23	1		T24	2
all_pins[4]	transitions[0x0=>0x1]	39	1		T24	2		T25	1		T62	2
all_pins[4]	transitions[0x1=>0x0]	36	1		T4	2		T24	1		T25	1
all_pins[5]	values[0x0]	225	1		T4	3		T10	4		T11	2
all_pins[5]	values[0x1]	43	1		T4	2		T10	1		T23	1
all_pins[5]	transitions[0x0=>0x1]	33	1		T4	2		T10	1		T23	1
all_pins[5]	transitions[0x1=>0x0]	31	1		T23	2		T25	1		T35	3
all_pins[6]	values[0x0]	227	1		T4	5		T10	5		T11	2
all_pins[6]	values[0x1]	41	1		T23	2		T25	1		T35	3
all_pins[6]	transitions[0x0=>0x1]	24	1		T25	1		T35	2		T73	1
all_pins[6]	transitions[0x1=>0x0]	38	1		T4	1		T23	4		T24	2
all_pins[7]	values[0x0]	213	1		T4	4		T10	5		T11	2
all_pins[7]	values[0x1]	55	1		T4	1		T23	6		T24	2
all_pins[7]	transitions[0x0=>0x1]	36	1		T23	5		T24	1		T25	1
all_pins[7]	transitions[0x1=>0x0]	34	1		T4	3		T10	2		T24	2
all_pins[8]	values[0x0]	215	1		T4	1		T10	3		T11	2
all_pins[8]	values[0x1]	53	1		T4	4		T10	2		T23	1
all_pins[8]	transitions[0x0=>0x1]	40	1		T4	2		T10	2		T23	1
all_pins[8]	transitions[0x1=>0x0]	30	1		T23	1		T24	3		T25	2
all_pins[9]	values[0x0]	225	1		T4	3		T10	5		T11	2
all_pins[9]	values[0x1]	43	1		T4	2		T23	1		T24	4
all_pins[9]	transitions[0x0=>0x1]	32	1		T23	1		T24	4		T25	1
all_pins[9]	transitions[0x1=>0x0]	47	1		T23	3		T25	2		T35	1
all_pins[10]	values[0x0]	210	1		T4	3		T10	5		T11	2
all_pins[10]	values[0x1]	58	1		T4	2		T23	3		T25	3
all_pins[10]	transitions[0x0=>0x1]	40	1		T4	2		T23	1		T25	3
all_pins[10]	transitions[0x1=>0x0]	39	1		T10	2		T23	1		T24	3
all_pins[11]	values[0x0]	211	1		T4	5		T10	3		T11	2
all_pins[11]	values[0x1]	57	1		T10	2		T23	3		T24	3
all_pins[11]	transitions[0x0=>0x1]	42	1		T10	2		T23	3		T24	3
all_pins[11]	transitions[0x1=>0x0]	41	1		T4	2		T23	2		T24	2
all_pins[12]	values[0x0]	212	1		T4	3		T10	5		T11	2
all_pins[12]	values[0x1]	56	1		T4	2		T23	2		T24	2
all_pins[12]	transitions[0x0=>0x1]	38	1		T4	2		T23	2		T25	5
all_pins[12]	transitions[0x1=>0x0]	25	1		T23	2		T35	1		T62	1
all_pins[13]	values[0x0]	225	1		T4	5		T10	5		T11	2
all_pins[13]	values[0x1]	43	1		T23	2		T24	2		T25	1
all_pins[13]	transitions[0x0=>0x1]	32	1		T23	1		T24	2		T25	1
all_pins[13]	transitions[0x1=>0x0]	49	1		T4	1		T23	2		T24	1
all_pins[14]	values[0x0]	208	1		T4	4		T10	5		T11	2
all_pins[14]	values[0x1]	60	1		T4	1		T23	3		T24	1
all_pins[14]	transitions[0x0=>0x1]	44	1		T4	1		T23	3		T24	1
all_pins[14]	transitions[0x1=>0x0]	40	1		T4	1		T10	1		T24	2
all_pins[15]	values[0x0]	212	1		T4	4		T10	4		T11	2
all_pins[15]	values[0x1]	56	1		T4	1		T10	1		T24	2
all_pins[15]	transitions[0x0=>0x1]	45	1		T4	1		T10	1		T24	2
all_pins[15]	transitions[0x1=>0x0]	30	1		T4	2		T24	1		T35	1
all_pins[16]	values[0x0]	227	1		T4	3		T10	5		T11	2
all_pins[16]	values[0x1]	41	1		T4	2		T24	1		T34	1
all_pins[16]	transitions[0x0=>0x1]	25	1		T4	1		T35	1		T62	2
all_pins[16]	transitions[0x1=>0x0]	49	1		T10	2		T23	4		T24	2