Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=16}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=16}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=16}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	23	0	23	100.00
Crosses	102	0	102	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=16}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	17	0	17	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=16}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	102	0	102	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	196	1		T4	4		T10	4		T23	7
all_values[1]	196	1		T4	4		T10	4		T23	7
all_values[2]	196	1		T4	4		T10	4		T23	7
all_values[3]	196	1		T4	4		T10	4		T23	7
all_values[4]	196	1		T4	4		T10	4		T23	7
all_values[5]	196	1		T4	4		T10	4		T23	7
all_values[6]	196	1		T4	4		T10	4		T23	7
all_values[7]	196	1		T4	4		T10	4		T23	7
all_values[8]	196	1		T4	4		T10	4		T23	7
all_values[9]	196	1		T4	4		T10	4		T23	7
all_values[10]	196	1		T4	4		T10	4		T23	7
all_values[11]	196	1		T4	4		T10	4		T23	7
all_values[12]	196	1		T4	4		T10	4		T23	7
all_values[13]	196	1		T4	4		T10	4		T23	7
all_values[14]	196	1		T4	4		T10	4		T23	7
all_values[15]	196	1		T4	4		T10	4		T23	7
all_values[16]	196	1		T4	4		T10	4		T23	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1836	1		T4	46		T10	41		T23	68
auto[1]	1496	1		T4	22		T10	27		T23	51

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	524	1		T4	17		T10	9		T23	8
auto[1]	2808	1		T4	51		T10	59		T23	111

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1897	1		T4	41		T10	34		T23	66
auto[1]	1435	1		T4	27		T10	34		T23	53

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	102	0	102	100.00
Automatically Generated Cross Bins	102	0	102	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	21	1		T10	1		T24	3		T34	3
all_values[0]	auto[0]	auto[0]	auto[1]	41	1		T4	3		T24	2		T25	1
all_values[0]	auto[0]	auto[1]	auto[0]	9	1		T34	1		T61	3		T69	2
all_values[0]	auto[0]	auto[1]	auto[1]	40	1		T10	1		T23	5		T24	1
all_values[0]	auto[1]	auto[0]	auto[1]	43	1		T4	1		T10	1		T23	1
all_values[0]	auto[1]	auto[1]	auto[1]	42	1		T10	1		T23	1		T24	1
all_values[1]	auto[0]	auto[0]	auto[0]	11	1		T4	1		T23	1		T24	1
all_values[1]	auto[0]	auto[0]	auto[1]	52	1		T10	1		T23	2		T24	2
all_values[1]	auto[0]	auto[1]	auto[0]	7	1		T68	1		T74	1		T75	1
all_values[1]	auto[0]	auto[1]	auto[1]	37	1		T4	1		T25	1		T34	1
all_values[1]	auto[1]	auto[0]	auto[1]	53	1		T4	1		T10	2		T23	2
all_values[1]	auto[1]	auto[1]	auto[1]	36	1		T4	1		T10	1		T23	2
all_values[2]	auto[0]	auto[0]	auto[0]	14	1		T4	1		T25	1		T35	1
all_values[2]	auto[0]	auto[0]	auto[1]	45	1		T4	1		T10	2		T23	1
all_values[2]	auto[0]	auto[1]	auto[0]	15	1		T35	3		T62	1		T68	1
all_values[2]	auto[0]	auto[1]	auto[1]	38	1		T23	1		T24	2		T25	2
all_values[2]	auto[1]	auto[0]	auto[1]	51	1		T4	2		T10	1		T23	3
all_values[2]	auto[1]	auto[1]	auto[1]	33	1		T10	1		T23	2		T25	4
all_values[3]	auto[0]	auto[0]	auto[0]	27	1		T4	3		T24	1		T25	1
all_values[3]	auto[0]	auto[0]	auto[1]	43	1		T10	1		T23	3		T25	4
all_values[3]	auto[0]	auto[1]	auto[0]	19	1		T4	1		T34	1		T62	5
all_values[3]	auto[0]	auto[1]	auto[1]	27	1		T10	1		T23	3		T24	2
all_values[3]	auto[1]	auto[0]	auto[1]	48	1		T10	2		T23	1		T25	1
all_values[3]	auto[1]	auto[1]	auto[1]	32	1		T24	4		T25	1		T34	1
all_values[4]	auto[0]	auto[0]	auto[0]	20	1		T24	2		T35	4		T68	1
all_values[4]	auto[0]	auto[0]	auto[1]	41	1		T4	1		T10	1		T25	3
all_values[4]	auto[0]	auto[1]	auto[0]	6	1		T68	3		T76	2		T72	1
all_values[4]	auto[0]	auto[1]	auto[1]	41	1		T10	1		T23	3		T24	3
all_values[4]	auto[1]	auto[0]	auto[1]	49	1		T4	3		T10	2		T23	3
all_values[4]	auto[1]	auto[1]	auto[1]	39	1		T23	1		T24	2		T25	1
all_values[5]	auto[0]	auto[0]	auto[0]	14	1		T4	2		T23	1		T25	2
all_values[5]	auto[0]	auto[0]	auto[1]	37	1		T10	2		T23	1		T25	1
all_values[5]	auto[0]	auto[1]	auto[0]	7	1		T23	2		T34	1		T77	1
all_values[5]	auto[0]	auto[1]	auto[1]	52	1		T4	1		T23	1		T24	4
all_values[5]	auto[1]	auto[0]	auto[1]	53	1		T10	1		T23	2		T24	1
all_values[5]	auto[1]	auto[1]	auto[1]	33	1		T4	1		T10	1		T24	2
all_values[6]	auto[0]	auto[0]	auto[0]	21	1		T4	1		T24	2		T25	1
all_values[6]	auto[0]	auto[0]	auto[1]	41	1		T4	1		T10	1		T23	2
all_values[6]	auto[0]	auto[1]	auto[0]	10	1		T61	2		T73	2		T77	2
all_values[6]	auto[0]	auto[1]	auto[1]	45	1		T10	1		T23	2		T24	2
all_values[6]	auto[1]	auto[0]	auto[1]	44	1		T4	1		T10	1		T23	3
all_values[6]	auto[1]	auto[1]	auto[1]	35	1		T4	1		T10	1		T25	1
all_values[7]	auto[0]	auto[0]	auto[0]	19	1		T10	2		T34	1		T62	1
all_values[7]	auto[0]	auto[0]	auto[1]	36	1		T4	1		T10	1		T23	1
all_values[7]	auto[0]	auto[1]	auto[0]	12	1		T34	1		T68	1		T69	2
all_values[7]	auto[0]	auto[1]	auto[1]	36	1		T4	1		T23	4		T24	1
all_values[7]	auto[1]	auto[0]	auto[1]	53	1		T4	2		T23	1		T24	2
all_values[7]	auto[1]	auto[1]	auto[1]	40	1		T10	1		T23	1		T24	1
all_values[8]	auto[0]	auto[0]	auto[0]	26	1		T23	1		T25	1		T35	4
all_values[8]	auto[0]	auto[0]	auto[1]	44	1		T23	3		T24	2		T25	1
all_values[8]	auto[0]	auto[1]	auto[0]	9	1		T34	1		T78	2		T79	1
all_values[8]	auto[0]	auto[1]	auto[1]	41	1		T4	1		T10	1		T23	2
all_values[8]	auto[1]	auto[0]	auto[1]	38	1		T4	1		T10	2		T24	1
all_values[8]	auto[1]	auto[1]	auto[1]	38	1		T4	2		T10	1		T23	1
all_values[9]	auto[0]	auto[0]	auto[0]	22	1		T24	1		T62	1		T68	1
all_values[9]	auto[0]	auto[0]	auto[1]	49	1		T4	1		T10	1		T23	4
all_values[9]	auto[0]	auto[1]	auto[0]	13	1		T24	1		T34	2		T73	4
all_values[9]	auto[0]	auto[1]	auto[1]	35	1		T4	1		T10	1		T23	1
all_values[9]	auto[1]	auto[0]	auto[1]	34	1		T4	1		T10	1		T23	2
all_values[9]	auto[1]	auto[1]	auto[1]	43	1		T4	1		T10	1		T24	3
all_values[10]	auto[0]	auto[0]	auto[0]	24	1		T10	1		T23	1		T24	4
all_values[10]	auto[0]	auto[0]	auto[1]	30	1		T4	1		T25	1		T34	1
all_values[10]	auto[0]	auto[1]	auto[0]	9	1		T24	3		T68	1		T77	1
all_values[10]	auto[0]	auto[1]	auto[1]	45	1		T4	2		T10	1		T23	2
all_values[10]	auto[1]	auto[0]	auto[1]	57	1		T4	1		T10	1		T23	3
all_values[10]	auto[1]	auto[1]	auto[1]	31	1		T10	1		T23	1		T25	1
all_values[11]	auto[0]	auto[0]	auto[0]	23	1		T4	2		T23	1		T25	1
all_values[11]	auto[0]	auto[0]	auto[1]	35	1		T4	1		T23	1		T24	2
all_values[11]	auto[0]	auto[1]	auto[0]	14	1		T25	1		T61	2		T73	2
all_values[11]	auto[0]	auto[1]	auto[1]	41	1		T10	1		T23	1		T24	1
all_values[11]	auto[1]	auto[0]	auto[1]	46	1		T4	1		T10	2		T23	3
all_values[11]	auto[1]	auto[1]	auto[1]	37	1		T10	1		T23	1		T24	2
all_values[12]	auto[0]	auto[0]	auto[0]	17	1		T4	2		T23	1		T24	1
all_values[12]	auto[0]	auto[0]	auto[1]	39	1		T10	1		T23	1		T35	1
all_values[12]	auto[0]	auto[1]	auto[0]	9	1		T68	2		T61	1		T70	1
all_values[12]	auto[0]	auto[1]	auto[1]	42	1		T4	1		T23	4		T24	3
all_values[12]	auto[1]	auto[0]	auto[1]	43	1		T10	1		T24	1		T25	2
all_values[12]	auto[1]	auto[1]	auto[1]	46	1		T4	1		T10	2		T23	1
all_values[13]	auto[0]	auto[0]	auto[0]	36	1		T4	1		T10	2		T24	4
all_values[13]	auto[0]	auto[0]	auto[1]	37	1		T4	1		T23	2		T25	1
all_values[13]	auto[0]	auto[1]	auto[0]	19	1		T4	1		T10	2		T24	1
all_values[13]	auto[0]	auto[1]	auto[1]	30	1		T23	1		T24	1		T62	1
all_values[13]	auto[1]	auto[0]	auto[1]	43	1		T4	1		T23	3		T25	3
all_values[13]	auto[1]	auto[1]	auto[1]	31	1		T23	1		T24	1		T25	2
all_values[14]	auto[0]	auto[0]	auto[0]	15	1		T4	1		T10	1		T24	1
all_values[14]	auto[0]	auto[0]	auto[1]	38	1		T4	2		T10	1		T24	2
all_values[14]	auto[0]	auto[1]	auto[0]	11	1		T80	1		T79	4		T72	1
all_values[14]	auto[0]	auto[1]	auto[1]	34	1		T10	1		T23	2		T24	1
all_values[14]	auto[1]	auto[0]	auto[1]	49	1		T4	1		T23	3		T25	5
all_values[14]	auto[1]	auto[1]	auto[1]	49	1		T10	1		T23	2		T24	3
all_values[15]	auto[0]	auto[0]	auto[0]	13	1		T24	1		T81	2		T69	4
all_values[15]	auto[0]	auto[0]	auto[1]	38	1		T23	2		T25	1		T35	1
all_values[15]	auto[0]	auto[1]	auto[0]	2	1		T71	1		T72	1		-	-
all_values[15]	auto[0]	auto[1]	auto[1]	50	1		T4	2		T10	2		T24	1
all_values[15]	auto[1]	auto[0]	auto[1]	52	1		T4	1		T10	2		T23	4
all_values[15]	auto[1]	auto[1]	auto[1]	41	1		T4	1		T23	1		T24	2
all_values[16]	auto[0]	auto[0]	auto[0]	24	1		T4	1		T25	2		T68	1
all_values[16]	auto[0]	auto[0]	auto[1]	47	1		T10	1		T23	1		T24	3
all_values[16]	auto[0]	auto[1]	auto[0]	6	1		T73	4		T69	1		T80	1
all_values[16]	auto[0]	auto[1]	auto[1]	46	1		T4	1		T10	1		T23	2
all_values[16]	auto[1]	auto[0]	auto[1]	40	1		T4	1		T10	2		T23	4
all_values[16]	auto[1]	auto[1]	auto[1]	33	1		T4	1		T24	1		T34	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal