Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	42339	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	53050	1		T1	2		T2	1		T3	1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	57188	1		T1	2		T2	2		T3	2
values[0x0]	18917	1		T2	1		T4	1		T6	17
values[0x1]	19284	1		T1	1		T3	1		T5	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	30036	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	65353	1		T1	2		T2	2		T3	2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	341	1		T7	4		T8	19		T9	3
valid_sources[0x01]	624	1		T7	7		T8	10		T10	6
valid_sources[0x02]	214	1		T7	4		T8	1		T9	4
valid_sources[0x03]	262	1		T7	8		T8	10		T11	1
valid_sources[0x04]	464	1		T6	94		T7	11		T8	13
valid_sources[0x05]	264	1		T7	9		T8	19		T11	3
valid_sources[0x06]	550	1		T1	1		T7	9		T8	18
valid_sources[0x07]	246	1		T7	11		T8	3		T29	1
valid_sources[0x08]	351	1		T7	10		T8	39		T10	13
valid_sources[0x09]	298	1		T7	6		T8	20		T10	12
valid_sources[0x0a]	274	1		T7	7		T8	17		T11	1
valid_sources[0x0b]	376	1		T7	11		T8	10		T29	4
valid_sources[0x0c]	268	1		T7	9		T8	5		T29	3
valid_sources[0x0d]	278	1		T7	8		T8	15		T11	1
valid_sources[0x0e]	306	1		T7	3		T8	14		T10	7
valid_sources[0x0f]	328	1		T7	7		T8	11		T11	3
valid_sources[0x10]	224	1		T7	10		T8	6		T9	3
valid_sources[0x11]	308	1		T7	5		T8	16		T10	14
valid_sources[0x12]	454	1		T7	14		T8	8		T11	1
valid_sources[0x13]	426	1		T5	1		T7	11		T8	4
valid_sources[0x14]	417	1		T7	9		T8	10		T9	3
valid_sources[0x15]	312	1		T7	6		T8	2		T11	1
valid_sources[0x16]	292	1		T7	6		T8	10		T29	1
valid_sources[0x17]	280	1		T7	13		T8	15		T29	1
valid_sources[0x18]	311	1		T7	15		T8	14		T31	2
valid_sources[0x19]	395	1		T7	14		T8	33		T11	1
valid_sources[0x1a]	264	1		T7	15		T8	30		T11	2
valid_sources[0x1b]	255	1		T7	8		T8	2		T9	3
valid_sources[0x1c]	403	1		T7	10		T8	24		T11	2
valid_sources[0x1d]	288	1		T7	13		T8	5		T29	2
valid_sources[0x1e]	258	1		T7	7		T8	2		T31	3
valid_sources[0x1f]	505	1		T7	8		T8	7		T10	3
valid_sources[0x20]	362	1		T7	7		T8	27		T13	3
valid_sources[0x21]	406	1		T7	10		T8	31		T11	1
valid_sources[0x22]	261	1		T7	4		T8	5		T29	1
valid_sources[0x23]	2072	1		T7	9		T8	17		T9	1
valid_sources[0x24]	201	1		T7	6		T8	5		T11	1
valid_sources[0x25]	455	1		T7	13		T8	3		T11	3
valid_sources[0x26]	446	1		T7	9		T8	7		T10	11
valid_sources[0x27]	305	1		T7	10		T8	1		T9	3
valid_sources[0x28]	301	1		T7	6		T8	20		T10	6
valid_sources[0x29]	420	1		T7	6		T8	25		T11	1
valid_sources[0x2a]	455	1		T7	8		T8	16		T11	1
valid_sources[0x2b]	244	1		T7	10		T8	5		T23	7
valid_sources[0x2c]	474	1		T7	4		T8	29		T11	1
valid_sources[0x2d]	304	1		T7	7		T8	11		T11	2
valid_sources[0x2e]	330	1		T7	8		T8	4		T13	1
valid_sources[0x2f]	297	1		T7	18		T8	8		T9	2
valid_sources[0x30]	359	1		T7	2		T8	10		T10	5
valid_sources[0x31]	371	1		T7	11		T8	6		T9	3
valid_sources[0x32]	657	1		T7	7		T8	10		T11	2
valid_sources[0x33]	354	1		T7	4		T8	13		T11	1
valid_sources[0x34]	273	1		T7	8		T8	9		T9	8
valid_sources[0x35]	300	1		T7	7		T8	14		T10	5
valid_sources[0x36]	309	1		T7	8		T8	3		T11	3
valid_sources[0x37]	467	1		T7	13		T8	15		T11	1
valid_sources[0x38]	289	1		T7	10		T8	8		T11	2
valid_sources[0x39]	215	1		T3	1		T7	7		T8	17
valid_sources[0x3a]	218	1		T7	14		T8	4		T29	1
valid_sources[0x3b]	293	1		T7	12		T8	7		T13	1
valid_sources[0x3c]	330	1		T7	5		T8	15		T11	2
valid_sources[0x3d]	564	1		T4	1		T7	8		T8	12
valid_sources[0x3e]	348	1		T7	11		T8	21		T10	1
valid_sources[0x3f]	305	1		T7	4		T8	9		T9	1
valid_sources[0x40]	319	1		T7	5		T8	22		T29	1
valid_sources[0x41]	461	1		T7	6		T8	25		T12	1
valid_sources[0x42]	377	1		T7	10		T8	15		T13	4
valid_sources[0x43]	527	1		T7	6		T8	22		T9	2
valid_sources[0x44]	568	1		T7	5		T8	15		T29	3
valid_sources[0x45]	299	1		T7	8		T8	11		T9	3
valid_sources[0x46]	605	1		T7	3		T8	6		T29	4
valid_sources[0x47]	417	1		T7	11		T8	24		T11	2
valid_sources[0x48]	566	1		T7	10		T8	15		T9	1
valid_sources[0x49]	297	1		T7	8		T8	12		T11	1
valid_sources[0x4a]	277	1		T7	7		T8	14		T11	2
valid_sources[0x4b]	533	1		T7	15		T8	21		T11	1
valid_sources[0x4c]	270	1		T7	3		T8	7		T11	1
valid_sources[0x4d]	373	1		T7	11		T8	23		T11	1
valid_sources[0x4e]	338	1		T7	6		T8	9		T11	1
valid_sources[0x4f]	221	1		T3	1		T7	6		T8	27
valid_sources[0x50]	321	1		T7	7		T8	10		T11	1
valid_sources[0x51]	490	1		T7	10		T8	32		T12	1
valid_sources[0x52]	555	1		T7	9		T8	6		T11	1
valid_sources[0x53]	544	1		T7	7		T8	24		T9	9
valid_sources[0x54]	223	1		T7	10		T8	24		T11	2
valid_sources[0x55]	341	1		T7	13		T8	16		T9	9
valid_sources[0x56]	405	1		T7	4		T8	7		T10	3
valid_sources[0x57]	320	1		T7	10		T8	4		T29	1
valid_sources[0x58]	376	1		T7	6		T8	18		T35	10
valid_sources[0x59]	622	1		T7	7		T8	5		T9	1
valid_sources[0x5a]	335	1		T7	14		T8	18		T11	1
valid_sources[0x5b]	346	1		T5	1		T7	9		T8	3
valid_sources[0x5c]	254	1		T7	11		T8	22		T9	1
valid_sources[0x5d]	441	1		T7	8		T8	20		T10	7
valid_sources[0x5e]	290	1		T7	5		T8	19		T10	3
valid_sources[0x5f]	418	1		T7	15		T8	17		T10	1
valid_sources[0x60]	314	1		T7	15		T8	30		T29	2
valid_sources[0x61]	463	1		T7	18		T8	8		T9	2
valid_sources[0x62]	293	1		T7	9		T8	32		T11	3
valid_sources[0x63]	283	1		T7	8		T8	16		T11	2
valid_sources[0x64]	304	1		T7	7		T8	11		T11	3
valid_sources[0x65]	496	1		T7	4		T8	14		T11	1
valid_sources[0x66]	436	1		T7	6		T8	21		T29	1
valid_sources[0x67]	574	1		T6	93		T7	13		T8	13
valid_sources[0x68]	495	1		T7	11		T8	13		T11	3
valid_sources[0x69]	322	1		T7	11		T8	1		T11	5
valid_sources[0x6a]	339	1		T7	11		T8	11		T29	1
valid_sources[0x6b]	277	1		T7	12		T8	24		T11	1
valid_sources[0x6c]	290	1		T7	8		T8	4		T13	1
valid_sources[0x6d]	285	1		T7	15		T8	5		T11	6
valid_sources[0x6e]	372	1		T7	10		T8	27		T11	5
valid_sources[0x6f]	218	1		T7	13		T8	9		T29	1
valid_sources[0x70]	368	1		T7	14		T8	12		T11	1
valid_sources[0x71]	267	1		T7	3		T8	22		T11	8
valid_sources[0x72]	297	1		T7	7		T8	6		T29	2
valid_sources[0x73]	264	1		T7	12		T8	14		T29	2
valid_sources[0x74]	275	1		T7	9		T8	13		T11	1
valid_sources[0x75]	434	1		T7	8		T8	16		T35	7
valid_sources[0x76]	314	1		T7	7		T8	19		T9	8
valid_sources[0x77]	339	1		T3	1		T7	10		T8	9
valid_sources[0x78]	298	1		T7	5		T8	6		T11	3
valid_sources[0x79]	306	1		T7	6		T8	6		T31	2
valid_sources[0x7a]	484	1		T7	7		T8	8		T9	2
valid_sources[0x7b]	321	1		T7	8		T8	12		T10	10
valid_sources[0x7c]	464	1		T7	12		T8	9		T11	8
valid_sources[0x7d]	353	1		T7	8		T8	7		T11	1
valid_sources[0x7e]	293	1		T7	16		T8	18		T29	2
valid_sources[0x7f]	347	1		T7	4		T8	23		T29	1
valid_sources[0x80]	399	1		T7	5		T8	5		T13	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

21885

1

T1

1

T4

1

T5

1

values[0x0]

all_enables

biggest_size

16451

1

T2

1

T4

1

T6

14

values[0x1]

all_enables

biggest_size

14714

1

T1

1

T3

1

T6

7