Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	54180	1		T1	1		T2	2		T3	2
full_word	53969	1		T1	2		T2	1		T3	1

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	107989	1		T1	3		T2	3		T3	3
auto[TlIntgErrCmd]	63	1		T8	7		T44	2		T42	5
auto[TlIntgErrData]	48	1		T8	6		T44	4		T42	3
auto[TlIntgErrBoth]	49	1		T8	7		T44	4		T42	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	58881	1		T1	2		T2	2		T3	2
auto[1]	49268	1		T1	1		T2	1		T3	1

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER
[auto[TlIntgErrBoth]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	36739	1		T1	1		T2	2		T3	2
auto[TlIntgErrNone]	partial	auto[1]	17291	1		T5	1		T6	12		T7	19
auto[TlIntgErrNone]	full_word	auto[0]	22073	1		T1	1		T4	1		T5	1
auto[TlIntgErrNone]	full_word	auto[1]	31886	1		T1	1		T2	1		T3	1
auto[TlIntgErrCmd]	partial	auto[0]	27	1		T8	2		T44	1		T42	2
auto[TlIntgErrCmd]	partial	auto[1]	31	1		T8	4		T44	1		T42	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T39	1		T73	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1		T8	1		T39	1		T74	1
auto[TlIntgErrData]	partial	auto[0]	19	1		T8	1		T44	3		T42	1
auto[TlIntgErrData]	partial	auto[1]	26	1		T8	5		T44	1		T42	2
auto[TlIntgErrData]	full_word	auto[0]	2	1		T39	1		T75	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	1	1		T76	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	19	1		T8	1		T44	1		T42	1
auto[TlIntgErrBoth]	partial	auto[1]	28	1		T8	6		T44	3		T42	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1		T77	1		T76	1		-	-