Unified Coverage Report :: Module :: prim_ram_2p_async

Module : prim_ram_2p_async_adv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
77.45	76.47	33.33			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_ram_2p_async_adv_0.1/rtl/prim_ram_2p_async_adv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_no_stubbed_memory.u_memory_2p.i_prim_ram_2p_async_adv	77.45	76.47	33.33			100.00	100.00

Module Instance : tb.dut.gen_no_stubbed_memory.u_memory_2p.i_prim_ram_2p_async_adv

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
77.45	76.47	33.33			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
41.00	59.57	33.33			60.00	11.11

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_no_stubbed_memory.u_memory_2p

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_mem	16.24	15.38				33.33	0.00

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_ram_2p_async_adv

	Line No.	Total	Covered	Percent
TOTAL		34	26	76.47
ALWAYS	136	3	3	100.00
ALWAYS	143	3	3	100.00
CONT_ASSIGN	150	1	0	0.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	154	1	0	0.00
CONT_ASSIGN	155	0	0
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	0	0.00
CONT_ASSIGN	162	0	0
CONT_ASSIGN	257	0	0
CONT_ASSIGN	258	0	0
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	261	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	307	1	0	0.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	309	1	1	100.00
CONT_ASSIGN	310	1	1	100.00
CONT_ASSIGN	311	0	0
CONT_ASSIGN	313	1	1	100.00
CONT_ASSIGN	314	1	1	100.00
CONT_ASSIGN	315	1	1	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	317	0	0
CONT_ASSIGN	347	1	1	100.00
CONT_ASSIGN	348	1	0	0.00
CONT_ASSIGN	350	0	0
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	353	1	0	0.00
CONT_ASSIGN	355	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_ram_2p_async_adv_0.1/rtl/prim_ram_2p_async_adv.sv' or '../src/lowrisc_prim_ram_2p_async_adv_0.1/rtl/prim_ram_2p_async_adv.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
150	0	1
151	1	1
152	1	1
153	1	1
154	0	1
155		unreachable
157	1	1
158	1	1
159	1	1
160	1	1
161	0	1
162		unreachable
257		unreachable
258		unreachable
259	1	1
260	1	1
261	0	1
262	0	1
267	1	1
268	1	1
307	0	1
308	1	1
309	1	1
310	1	1
311		unreachable
313	1	1
314	1	1
315	1	1
316	1	1
317		unreachable
347	1	1
348	0	1
350		unreachable
352	1	1
353	0	1
355		unreachable

Cond Coverage for Module : prim_ram_2p_async_adv

	Total	Covered	Percent
Conditions	6	2	33.33
Logical	6	2	33.33
Non-Logical	0	0
Event	0	0

 LINE       139
 EXPRESSION (a_req_q & ((~a_write_q)))
             ---1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       146
 EXPRESSION (b_req_q & ((~b_write_q)))
             ---1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

Branch Coverage for Module : prim_ram_2p_async_adv

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	136	2	2	100.00
IF	143	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_ram_2p_async_adv_0.1/rtl/prim_ram_2p_async_adv.sv' or '../src/lowrisc_prim_ram_2p_async_adv_0.1/rtl/prim_ram_2p_async_adv.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	136	if ((!rst_a_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	143	if ((!rst_b_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Module : prim_ram_2p_async_adv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CannotHaveEccAndParity_A	5	5	0	0

CannotHaveEccAndParity_A

Name	Attempts	Real Successes
Total	5	5
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1