Module Definition
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Module Instance : tb.dut.u_reg.u_wake_events_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
58.33 100.00 33.33 100.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
58.33 100.00 33.33 100.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
57.45 82.35 30.77 66.67 50.00 u_wake_events_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wake_control_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_wake_control_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wake_control_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
66.67 33.33 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00

Line Coverage for Module : prim_pulse_sync
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Module : prim_pulse_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT6,T7,T8
10CoveredT6,T7,T8
11CoveredT7,T10,T29

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT6,T7,T8
10CoveredT7,T10,T29
11CoveredT6,T7,T8

Branch Coverage for Module : prim_pulse_sync
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : prim_pulse_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1217673 1475 0 0
SrcPulseCheck_M 1745865 1479 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1217673 1475 0 0
T6 3414 2 0 0
T7 17027 4 0 0
T8 16889 36 0 0
T9 2572 2 0 0
T10 5249 4 0 0
T16 2983 4 0 0
T23 4418 28 0 0
T29 3821 4 0 0
T30 3402 12 0 0
T35 3051 2 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1745865 1479 0 0
T6 3414 2 0 0
T7 17027 4 0 0
T8 16889 36 0 0
T9 2572 2 0 0
T10 5249 4 0 0
T16 2983 4 0 0
T23 4418 28 0 0
T29 3821 4 0 0
T30 3402 12 0 0
T35 3051 2 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions6233.33
Logical6233.33
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Not Covered
11Unreachable

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered
11Not Covered

Branch Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 0 0.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 0 0.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 229827 0 0 0
SrcPulseCheck_M 758019 0 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 229827 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 758019 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT6,T7,T8
10CoveredT6,T7,T8
11CoveredT7,T10,T29

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT6,T7,T8
10CoveredT7,T10,T29
11CoveredT6,T7,T8

Branch Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 229827 737 0 0
SrcPulseCheck_M 758019 741 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 229827 737 0 0
T6 320 1 0 0
T7 1309 2 0 0
T8 4605 18 0 0
T9 701 1 0 0
T10 1597 2 0 0
T16 779 2 0 0
T23 1344 14 0 0
T29 862 2 0 0
T30 199 6 0 0
T35 178 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 758019 741 0 0
T6 3094 1 0 0
T7 15718 2 0 0
T8 12284 18 0 0
T9 1871 1 0 0
T10 3652 2 0 0
T16 2204 2 0 0
T23 3074 14 0 0
T29 2959 2 0 0
T30 3203 6 0 0
T35 2873 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT6,T7,T8
10CoveredT6,T7,T8
11CoveredT7,T10,T29

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT6,T7,T8
10CoveredT7,T10,T29
11CoveredT6,T7,T8

Branch Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 758019 738 0 0
SrcPulseCheck_M 229827 738 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 758019 738 0 0
T6 3094 1 0 0
T7 15718 2 0 0
T8 12284 18 0 0
T9 1871 1 0 0
T10 3652 2 0 0
T16 2204 2 0 0
T23 3074 14 0 0
T29 2959 2 0 0
T30 3203 6 0 0
T35 2873 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 229827 738 0 0
T6 320 1 0 0
T7 1309 2 0 0
T8 4605 18 0 0
T9 701 1 0 0
T10 1597 2 0 0
T16 779 2 0 0
T23 1344 14 0 0
T29 862 2 0 0
T30 199 6 0 0
T35 178 1 0 0

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