Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	25627	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	37510	1		T1	2		T2	2		T3	15

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36821	1		T1	2		T2	2		T3	11
values[0x0]	12751	1		T2	1		T3	6		T4	160
values[0x1]	13565	1		T1	1		T3	5		T4	157

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	17825	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	45312	1		T1	2		T2	2		T3	19

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	382	1		T4	22		T6	2		T25	128
valid_sources[0x01]	206	1		T4	20		T22	15		T55	7
valid_sources[0x02]	176	1		T6	10		T54	5		T23	8
valid_sources[0x03]	123	1		T6	10		T7	2		T54	7
valid_sources[0x04]	609	1		T5	11		T25	128		T55	5
valid_sources[0x05]	241	1		T6	3		T7	1		T22	6
valid_sources[0x06]	118	1		T6	2		T12	6		T42	1
valid_sources[0x07]	158	1		T6	17		T54	2		T55	1
valid_sources[0x08]	130	1		T6	4		T7	2		T9	2
valid_sources[0x09]	159	1		T6	5		T55	2		T56	3
valid_sources[0x0a]	260	1		T4	1		T5	78		T6	10
valid_sources[0x0b]	134	1		T6	1		T10	5		T12	6
valid_sources[0x0c]	212	1		T6	15		T22	4		T54	2
valid_sources[0x0d]	231	1		T6	19		T22	36		T54	2
valid_sources[0x0e]	208	1		T7	2		T54	1		T12	5
valid_sources[0x0f]	177	1		T9	1		T55	5		T12	11
valid_sources[0x10]	440	1		T6	4		T25	256		T55	5
valid_sources[0x11]	186	1		T5	6		T6	5		T55	29
valid_sources[0x12]	174	1		T3	2		T8	5		T9	1
valid_sources[0x13]	304	1		T4	1		T10	1		T25	128
valid_sources[0x14]	373	1		T6	7		T54	3		T55	6
valid_sources[0x15]	218	1		T6	5		T55	24		T12	25
valid_sources[0x16]	226	1		T4	36		T5	9		T6	4
valid_sources[0x17]	131	1		T1	1		T6	1		T9	1
valid_sources[0x18]	136	1		T6	1		T7	2		T9	1
valid_sources[0x19]	155	1		T4	16		T6	1		T7	2
valid_sources[0x1a]	181	1		T6	8		T9	1		T54	8
valid_sources[0x1b]	226	1		T6	21		T9	1		T22	29
valid_sources[0x1c]	144	1		T6	12		T22	11		T12	3
valid_sources[0x1d]	359	1		T6	11		T8	34		T25	128
valid_sources[0x1e]	195	1		T6	7		T7	5		T10	9
valid_sources[0x1f]	231	1		T5	1		T6	7		T8	36
valid_sources[0x20]	132	1		T6	11		T55	3		T12	3
valid_sources[0x21]	235	1		T5	10		T6	3		T55	2
valid_sources[0x22]	567	1		T6	2		T55	5		T12	1
valid_sources[0x23]	265	1		T4	6		T6	5		T9	1
valid_sources[0x24]	240	1		T5	17		T6	7		T55	6
valid_sources[0x25]	141	1		T6	2		T12	6		T42	2
valid_sources[0x26]	178	1		T6	19		T10	23		T22	8
valid_sources[0x27]	176	1		T54	7		T12	3		T42	3
valid_sources[0x28]	276	1		T6	6		T9	1		T25	128
valid_sources[0x29]	176	1		T8	8		T9	1		T22	7
valid_sources[0x2a]	332	1		T6	5		T10	16		T25	128
valid_sources[0x2b]	298	1		T4	23		T6	13		T10	11
valid_sources[0x2c]	243	1		T5	12		T6	12		T54	1
valid_sources[0x2d]	176	1		T6	2		T9	3		T12	2
valid_sources[0x2e]	186	1		T4	6		T22	25		T54	4
valid_sources[0x2f]	306	1		T25	128		T27	1		T54	1
valid_sources[0x30]	276	1		T5	21		T9	3		T12	13
valid_sources[0x31]	190	1		T4	15		T6	2		T56	7
valid_sources[0x32]	280	1		T12	11		T56	1		T42	4
valid_sources[0x33]	226	1		T4	1		T6	2		T22	21
valid_sources[0x34]	256	1		T5	17		T6	7		T10	9
valid_sources[0x35]	152	1		T55	8		T12	16		T56	6
valid_sources[0x36]	173	1		T6	2		T54	1		T56	8
valid_sources[0x37]	689	1		T6	4		T8	3		T54	13
valid_sources[0x38]	165	1		T4	7		T12	5		T56	1
valid_sources[0x39]	375	1		T6	9		T10	4		T54	4
valid_sources[0x3a]	183	1		T6	27		T55	13		T42	2
valid_sources[0x3b]	180	1		T6	14		T7	2		T54	2
valid_sources[0x3c]	178	1		T6	10		T10	4		T23	2
valid_sources[0x3d]	161	1		T4	4		T54	5		T12	12
valid_sources[0x3e]	137	1		T5	7		T12	10		T56	2
valid_sources[0x3f]	147	1		T6	6		T7	12		T27	1
valid_sources[0x40]	252	1		T6	3		T10	11		T54	3
valid_sources[0x41]	163	1		T6	4		T7	10		T55	1
valid_sources[0x42]	289	1		T6	7		T25	128		T55	4
valid_sources[0x43]	204	1		T5	56		T6	11		T55	1
valid_sources[0x44]	305	1		T6	3		T7	19		T10	3
valid_sources[0x45]	239	1		T6	5		T11	16		T12	1
valid_sources[0x46]	248	1		T4	17		T6	2		T10	35
valid_sources[0x47]	238	1		T4	5		T5	4		T6	17
valid_sources[0x48]	202	1		T27	1		T22	9		T54	2
valid_sources[0x49]	138	1		T4	2		T6	5		T9	2
valid_sources[0x4a]	157	1		T5	24		T6	2		T22	7
valid_sources[0x4b]	249	1		T6	9		T27	1		T55	2
valid_sources[0x4c]	163	1		T27	1		T55	3		T12	5
valid_sources[0x4d]	130	1		T6	4		T7	3		T54	1
valid_sources[0x4e]	148	1		T6	5		T10	11		T54	5
valid_sources[0x4f]	394	1		T6	1		T23	2		T55	17
valid_sources[0x50]	199	1		T23	1		T12	9		T42	2
valid_sources[0x51]	181	1		T4	38		T6	1		T22	3
valid_sources[0x52]	152	1		T6	2		T9	1		T55	9
valid_sources[0x53]	146	1		T6	1		T8	23		T12	1
valid_sources[0x54]	269	1		T5	2		T6	5		T25	124
valid_sources[0x55]	262	1		T4	1		T9	1		T54	1
valid_sources[0x56]	198	1		T5	24		T6	3		T55	17
valid_sources[0x57]	177	1		T5	6		T54	2		T12	4
valid_sources[0x58]	260	1		T6	2		T9	2		T22	1
valid_sources[0x59]	369	1		T4	15		T6	1		T23	3
valid_sources[0x5a]	198	1		T6	1		T7	3		T12	4
valid_sources[0x5b]	235	1		T4	15		T27	1		T55	2
valid_sources[0x5c]	149	1		T6	6		T55	5		T12	2
valid_sources[0x5d]	398	1		T7	20		T8	17		T10	8
valid_sources[0x5e]	134	1		T5	2		T6	4		T54	2
valid_sources[0x5f]	156	1		T6	10		T10	3		T55	4
valid_sources[0x60]	160	1		T5	8		T6	5		T10	12
valid_sources[0x61]	142	1		T4	16		T7	1		T12	8
valid_sources[0x62]	140	1		T4	2		T6	10		T56	2
valid_sources[0x63]	126	1		T4	1		T6	18		T54	5
valid_sources[0x64]	163	1		T6	2		T9	1		T55	4
valid_sources[0x65]	222	1		T5	25		T6	1		T54	14
valid_sources[0x66]	330	1		T6	1		T9	1		T25	128
valid_sources[0x67]	170	1		T9	1		T27	1		T55	6
valid_sources[0x68]	111	1		T6	7		T10	5		T12	1
valid_sources[0x69]	1848	1		T5	2		T6	1		T12	25
valid_sources[0x6a]	158	1		T4	6		T6	11		T22	4
valid_sources[0x6b]	204	1		T6	14		T7	3		T54	4
valid_sources[0x6c]	157	1		T5	1		T6	22		T23	7
valid_sources[0x6d]	411	1		T5	12		T6	2		T25	256
valid_sources[0x6e]	251	1		T6	2		T56	5		T20	2
valid_sources[0x6f]	133	1		T7	2		T54	3		T23	5
valid_sources[0x70]	199	1		T7	10		T54	1		T12	2
valid_sources[0x71]	342	1		T6	5		T9	1		T25	128
valid_sources[0x72]	337	1		T5	1		T6	6		T9	1
valid_sources[0x73]	204	1		T4	10		T5	3		T6	6
valid_sources[0x74]	172	1		T5	2		T6	7		T54	1
valid_sources[0x75]	245	1		T6	4		T10	18		T54	6
valid_sources[0x76]	154	1		T4	13		T6	3		T29	8
valid_sources[0x77]	112	1		T54	5		T12	4		T42	2
valid_sources[0x78]	267	1		T6	5		T9	1		T55	4
valid_sources[0x79]	177	1		T4	4		T6	21		T54	1
valid_sources[0x7a]	353	1		T6	7		T9	1		T25	128
valid_sources[0x7b]	177	1		T6	10		T55	6		T12	11
valid_sources[0x7c]	304	1		T6	2		T10	8		T25	128
valid_sources[0x7d]	352	1		T5	1		T6	9		T9	2
valid_sources[0x7e]	254	1		T6	15		T10	56		T54	5
valid_sources[0x7f]	266	1		T6	11		T25	128		T12	3
valid_sources[0x80]	205	1		T4	3		T6	7		T55	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

14892

1

T1

1

T2

1

T3

6

values[0x0]

all_enables

biggest_size

11613

1

T2

1

T3

6

T4

160

values[0x1]

all_enables

biggest_size

11005

1

T1

1

T3

3

T4

157