Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	38526	1		T1	1		T2	1		T3	7
full_word	38461	1		T1	2		T2	2		T3	15

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	76887	1		T1	3		T2	3		T3	22
auto[TlIntgErrCmd]	34	1		T6	3		T32	3		T33	4
auto[TlIntgErrData]	36	1		T6	5		T32	1		T33	3
auto[TlIntgErrBoth]	30	1		T6	2		T32	6		T33	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	38597	1		T1	2		T2	2		T3	11
auto[1]	38390	1		T1	1		T2	1		T3	11

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER
[auto[TlIntgErrData]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	23497	1		T1	1		T2	1		T3	5
auto[TlIntgErrNone]	partial	auto[1]	14937	1		T3	2		T5	1035		T6	92
auto[TlIntgErrNone]	full_word	auto[0]	15058	1		T1	1		T2	1		T3	6
auto[TlIntgErrNone]	full_word	auto[1]	23395	1		T1	1		T2	1		T3	9
auto[TlIntgErrCmd]	partial	auto[0]	10	1		T6	1		T32	1		T41	5
auto[TlIntgErrCmd]	partial	auto[1]	21	1		T6	2		T32	2		T33	3
auto[TlIntgErrCmd]	full_word	auto[0]	1	1		T33	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	2	1		T41	1		T70	1		-	-
auto[TlIntgErrData]	partial	auto[0]	20	1		T6	3		T33	2		T41	4
auto[TlIntgErrData]	partial	auto[1]	14	1		T6	2		T32	1		T33	1
auto[TlIntgErrData]	full_word	auto[1]	2	1		T71	2		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	9	1		T32	1		T41	3		T71	3
auto[TlIntgErrBoth]	partial	auto[1]	18	1		T6	2		T32	5		T33	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T33	1		T41	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	1	1		T41	1		-	-		-	-