Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
72.77	83.19	35.82	89.69		55.17	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	593410	11042	0	0
ep_in_enable_rd_A	593410	1499	0	0
ep_out_enable_rd_A	593410	1255	0	0
in_iso_rd_A	593410	1092	0	0
intr_enable_rd_A	593410	1866	0	0
out_iso_rd_A	593410	1133	0	0
phy_config_rd_A	593410	780	0	0
phy_pins_drive_rd_A	593410	1264	0	0
rxenable_setup_rd_A	593410	1281	0	0
set_nak_out_rd_A	593410	1160	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593410	11042	0	0
T5	15912	1123	0	0
T6	23737	1	0	0
T7	11123	697	0	0
T10	4367	1009	0	0
T11	1691	2	0	0
T13	2070	5	0	0
T14	0	319	0	0
T15	0	570	0	0
T18	8098	0	0	0
T19	1843	0	0	0
T20	1474	0	0	0
T21	3721	0	0	0
T32	0	3	0	0
T33	0	2	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593410	1499	0	0
T6	23737	303	0	0
T22	4912	28	0	0
T31	1603	0	0	0
T35	4279	0	0	0
T40	21449	323	0	0
T43	7895	0	0	0
T44	2097	0	0	0
T45	3463	4	0	0
T52	0	1	0	0
T58	4417	30	0	0
T59	0	36	0	0
T60	0	25	0	0
T61	0	2	0	0
T62	0	9	0	0
T63	1780	0	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593410	1255	0	0
T5	15912	2	0	0
T6	23737	202	0	0
T22	4912	17	0	0
T31	1603	0	0	0
T35	4279	0	0	0
T40	21449	322	0	0
T43	7895	0	0	0
T44	2097	0	0	0
T45	0	1	0	0
T58	4417	52	0	0
T59	0	20	0	0
T60	0	6	0	0
T61	0	6	0	0
T63	1780	0	0	0
T64	0	3	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593410	1092	0	0
T6	23737	237	0	0
T22	4912	38	0	0
T31	1603	0	0	0
T35	4279	0	0	0
T40	21449	182	0	0
T43	7895	0	0	0
T44	2097	0	0	0
T45	0	1	0	0
T58	4417	5	0	0
T59	0	13	0	0
T60	0	33	0	0
T61	0	4	0	0
T63	1780	0	0	0
T64	0	15	0	0
T65	1185	7	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593410	1866	0	0
T3	1405	5	0	0
T6	23737	387	0	0
T14	2275	0	0	0
T15	10997	0	0	0
T22	4912	34	0	0
T28	2800	15	0	0
T32	13651	0	0	0
T37	2119	0	0	0
T38	3980	0	0	0
T39	12068	0	0	0
T40	0	358	0	0
T45	0	49	0	0
T58	0	24	0	0
T65	0	7	0	0
T66	0	21	0	0
T67	0	23	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593410	1133	0	0
T6	23737	225	0	0
T22	4912	28	0	0
T31	1603	0	0	0
T35	4279	0	0	0
T40	21449	232	0	0
T43	7895	0	0	0
T44	2097	0	0	0
T52	0	1	0	0
T58	4417	14	0	0
T59	0	50	0	0
T60	0	16	0	0
T61	0	2	0	0
T63	1780	0	0	0
T64	0	37	0	0
T65	1185	6	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593410	780	0	0
T6	23737	93	0	0
T22	4912	30	0	0
T31	1603	0	0	0
T35	4279	0	0	0
T40	21449	116	0	0
T43	7895	0	0	0
T44	2097	0	0	0
T45	0	27	0	0
T58	4417	44	0	0
T59	0	22	0	0
T60	0	9	0	0
T61	0	4	0	0
T63	1780	0	0	0
T64	0	13	0	0
T65	1185	5	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593410	1264	0	0
T6	23737	264	0	0
T22	4912	34	0	0
T31	1603	0	0	0
T35	4279	0	0	0
T40	21449	233	0	0
T43	7895	0	0	0
T44	2097	0	0	0
T45	0	43	0	0
T58	4417	3	0	0
T59	0	41	0	0
T60	0	26	0	0
T61	0	5	0	0
T63	1780	0	0	0
T64	0	23	0	0
T65	1185	1	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593410	1281	0	0
T6	23737	182	0	0
T22	4912	5	0	0
T35	4279	0	0	0
T40	21449	335	0	0
T44	2097	0	0	0
T45	3463	35	0	0
T52	0	55	0	0
T59	0	30	0	0
T60	0	30	0	0
T62	0	3	0	0
T63	1780	0	0	0
T64	0	9	0	0
T65	1185	3	0	0
T68	1778	0	0	0
T69	1457	0	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593410	1160	0	0
T6	23737	207	0	0
T22	4912	17	0	0
T31	1603	0	0	0
T35	4279	0	0	0
T40	21449	267	0	0
T43	7895	0	0	0
T44	2097	0	0	0
T45	0	64	0	0
T58	4417	1	0	0
T59	0	7	0	0
T60	0	36	0	0
T61	0	8	0	0
T63	1780	0	0	0
T64	0	22	0	0
T65	1185	1	0	0