Unified Coverage Report :: Module :: prim_ram_2p

Module : prim_ram_2p

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_abstract_ram_2p_0/prim_ram_2p.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_no_stubbed_memory.u_memory_2p.i_prim_ram_2p_async_adv.u_mem

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Module Instance : tb.dut.gen_no_stubbed_memory.u_memory_2p.i_prim_ram_2p_async_adv.u_mem

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
16.24	15.38				33.33	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
77.45	76.47	33.33			100.00	100.00	i_prim_ram_2p_async_adv

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	16.24	15.38				33.33	0.00

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Since this is the module's only instance, the coverage report is the same as for the module.