Line Coverage for Module :
prim_filter
| Line No. | Total | Covered | Percent |
TOTAL | | 12 | 12 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
ALWAYS | 48 | 4 | 4 | 100.00 |
CONT_ASSIGN | 55 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
ALWAYS | 59 | 3 | 3 | 100.00 |
CONT_ASSIGN | 66 | 1 | 1 | 100.00 |
CONT_ASSIGN | 70 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
|
|
|
MISSING_ELSE |
55 |
1 |
1 |
56 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
62 |
1 |
1 |
66 |
1 |
1 |
70 |
1 |
1 |
Cond Coverage for Module :
prim_filter
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 66
EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
------------------1----------------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2 |
0 | 1 | Covered | T1,T2 |
1 | 0 | Covered | T1,T2 |
LINE 66
SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
------------------1-----------------
-1- | Status | Tests |
0 | Covered | T1,T2 |
1 | Covered | T1,T2 |
LINE 66
SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
------------------1-----------------
-1- | Status | Tests |
0 | Covered | T1,T2 |
1 | Covered | T1,T2 |
LINE 70
EXPRESSION (enable_i ? stored_value_q : filter_synced)
----1---
-1- | Status | Tests |
0 | Unreachable | |
1 | Covered | T1,T2 |
Branch Coverage for Module :
prim_filter
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
70 |
1 |
1 |
100.00 |
IF |
48 |
3 |
3 |
100.00 |
IF |
59 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 70 (enable_i) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2 |
0 |
Unreachable |
|
LineNo. Expression
-1-: 48 if ((!rst_ni))
-2-: 50 if (update_stored_value)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2 |
0 |
1 |
Covered |
T1,T2 |
0 |
0 |
Covered |
T1,T2 |
LineNo. Expression
-1-: 59 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2 |
0 |
Covered |
T1,T2 |
Line Coverage for Instance : tb.dut.usbdev_impl.u_usbdev_linkstate.filter_se0
| Line No. | Total | Covered | Percent |
TOTAL | | 12 | 12 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
ALWAYS | 48 | 4 | 4 | 100.00 |
CONT_ASSIGN | 55 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
ALWAYS | 59 | 3 | 3 | 100.00 |
CONT_ASSIGN | 66 | 1 | 1 | 100.00 |
CONT_ASSIGN | 70 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
|
|
|
MISSING_ELSE |
55 |
1 |
1 |
56 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
62 |
1 |
1 |
66 |
1 |
1 |
70 |
1 |
1 |
Cond Coverage for Instance : tb.dut.usbdev_impl.u_usbdev_linkstate.filter_se0
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 66
EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
------------------1----------------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2 |
0 | 1 | Covered | T1,T2 |
1 | 0 | Covered | T1,T2 |
LINE 66
SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
------------------1-----------------
-1- | Status | Tests |
0 | Covered | T1,T2 |
1 | Covered | T1,T2 |
LINE 66
SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
------------------1-----------------
-1- | Status | Tests |
0 | Covered | T1,T2 |
1 | Covered | T1,T2 |
LINE 70
EXPRESSION (enable_i ? stored_value_q : filter_synced)
----1---
-1- | Status | Tests |
0 | Unreachable | |
1 | Covered | T1,T2 |
Branch Coverage for Instance : tb.dut.usbdev_impl.u_usbdev_linkstate.filter_se0
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
70 |
1 |
1 |
100.00 |
IF |
48 |
3 |
3 |
100.00 |
IF |
59 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 70 (enable_i) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2 |
0 |
Unreachable |
|
LineNo. Expression
-1-: 48 if ((!rst_ni))
-2-: 50 if (update_stored_value)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2 |
0 |
1 |
Covered |
T1,T2 |
0 |
0 |
Covered |
T1,T2 |
LineNo. Expression
-1-: 59 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2 |
0 |
Covered |
T1,T2 |
Line Coverage for Instance : tb.dut.usbdev_impl.u_usbdev_linkstate.filter_pwr_sense
| Line No. | Total | Covered | Percent |
TOTAL | | 12 | 12 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
ALWAYS | 48 | 4 | 4 | 100.00 |
CONT_ASSIGN | 55 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
ALWAYS | 59 | 3 | 3 | 100.00 |
CONT_ASSIGN | 66 | 1 | 1 | 100.00 |
CONT_ASSIGN | 70 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
|
|
|
MISSING_ELSE |
55 |
1 |
1 |
56 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
62 |
1 |
1 |
66 |
1 |
1 |
70 |
1 |
1 |
Cond Coverage for Instance : tb.dut.usbdev_impl.u_usbdev_linkstate.filter_pwr_sense
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 66
EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
------------------1----------------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2 |
0 | 1 | Covered | T1,T2 |
1 | 0 | Covered | T1,T2 |
LINE 66
SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
------------------1-----------------
-1- | Status | Tests |
0 | Covered | T1,T2 |
1 | Covered | T1,T2 |
LINE 66
SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
------------------1-----------------
-1- | Status | Tests |
0 | Covered | T1,T2 |
1 | Covered | T1,T2 |
LINE 70
EXPRESSION (enable_i ? stored_value_q : filter_synced)
----1---
-1- | Status | Tests |
0 | Unreachable | |
1 | Covered | T1,T2 |
Branch Coverage for Instance : tb.dut.usbdev_impl.u_usbdev_linkstate.filter_pwr_sense
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
70 |
1 |
1 |
100.00 |
IF |
48 |
3 |
3 |
100.00 |
IF |
59 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 70 (enable_i) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2 |
0 |
Unreachable |
|
LineNo. Expression
-1-: 48 if ((!rst_ni))
-2-: 50 if (update_stored_value)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2 |
0 |
1 |
Covered |
T1,T2 |
0 |
0 |
Covered |
T1,T2 |
LineNo. Expression
-1-: 59 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2 |
0 |
Covered |
T1,T2 |