Toggle Coverage for Module :
prim_secded_inv_39_32_dec
| Total | Covered | Percent |
Totals |
4 |
4 |
100.00 |
Total Bits |
160 |
160 |
100.00 |
Total Bits 0->1 |
80 |
80 |
100.00 |
Total Bits 1->0 |
80 |
80 |
100.00 |
| | | |
Ports |
4 |
4 |
100.00 |
Port Bits |
160 |
160 |
100.00 |
Port Bits 0->1 |
80 |
80 |
100.00 |
Port Bits 1->0 |
80 |
80 |
100.00 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[38:0] |
Yes |
Yes |
T2,T3,T4 |
Yes |
T1,T3,T4 |
INPUT |
data_o[31:0] |
Yes |
Yes |
T2,T3,T4 |
Yes |
T1,T3,T4 |
OUTPUT |
syndrome_o[6:0] |
Yes |
Yes |
T5,T6,T7 |
Yes |
T5,T6,T7 |
OUTPUT |
err_o[1:0] |
Yes |
Yes |
T5,T6,T7 |
Yes |
T5,T6,T7 |
OUTPUT |