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Module Instance : tb.dut.usbdev_avfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
62.63 86.36 41.67 62.50 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.10 82.50 41.67 56.25 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
72.77 83.19 35.82 89.69 55.17 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 63.89 77.78 50.00


Module Instance : tb.dut.usbdev_rxfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
63.30 90.91 42.31 60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.72 85.00 42.31 55.56 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
72.77 83.19 35.82 89.69 55.17 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 63.89 77.78 50.00


Module Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 fifo_h


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 fifo_h


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[0].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[0].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[1].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[1].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
62.17 86.36 42.31 60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.09 82.50 42.31 55.56 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
59.84 75.38 35.40 50.00 78.57 gen_no_stubbed_memory.u_tlul2sram


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 63.89 77.78 50.00

Go back
Module Instances:
tb.dut.usbdev_avfifo
tb.dut.usbdev_rxfifo
tb.dut.u_reg.u_socket.fifo_h.reqfifo
tb.dut.u_reg.u_socket.fifo_h.rspfifo
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo
Line Coverage for Instance : tb.dut.usbdev_avfifo
Line No.TotalCoveredPercent
TOTAL221986.36
ALWAYS7044100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9811100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN16211100.00
ALWAYS1652150.00
CONT_ASSIGN175100.00
CONT_ASSIGN17611100.00
CONT_ASSIGN182100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
70 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
92 1 1
93 1 1
98 1 1
99 1 1
100 1 1
145 1 1
146 1 1
162 1 1
165 1 1
166 0 1
MISSING_ELSE
175 0 1
176 1 1
182 0 1


Cond Coverage for Instance : tb.dut.usbdev_avfifo
TotalCoveredPercent
Conditions241041.67
Logical241041.67
Non-Logical00
Event00

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (4'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0CoveredT1,T2
1Not Covered

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0Not Covered
1CoveredT1,T2

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------
-1-StatusTests
0Not Covered
1CoveredT1,T2

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2
101Not Covered
110Not Covered
111Not Covered

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2
11CoveredT1,T2

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2
10Not Covered
11Not Covered

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0CoveredT1,T2
1Not Covered

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2
1CoveredT1,T2

Branch Coverage for Instance : tb.dut.usbdev_avfifo
Line No.TotalCoveredPercent
Branches 8 5 62.50
TERNARY 88 3 1 33.33
IF 70 3 3 100.00
IF 165 2 1 50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 88 (gen_normal_fifo.full) ? -2-: 88 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T2
0 0 Not Covered


LineNo. Expression -1-: 70 if ((!rst_ni)) -2-: 72 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2
0 1 Covered T1,T2
0 0 Covered T1,T2


LineNo. Expression -1-: 165 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2


Assert Coverage for Instance : tb.dut.usbdev_avfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 3 60.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 3 60.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 12319 0 0 0
DepthKnown_A 12319 10625 0 0
RvalidKnown_A 12319 10625 0 0
WreadyKnown_A 12319 10625 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 12319 0 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12319 0 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12319 10625 0 0
T1 7240 6396 0 0
T2 5079 4229 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12319 10625 0 0
T1 7240 6396 0 0
T2 5079 4229 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12319 10625 0 0
T1 7240 6396 0 0
T2 5079 4229 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 12319 0 0 0

Line Coverage for Instance : tb.dut.usbdev_rxfifo
Line No.TotalCoveredPercent
TOTAL222090.91
ALWAYS7044100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9811100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN16211100.00
ALWAYS1652150.00
CONT_ASSIGN175100.00
CONT_ASSIGN17611100.00
CONT_ASSIGN18011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
70 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
92 1 1
93 1 1
98 1 1
99 1 1
100 1 1
145 1 1
146 1 1
162 1 1
165 1 1
166 0 1
MISSING_ELSE
175 0 1
176 1 1
180 1 1


Cond Coverage for Instance : tb.dut.usbdev_rxfifo
TotalCoveredPercent
Conditions261142.31
Logical261142.31
Non-Logical00
Event00

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (4'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0CoveredT1,T2
1Not Covered

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0Not Covered
1CoveredT1,T2

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------
-1-StatusTests
0Not Covered
1CoveredT1,T2

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2
101Not Covered
110Not Covered
111Not Covered

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2
11CoveredT1,T2

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2
10Not Covered
11Not Covered

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0CoveredT1,T2
1Not Covered

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2
1CoveredT1,T2

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0Not Covered
1CoveredT1,T2

Branch Coverage for Instance : tb.dut.usbdev_rxfifo
Line No.TotalCoveredPercent
Branches 10 6 60.00
TERNARY 88 3 1 33.33
TERNARY 180 2 1 50.00
IF 70 3 3 100.00
IF 165 2 1 50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 88 (gen_normal_fifo.full) ? -2-: 88 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T2
0 0 Not Covered


LineNo. Expression -1-: 180 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2
0 Not Covered


LineNo. Expression -1-: 70 if ((!rst_ni)) -2-: 72 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2
0 1 Covered T1,T2
0 0 Covered T1,T2


LineNo. Expression -1-: 165 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2


Assert Coverage for Instance : tb.dut.usbdev_rxfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 3 60.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 3 60.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 12319 0 0 0
DepthKnown_A 12319 10625 0 0
RvalidKnown_A 12319 10625 0 0
WreadyKnown_A 12319 10625 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 12319 0 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12319 0 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12319 10625 0 0
T1 7240 6396 0 0
T2 5079 4229 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12319 10625 0 0
T1 7240 6396 0 0
T2 5079 4229 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12319 10625 0 0
T1 7240 6396 0 0
T2 5079 4229 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 12319 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 593410 132385 0 0
DepthKnown_A 593410 573848 0 0
RvalidKnown_A 593410 573848 0 0
WreadyKnown_A 593410 573848 0 0
gen_passthru_fifo.paramCheckPass 125 125 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 593410 132385 0 0
T1 7240 3 0 0
T2 5079 3 0 0
T3 1405 22 0 0
T4 2786 1312 0 0
T5 15912 3939 0 0
T6 23737 3528 0 0
T7 11123 2345 0 0
T8 1304 301 0 0
T9 1848 134 0 0
T10 4367 3331 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 593410 573848 0 0
T1 7240 6396 0 0
T2 5079 4229 0 0
T3 1405 1340 0 0
T4 2786 2677 0 0
T5 15912 15817 0 0
T6 23737 22914 0 0
T7 11123 11038 0 0
T8 1304 1246 0 0
T9 1848 1727 0 0
T10 4367 4294 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 593410 573848 0 0
T1 7240 6396 0 0
T2 5079 4229 0 0
T3 1405 1340 0 0
T4 2786 2677 0 0
T5 15912 15817 0 0
T6 23737 22914 0 0
T7 11123 11038 0 0
T8 1304 1246 0 0
T9 1848 1727 0 0
T10 4367 4294 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 593410 573848 0 0
T1 7240 6396 0 0
T2 5079 4229 0 0
T3 1405 1340 0 0
T4 2786 2677 0 0
T5 15912 15817 0 0
T6 23737 22914 0 0
T7 11123 11038 0 0
T8 1304 1246 0 0
T9 1848 1727 0 0
T10 4367 4294 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 125 125 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 593410 146831 0 0
DepthKnown_A 593410 573848 0 0
RvalidKnown_A 593410 573848 0 0
WreadyKnown_A 593410 573848 0 0
gen_passthru_fifo.paramCheckPass 125 125 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 593410 146831 0 0
T1 7240 3 0 0
T2 5079 3 0 0
T3 1405 107 0 0
T4 2786 661 0 0
T5 15912 6402 0 0
T6 23737 7373 0 0
T7 11123 4104 0 0
T8 1304 151 0 0
T9 1848 68 0 0
T10 4367 1675 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 593410 573848 0 0
T1 7240 6396 0 0
T2 5079 4229 0 0
T3 1405 1340 0 0
T4 2786 2677 0 0
T5 15912 15817 0 0
T6 23737 22914 0 0
T7 11123 11038 0 0
T8 1304 1246 0 0
T9 1848 1727 0 0
T10 4367 4294 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 593410 573848 0 0
T1 7240 6396 0 0
T2 5079 4229 0 0
T3 1405 1340 0 0
T4 2786 2677 0 0
T5 15912 15817 0 0
T6 23737 22914 0 0
T7 11123 11038 0 0
T8 1304 1246 0 0
T9 1848 1727 0 0
T10 4367 4294 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 593410 573848 0 0
T1 7240 6396 0 0
T2 5079 4229 0 0
T3 1405 1340 0 0
T4 2786 2677 0 0
T5 15912 15817 0 0
T6 23737 22914 0 0
T7 11123 11038 0 0
T8 1304 1246 0 0
T9 1848 1727 0 0
T10 4367 4294 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 125 125 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 593410 21692 0 0
DepthKnown_A 593410 573848 0 0
RvalidKnown_A 593410 573848 0 0
WreadyKnown_A 593410 573848 0 0
gen_passthru_fifo.paramCheckPass 125 125 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 593410 21692 0 0
T5 15912 888 0 0
T7 11123 378 0 0
T10 4367 624 0 0
T11 1691 15 0 0
T12 3905 1535 0 0
T13 2070 662 0 0
T14 0 174 0 0
T15 0 536 0 0
T16 0 1535 0 0
T17 0 1112 0 0
T18 8098 0 0 0
T19 1843 0 0 0
T20 1474 0 0 0
T21 3721 0 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 593410 573848 0 0
T1 7240 6396 0 0
T2 5079 4229 0 0
T3 1405 1340 0 0
T4 2786 2677 0 0
T5 15912 15817 0 0
T6 23737 22914 0 0
T7 11123 11038 0 0
T8 1304 1246 0 0
T9 1848 1727 0 0
T10 4367 4294 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 593410 573848 0 0
T1 7240 6396 0 0
T2 5079 4229 0 0
T3 1405 1340 0 0
T4 2786 2677 0 0
T5 15912 15817 0 0
T6 23737 22914 0 0
T7 11123 11038 0 0
T8 1304 1246 0 0
T9 1848 1727 0 0
T10 4367 4294 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 593410 573848 0 0
T1 7240 6396 0 0
T2 5079 4229 0 0
T3 1405 1340 0 0
T4 2786 2677 0 0
T5 15912 15817 0 0
T6 23737 22914 0 0
T7 11123 11038 0 0
T8 1304 1246 0 0
T9 1848 1727 0 0
T10 4367 4294 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 125 125 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 593410 27836 0 0
DepthKnown_A 593410 573848 0 0
RvalidKnown_A 593410 573848 0 0
WreadyKnown_A 593410 573848 0 0
gen_passthru_fifo.paramCheckPass 125 125 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 593410 27836 0 0
T5 15912 2188 0 0
T7 11123 912 0 0
T10 4367 482 0 0
T11 1691 14 0 0
T12 3905 1535 0 0
T13 2070 368 0 0
T14 0 150 0 0
T15 0 1404 0 0
T16 0 1535 0 0
T17 0 2311 0 0
T18 8098 0 0 0
T19 1843 0 0 0
T20 1474 0 0 0
T21 3721 0 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 593410 573848 0 0
T1 7240 6396 0 0
T2 5079 4229 0 0
T3 1405 1340 0 0
T4 2786 2677 0 0
T5 15912 15817 0 0
T6 23737 22914 0 0
T7 11123 11038 0 0
T8 1304 1246 0 0
T9 1848 1727 0 0
T10 4367 4294 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 593410 573848 0 0
T1 7240 6396 0 0
T2 5079 4229 0 0
T3 1405 1340 0 0
T4 2786 2677 0 0
T5 15912 15817 0 0
T6 23737 22914 0 0
T7 11123 11038 0 0
T8 1304 1246 0 0
T9 1848 1727 0 0
T10 4367 4294 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 593410 573848 0 0
T1 7240 6396 0 0
T2 5079 4229 0 0
T3 1405 1340 0 0
T4 2786 2677 0 0
T5 15912 15817 0 0
T6 23737 22914 0 0
T7 11123 11038 0 0
T8 1304 1246 0 0
T9 1848 1727 0 0
T10 4367 4294 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 125 125 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 593410 101934 0 0
DepthKnown_A 593410 573848 0 0
RvalidKnown_A 593410 573848 0 0
WreadyKnown_A 593410 573848 0 0
gen_passthru_fifo.paramCheckPass 125 125 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 593410 101934 0 0
T1 7240 3 0 0
T2 5079 3 0 0
T3 1405 22 0 0
T4 2786 1312 0 0
T5 15912 2201 0 0
T6 23737 3528 0 0
T7 11123 1614 0 0
T8 1304 301 0 0
T9 1848 134 0 0
T10 4367 2029 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 593410 573848 0 0
T1 7240 6396 0 0
T2 5079 4229 0 0
T3 1405 1340 0 0
T4 2786 2677 0 0
T5 15912 15817 0 0
T6 23737 22914 0 0
T7 11123 11038 0 0
T8 1304 1246 0 0
T9 1848 1727 0 0
T10 4367 4294 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 593410 573848 0 0
T1 7240 6396 0 0
T2 5079 4229 0 0
T3 1405 1340 0 0
T4 2786 2677 0 0
T5 15912 15817 0 0
T6 23737 22914 0 0
T7 11123 11038 0 0
T8 1304 1246 0 0
T9 1848 1727 0 0
T10 4367 4294 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 593410 573848 0 0
T1 7240 6396 0 0
T2 5079 4229 0 0
T3 1405 1340 0 0
T4 2786 2677 0 0
T5 15912 15817 0 0
T6 23737 22914 0 0
T7 11123 11038 0 0
T8 1304 1246 0 0
T9 1848 1727 0 0
T10 4367 4294 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 125 125 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 593410 118995 0 0
DepthKnown_A 593410 573848 0 0
RvalidKnown_A 593410 573848 0 0
WreadyKnown_A 593410 573848 0 0
gen_passthru_fifo.paramCheckPass 125 125 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 593410 118995 0 0
T1 7240 3 0 0
T2 5079 3 0 0
T3 1405 107 0 0
T4 2786 661 0 0
T5 15912 4214 0 0
T6 23737 7373 0 0
T7 11123 3192 0 0
T8 1304 151 0 0
T9 1848 68 0 0
T10 4367 1193 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 593410 573848 0 0
T1 7240 6396 0 0
T2 5079 4229 0 0
T3 1405 1340 0 0
T4 2786 2677 0 0
T5 15912 15817 0 0
T6 23737 22914 0 0
T7 11123 11038 0 0
T8 1304 1246 0 0
T9 1848 1727 0 0
T10 4367 4294 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 593410 573848 0 0
T1 7240 6396 0 0
T2 5079 4229 0 0
T3 1405 1340 0 0
T4 2786 2677 0 0
T5 15912 15817 0 0
T6 23737 22914 0 0
T7 11123 11038 0 0
T8 1304 1246 0 0
T9 1848 1727 0 0
T10 4367 4294 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 593410 573848 0 0
T1 7240 6396 0 0
T2 5079 4229 0 0
T3 1405 1340 0 0
T4 2786 2677 0 0
T5 15912 15817 0 0
T6 23737 22914 0 0
T7 11123 11038 0 0
T8 1304 1246 0 0
T9 1848 1727 0 0
T10 4367 4294 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 125 125 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo
Line No.TotalCoveredPercent
TOTAL221986.36
ALWAYS7044100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9811100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN154100.00
ALWAYS1572150.00
CONT_ASSIGN175100.00
CONT_ASSIGN17611100.00
CONT_ASSIGN18011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
70 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
92 1 1
93 1 1
98 1 1
99 1 1
100 1 1
145 1 1
146 1 1
154 0 1
157 1 1
158 0 1
MISSING_ELSE
175 0 1
176 1 1
180 1 1


Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo
TotalCoveredPercent
Conditions261142.31
Logical261142.31
Non-Logical00
Event00

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0CoveredT1,T2
1Not Covered

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0Not Covered
1CoveredT1,T2

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------
-1-StatusTests
0Not Covered
1CoveredT1,T2

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2
101Not Covered
110Not Covered
111Not Covered

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2
11CoveredT1,T2

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2
10Not Covered
11Not Covered

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0CoveredT1,T2
1Not Covered

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2
1CoveredT1,T2

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0Not Covered
1CoveredT1,T2

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo
Line No.TotalCoveredPercent
Branches 10 6 60.00
TERNARY 88 3 1 33.33
TERNARY 180 2 1 50.00
IF 70 3 3 100.00
IF 165 2 1 50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 88 (gen_normal_fifo.full) ? -2-: 88 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T2
0 0 Not Covered


LineNo. Expression -1-: 180 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2
0 Not Covered


LineNo. Expression -1-: 70 if ((!rst_ni)) -2-: 72 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2
0 1 Covered T1,T2
0 0 Covered T1,T2


LineNo. Expression -1-: 165 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2


Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 3 60.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 3 60.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 12319 0 0 0
DepthKnown_A 12319 10625 0 0
RvalidKnown_A 12319 10625 0 0
WreadyKnown_A 12319 10625 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 12319 0 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12319 0 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12319 10625 0 0
T1 7240 6396 0 0
T2 5079 4229 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12319 10625 0 0
T1 7240 6396 0 0
T2 5079 4229 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12319 10625 0 0
T1 7240 6396 0 0
T2 5079 4229 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 12319 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%