Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	36278	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	47944	1		T1	2		T2	442		T3	155

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	50195	1		T1	2		T2	240		T3	34
values[0x0]	16810	1		T2	193		T3	66		T4	70
values[0x1]	17217	1		T1	1		T2	209		T3	74

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	25327	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	58895	1		T1	2		T2	529		T3	158

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	300	1		T2	1		T3	2		T5	2
valid_sources[0x01]	313	1		T2	2		T3	3		T5	2
valid_sources[0x02]	325	1		T2	1		T6	9		T7	2
valid_sources[0x03]	295	1		T2	2		T3	2		T4	4
valid_sources[0x04]	448	1		T2	4		T4	3		T5	2
valid_sources[0x05]	321	1		T2	1		T4	8		T5	2
valid_sources[0x06]	282	1		T2	3		T7	2		T9	1
valid_sources[0x07]	230	1		T2	4		T3	1		T5	5
valid_sources[0x08]	298	1		T2	2		T4	3		T5	3
valid_sources[0x09]	381	1		T2	5		T4	3		T7	1
valid_sources[0x0a]	253	1		T4	1		T5	1		T7	2
valid_sources[0x0b]	311	1		T2	1		T7	1		T9	1
valid_sources[0x0c]	335	1		T2	5		T5	1		T6	18
valid_sources[0x0d]	244	1		T2	2		T3	2		T5	2
valid_sources[0x0e]	291	1		T2	1		T3	4		T4	1
valid_sources[0x0f]	265	1		T2	10		T3	1		T5	1
valid_sources[0x10]	365	1		T2	1		T5	2		T6	1
valid_sources[0x11]	373	1		T2	4		T4	2		T5	2
valid_sources[0x12]	331	1		T2	1		T5	2		T8	1
valid_sources[0x13]	360	1		T2	4		T3	1		T5	1
valid_sources[0x14]	316	1		T2	1		T4	1		T5	1
valid_sources[0x15]	323	1		T2	6		T4	3		T5	2
valid_sources[0x16]	379	1		T2	3		T4	2		T7	1
valid_sources[0x17]	310	1		T2	3		T9	1		T29	5
valid_sources[0x18]	331	1		T2	1		T5	1		T6	1
valid_sources[0x19]	340	1		T2	4		T5	1		T27	13
valid_sources[0x1a]	253	1		T2	7		T5	1		T7	6
valid_sources[0x1b]	347	1		T2	7		T4	1		T7	4
valid_sources[0x1c]	373	1		T2	3		T3	2		T5	3
valid_sources[0x1d]	431	1		T2	3		T3	2		T4	2
valid_sources[0x1e]	329	1		T2	3		T3	2		T5	1
valid_sources[0x1f]	405	1		T2	4		T4	4		T7	1
valid_sources[0x20]	373	1		T2	2		T4	1		T7	2
valid_sources[0x21]	236	1		T2	1		T5	2		T7	1
valid_sources[0x22]	274	1		T2	1		T3	2		T5	1
valid_sources[0x23]	298	1		T3	2		T7	1		T8	1
valid_sources[0x24]	312	1		T2	1		T3	3		T6	3
valid_sources[0x25]	260	1		T2	1		T4	3		T5	1
valid_sources[0x26]	260	1		T2	1		T5	1		T6	2
valid_sources[0x27]	308	1		T4	2		T5	1		T6	9
valid_sources[0x28]	400	1		T2	1		T3	2		T9	1
valid_sources[0x29]	336	1		T2	2		T4	3		T5	4
valid_sources[0x2a]	505	1		T2	4		T3	2		T5	1
valid_sources[0x2b]	271	1		T2	1		T5	3		T8	1
valid_sources[0x2c]	281	1		T2	3		T3	2		T5	1
valid_sources[0x2d]	312	1		T2	1		T11	24		T12	1
valid_sources[0x2e]	327	1		T2	2		T8	1		T29	4
valid_sources[0x2f]	331	1		T2	1		T6	10		T8	3
valid_sources[0x30]	372	1		T4	1		T5	4		T7	1
valid_sources[0x31]	301	1		T2	2		T3	1		T5	2
valid_sources[0x32]	311	1		T2	1		T5	3		T8	1
valid_sources[0x33]	318	1		T2	5		T4	1		T6	5
valid_sources[0x34]	253	1		T2	2		T4	3		T5	1
valid_sources[0x35]	283	1		T2	1		T3	5		T4	4
valid_sources[0x36]	309	1		T2	2		T3	1		T12	1
valid_sources[0x37]	402	1		T2	3		T7	1		T9	1
valid_sources[0x38]	419	1		T2	3		T4	3		T5	1
valid_sources[0x39]	262	1		T2	2		T7	1		T9	1
valid_sources[0x3a]	501	1		T2	4		T4	2		T5	2
valid_sources[0x3b]	292	1		T2	5		T3	1		T7	1
valid_sources[0x3c]	462	1		T2	3		T5	2		T6	1
valid_sources[0x3d]	296	1		T3	1		T7	1		T9	1
valid_sources[0x3e]	321	1		T2	10		T5	2		T6	19
valid_sources[0x3f]	272	1		T2	4		T5	1		T7	2
valid_sources[0x40]	322	1		T3	1		T5	1		T7	2
valid_sources[0x41]	411	1		T2	7		T7	3		T12	1
valid_sources[0x42]	348	1		T2	1		T3	1		T5	1
valid_sources[0x43]	337	1		T2	2		T7	1		T8	1
valid_sources[0x44]	356	1		T3	1		T5	1		T7	1
valid_sources[0x45]	290	1		T2	2		T3	2		T4	1
valid_sources[0x46]	278	1		T2	4		T5	2		T7	4
valid_sources[0x47]	337	1		T2	2		T3	1		T5	3
valid_sources[0x48]	288	1		T2	4		T3	2		T4	1
valid_sources[0x49]	227	1		T2	3		T5	3		T6	3
valid_sources[0x4a]	233	1		T2	2		T3	2		T4	1
valid_sources[0x4b]	447	1		T2	2		T5	1		T12	2
valid_sources[0x4c]	332	1		T2	3		T3	1		T6	1
valid_sources[0x4d]	322	1		T3	1		T5	1		T7	1
valid_sources[0x4e]	291	1		T2	1		T4	3		T5	2
valid_sources[0x4f]	486	1		T2	6		T3	1		T4	1
valid_sources[0x50]	314	1		T2	4		T3	1		T5	3
valid_sources[0x51]	294	1		T2	3		T5	1		T6	10
valid_sources[0x52]	535	1		T2	1		T3	1		T12	1
valid_sources[0x53]	339	1		T2	1		T4	1		T5	1
valid_sources[0x54]	451	1		T3	1		T5	2		T28	5
valid_sources[0x55]	398	1		T2	5		T5	1		T6	1
valid_sources[0x56]	264	1		T2	4		T3	4		T5	1
valid_sources[0x57]	322	1		T2	5		T3	1		T9	1
valid_sources[0x58]	353	1		T2	1		T3	1		T4	1
valid_sources[0x59]	259	1		T2	1		T4	2		T7	2
valid_sources[0x5a]	315	1		T2	2		T3	2		T5	2
valid_sources[0x5b]	308	1		T2	1		T3	1		T5	2
valid_sources[0x5c]	372	1		T2	1		T4	4		T5	1
valid_sources[0x5d]	412	1		T2	10		T3	1		T5	2
valid_sources[0x5e]	331	1		T2	4		T29	2		T13	17
valid_sources[0x5f]	420	1		T2	1		T3	1		T4	2
valid_sources[0x60]	350	1		T2	1		T5	3		T6	1
valid_sources[0x61]	335	1		T3	1		T5	2		T7	1
valid_sources[0x62]	347	1		T2	2		T8	1		T12	2
valid_sources[0x63]	293	1		T2	3		T4	3		T5	1
valid_sources[0x64]	303	1		T2	7		T3	1		T5	1
valid_sources[0x65]	361	1		T2	6		T4	3		T5	4
valid_sources[0x66]	502	1		T2	4		T7	2		T9	4
valid_sources[0x67]	342	1		T2	2		T3	2		T5	3
valid_sources[0x68]	315	1		T2	1		T5	2		T6	4
valid_sources[0x69]	333	1		T4	2		T5	1		T7	1
valid_sources[0x6a]	296	1		T2	6		T5	1		T27	1
valid_sources[0x6b]	248	1		T5	1		T7	3		T27	2
valid_sources[0x6c]	479	1		T2	3		T5	1		T7	2
valid_sources[0x6d]	334	1		T7	1		T8	2		T9	1
valid_sources[0x6e]	305	1		T2	3		T3	2		T4	2
valid_sources[0x6f]	350	1		T2	3		T5	1		T8	1
valid_sources[0x70]	411	1		T2	3		T12	1		T28	1
valid_sources[0x71]	321	1		T2	1		T4	1		T5	1
valid_sources[0x72]	254	1		T3	1		T5	1		T7	1
valid_sources[0x73]	352	1		T2	3		T3	1		T4	1
valid_sources[0x74]	311	1		T2	1		T4	4		T5	2
valid_sources[0x75]	328	1		T3	1		T5	1		T7	1
valid_sources[0x76]	236	1		T2	1		T3	1		T5	2
valid_sources[0x77]	334	1		T2	5		T5	3		T7	2
valid_sources[0x78]	394	1		T2	9		T4	3		T5	1
valid_sources[0x79]	348	1		T2	2		T5	2		T12	2
valid_sources[0x7a]	393	1		T2	2		T7	5		T9	1
valid_sources[0x7b]	578	1		T5	3		T9	1		T12	1
valid_sources[0x7c]	267	1		T2	5		T3	1		T4	1
valid_sources[0x7d]	279	1		T4	1		T7	1		T9	1
valid_sources[0x7e]	244	1		T2	1		T3	3		T4	1
valid_sources[0x7f]	416	1		T3	1		T4	1		T6	3
valid_sources[0x80]	319	1		T2	1		T3	1		T5	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

18929

1

T1

1

T2

62

T3

22

values[0x0]

all_enables

biggest_size

15172

1

T2

188

T3

65

T4

69

values[0x1]

all_enables

biggest_size

13843

1

T1

1

T2

192

T3

68