Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
91.67	91.67	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	91.67	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.67	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	2	14	87.50

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	2	14	87.50	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	49061	1		T1	1		T2	200		T3	19
full_word	48904	1		T1	2		T2	442		T3	155

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	97805	1		T1	3		T2	642		T3	174
auto[TlIntgErrCmd]	46	1		T43	1		T45	6		T31	4
auto[TlIntgErrData]	53	1		T43	5		T45	7		T31	2
auto[TlIntgErrBoth]	61	1		T43	4		T45	7		T31	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	51990	1		T1	2		T2	240		T3	34
auto[1]	45975	1		T1	1		T2	402		T3	140

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	2	14	87.50	2

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER
[auto[TlIntgErrCmd] , auto[TlIntgErrData]]	[full_word]	[auto[0]]	--	--	2

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	32826	1		T1	1		T2	178		T3	12
auto[TlIntgErrNone]	partial	auto[1]	16086	1		T2	22		T3	7		T4	7
auto[TlIntgErrNone]	full_word	auto[0]	19091	1		T1	1		T2	62		T3	22
auto[TlIntgErrNone]	full_word	auto[1]	29802	1		T1	1		T2	380		T3	133
auto[TlIntgErrCmd]	partial	auto[0]	15	1		T43	1		T45	3		T44	1
auto[TlIntgErrCmd]	partial	auto[1]	27	1		T45	3		T31	3		T33	8
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T31	1		T70	1		T34	1
auto[TlIntgErrData]	partial	auto[0]	30	1		T43	4		T45	5		T31	2
auto[TlIntgErrData]	partial	auto[1]	22	1		T43	1		T45	2		T44	2
auto[TlIntgErrData]	full_word	auto[1]	1	1		T34	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	25	1		T43	2		T45	2		T31	2
auto[TlIntgErrBoth]	partial	auto[1]	30	1		T43	2		T45	3		T31	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T45	1		T33	1		T35	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T45	1		T44	1		T35	1