Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
72.77	83.19	35.82	89.69		55.17	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	722341	11100	0	0
ep_in_enable_rd_A	722341	557	0	0
ep_out_enable_rd_A	722341	684	0	0
in_iso_rd_A	722341	700	0	0
intr_enable_rd_A	722341	1119	0	0
out_iso_rd_A	722341	907	0	0
phy_config_rd_A	722341	321	0	0
phy_pins_drive_rd_A	722341	561	0	0
rxenable_setup_rd_A	722341	873	0	0
set_nak_out_rd_A	722341	636	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	722341	11100	0	0
T2	2364	5	0	0
T3	2627	2	0	0
T4	1417	2	0	0
T5	8608	460	0	0
T9	2391	1	0	0
T11	2067	5	0	0
T12	13733	705	0	0
T14	1877	3	0	0
T15	4429	253	0	0
T16	1647	0	0	0
T37	0	5	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	722341	557	0	0
T24	1125	0	0	0
T26	1288	0	0	0
T31	0	222	0	0
T43	21371	0	0	0
T45	23082	0	0	0
T46	0	179	0	0
T51	3715	52	0	0
T52	16299	0	0	0
T53	2187	0	0	0
T54	2063	0	0	0
T55	5611	0	0	0
T57	0	8	0	0
T62	7237	20	0	0
T65	0	5	0	0
T66	0	1	0	0
T67	0	15	0	0
T68	0	8	0	0
T69	0	4	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	722341	684	0	0
T12	13733	1	0	0
T24	1125	0	0	0
T26	1288	0	0	0
T31	0	270	0	0
T43	21371	0	0	0
T45	23082	0	0	0
T46	0	97	0	0
T51	3715	83	0	0
T52	16299	0	0	0
T53	2187	0	0	0
T55	5611	0	0	0
T57	0	50	0	0
T62	7237	17	0	0
T65	0	1	0	0
T66	0	40	0	0
T67	0	9	0	0
T68	0	20	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	722341	700	0	0
T17	0	3	0	0
T24	1125	0	0	0
T26	1288	0	0	0
T31	0	296	0	0
T43	21371	0	0	0
T45	23082	0	0	0
T46	0	231	0	0
T51	3715	79	0	0
T52	16299	0	0	0
T53	2187	0	0	0
T54	2063	0	0	0
T55	5611	0	0	0
T57	0	61	0	0
T62	7237	1	0	0
T65	0	3	0	0
T66	0	3	0	0
T67	0	1	0	0
T68	0	2	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	722341	1119	0	0
T15	4429	0	0	0
T16	1647	11	0	0
T21	1633	12	0	0
T22	1253	9	0	0
T24	0	13	0	0
T26	0	10	0	0
T31	0	275	0	0
T37	2509	0	0	0
T38	9274	0	0	0
T39	3050	0	0	0
T40	3590	0	0	0
T41	2086	0	0	0
T51	0	135	0	0
T57	0	1	0	0
T62	7237	59	0	0
T65	0	4	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	722341	907	0	0
T17	0	2	0	0
T24	1125	0	0	0
T26	1288	0	0	0
T31	0	246	0	0
T43	21371	0	0	0
T45	23082	0	0	0
T46	0	325	0	0
T51	3715	81	0	0
T52	16299	0	0	0
T53	2187	0	0	0
T54	2063	0	0	0
T55	5611	0	0	0
T57	0	48	0	0
T62	7237	113	0	0
T65	0	7	0	0
T66	0	1	0	0
T67	0	2	0	0
T68	0	20	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	722341	321	0	0
T17	0	7	0	0
T24	1125	0	0	0
T26	1288	0	0	0
T31	0	87	0	0
T43	21371	0	0	0
T45	23082	0	0	0
T46	0	90	0	0
T51	3715	2	0	0
T52	16299	0	0	0
T53	2187	0	0	0
T54	2063	0	0	0
T55	5611	0	0	0
T57	0	7	0	0
T62	7237	30	0	0
T65	0	3	0	0
T66	0	5	0	0
T67	0	10	0	0
T68	0	24	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	722341	561	0	0
T17	0	9	0	0
T24	1125	0	0	0
T26	1288	0	0	0
T31	0	154	0	0
T43	21371	0	0	0
T45	23082	0	0	0
T46	0	185	0	0
T51	3715	37	0	0
T52	16299	0	0	0
T53	2187	0	0	0
T54	2063	0	0	0
T55	5611	0	0	0
T57	0	6	0	0
T62	7237	68	0	0
T65	0	2	0	0
T66	0	2	0	0
T67	0	11	0	0
T68	0	14	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	722341	873	0	0
T17	0	8	0	0
T24	1125	0	0	0
T26	1288	0	0	0
T31	0	240	0	0
T43	21371	0	0	0
T45	23082	0	0	0
T46	0	254	0	0
T51	3715	92	0	0
T52	16299	0	0	0
T53	2187	0	0	0
T54	2063	0	0	0
T55	5611	0	0	0
T57	0	111	0	0
T62	7237	47	0	0
T64	0	2	0	0
T66	0	34	0	0
T67	0	11	0	0
T68	0	20	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	722341	636	0	0
T17	0	4	0	0
T24	1125	0	0	0
T26	1288	0	0	0
T31	0	255	0	0
T43	21371	0	0	0
T45	23082	0	0	0
T46	0	196	0	0
T51	3715	69	0	0
T52	16299	0	0	0
T53	2187	0	0	0
T54	2063	0	0	0
T55	5611	0	0	0
T57	0	6	0	0
T62	7237	16	0	0
T65	0	4	0	0
T66	0	43	0	0
T67	0	11	0	0
T69	0	3	0	0