SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.83 | 91.67 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen | 83.33 | 66.67 | 100.00 | ||||
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rsp_gen | 91.67 | 83.33 | 100.00 | ||||
tb.dut.u_reg.u_rsp_intg_gen | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
83.33 | 66.67 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
83.33 | 66.67 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.98 | 100.00 | 95.92 | 100.00 | 100.00 | u_reg_if |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
91.67 | 83.33 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
91.67 | 83.33 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
59.40 | 75.38 | 33.63 | 50.00 | 78.57 | gen_no_stubbed_memory.u_tlul2sram |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.60 | 99.72 | 98.70 | 100.00 | 100.00 | u_reg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_data_intg.u_tlul_data_integ_enc | 100.00 | 100.00 | |||||
gen_rsp_intg.u_rsp_gen | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
CONT_ASSIGN | 25 | 1 | 1 | 100.00 |
ALWAYS | 47 | 3 | 3 | 100.00 |
CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
47 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | 1 | 1 |
SCORE | LINE |
83.33 | 66.67 |
SCORE | LINE |
91.67 | 83.33 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 5 | 83.33 | |
CONT_ASSIGN | 32 | 1 | 0 | 0.00 |
CONT_ASSIGN | 43 | 1 | 1 | 100.00 |
ALWAYS | 47 | 3 | 3 | 100.00 |
CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
32 | 0 | 1 | |
43 | 1 | 1 | |
47 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataWidthCheck_A | 297 | 297 | 0 | 0 |
PayLoadWidthCheck | 297 | 297 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 297 | 297 | 0 | 0 |
T1 | 3 | 3 | 0 | 0 |
T2 | 2 | 2 | 0 | 0 |
T3 | 2 | 2 | 0 | 0 |
T4 | 2 | 2 | 0 | 0 |
T5 | 2 | 2 | 0 | 0 |
T6 | 2 | 2 | 0 | 0 |
T7 | 2 | 2 | 0 | 0 |
T8 | 2 | 2 | 0 | 0 |
T9 | 2 | 2 | 0 | 0 |
T10 | 2 | 2 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 297 | 297 | 0 | 0 |
T1 | 3 | 3 | 0 | 0 |
T2 | 2 | 2 | 0 | 0 |
T3 | 2 | 2 | 0 | 0 |
T4 | 2 | 2 | 0 | 0 |
T5 | 2 | 2 | 0 | 0 |
T6 | 2 | 2 | 0 | 0 |
T7 | 2 | 2 | 0 | 0 |
T8 | 2 | 2 | 0 | 0 |
T9 | 2 | 2 | 0 | 0 |
T10 | 2 | 2 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 4 | 66.67 | |
CONT_ASSIGN | 32 | 1 | 0 | 0.00 |
CONT_ASSIGN | 43 | 1 | 0 | 0.00 |
ALWAYS | 47 | 3 | 3 | 100.00 |
CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
32 | 0 | 1 | |
43 | 0 | 1 | |
47 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataWidthCheck_A | 148 | 148 | 0 | 0 |
PayLoadWidthCheck | 148 | 148 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 148 | 148 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 148 | 148 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 5 | 83.33 | |
CONT_ASSIGN | 32 | 1 | 0 | 0.00 |
CONT_ASSIGN | 43 | 1 | 1 | 100.00 |
ALWAYS | 47 | 3 | 3 | 100.00 |
CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
32 | 0 | 1 | |
43 | 1 | 1 | |
47 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataWidthCheck_A | 1 | 1 | 0 | 0 |
PayLoadWidthCheck | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1 | 1 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1 | 1 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
CONT_ASSIGN | 25 | 1 | 1 | 100.00 |
ALWAYS | 47 | 3 | 3 | 100.00 |
CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
47 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataWidthCheck_A | 148 | 148 | 0 | 0 |
PayLoadWidthCheck | 148 | 148 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 148 | 148 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 148 | 148 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |