Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : usb_fs_rx
SCORELINECONDTOGGLEFSMBRANCHASSERT
59.90 75.68 45.60 58.43

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_rx.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_rx 59.90 75.68 45.60 58.43



Module Instance : tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_rx

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
59.90 75.68 45.60 58.43


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
59.90 75.68 45.60 58.43


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
72.22 100.00 16.67 100.00 u_usb_fs_nb_pe


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : usb_fs_rx
Line No.TotalCoveredPercent
TOTAL18514075.68
CONT_ASSIGN7011100.00
CONT_ASSIGN7111100.00
CONT_ASSIGN7211100.00
ALWAYS1225360.00
ALWAYS13211872.73
ALWAYS15155100.00
ALWAYS16955100.00
CONT_ASSIGN22111100.00
CONT_ASSIGN22211100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24311100.00
CONT_ASSIGN24611100.00
ALWAYS2495480.00
CONT_ASSIGN27611100.00
CONT_ASSIGN27711100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28611100.00
CONT_ASSIGN28711100.00
ALWAYS29133100.00
ALWAYS2999666.67
CONT_ASSIGN32211100.00
ALWAYS3268675.00
CONT_ASSIGN34311100.00
CONT_ASSIGN34411100.00
ALWAYS34733100.00
CONT_ASSIGN35511100.00
ALWAYS37012433.33
ALWAYS3965360.00
ALWAYS4065480.00
CONT_ASSIGN41811100.00
CONT_ASSIGN42411100.00
ALWAYS4285360.00
ALWAYS43733100.00
CONT_ASSIGN44411100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45711100.00
ALWAYS4605360.00
CONT_ASSIGN47411100.00
CONT_ASSIGN47511100.00
ALWAYS4785360.00
CONT_ASSIGN49611100.00
CONT_ASSIGN49711100.00
ALWAYS5005360.00
CONT_ASSIGN51611100.00
CONT_ASSIGN51711100.00
CONT_ASSIGN51811100.00
CONT_ASSIGN52011100.00
CONT_ASSIGN52411100.00
CONT_ASSIGN53111100.00
CONT_ASSIGN53511100.00
CONT_ASSIGN54011100.00
ALWAYS5475360.00
ALWAYS5607457.14
CONT_ASSIGN57111100.00
CONT_ASSIGN57211100.00
CONT_ASSIGN57311100.00
CONT_ASSIGN57411100.00
CONT_ASSIGN57611100.00
CONT_ASSIGN57711100.00
CONT_ASSIGN58711100.00
CONT_ASSIGN58811100.00
CONT_ASSIGN58911100.00
ALWAYS5925360.00
ALWAYS608261869.23
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_rx.sv' or '../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_rx.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
70 1 1
71 1 1
72 1 1
122 1 1
123 0 1
124 0 1
126 1 1
127 1 1
132 1 1
133 1 1
134 1 1
135 1 1
137 1 1
138 0 1
139 0 1
140 0 1
142 1 1
143 1 1
144 1 1
151 1 1
153 1 1
156 1 1
161 1 1
162 1 1
MISSING_ELSE
169 1 1
171 1 1
174 1 1
179 1 1
180 1 1
MISSING_ELSE
221 1 1
222 1 1
242 1 1
243 1 1
246 1 1
249 1 1
250 1 1
252 1 1
253 0 1
255 1 1
276 1 1
277 1 1
282 1 1
286 1 1
287 1 1
291 1 1
292 1 1
294 1 1
299 1 1
302 1 1
303 0 1
305 1 1
306 0 1
310 1 1
311 0 1
314 1 1
317 1 1
322 1 1
326 1 1
327 1 1
328 1 1
330 1 1
331 0 1
332 0 1
334 1 1
335 1 1
343 1 1
344 1 1
347 1 1
348 1 1
350 1 1
355 1 1
370 1 1
371 0 1
372 0 1
373 0 1
374 1 1
378 1 1
379 0 1
380 0 1
381 0 1
382 0 1
383 0 1
387 1 1
396 1 1
397 0 1
398 1 1
399 0 1
401 1 1
406 1 1
407 1 1
409 1 1
410 0 1
412 1 1
418 1 1
424 1 1
428 1 1
429 1 1
430 0 1
431 1 1
432 0 1
MISSING_ELSE
437 1 1
438 1 1
440 1 1
444 1 1
456 1 1
457 1 1
460 1 1
461 0 1
462 1 1
463 0 1
465 1 1
474 1 1
475 1 1
478 1 1
480 1 1
481 0 1
MISSING_ELSE
484 1 1
485 0 1
MISSING_ELSE
496 1 1
497 1 1
500 1 1
502 1 1
503 0 1
MISSING_ELSE
506 1 1
507 0 1
MISSING_ELSE
516 1 1
517 1 1
518 1 1
520 1 1
524 1 1
531 1 1
535 1 1
540 1 1
547 1 1
549 1 1
550 0 1
MISSING_ELSE
553 1 1
554 0 1
MISSING_ELSE
560 1 1
561 1 1
562 1 1
564 1 1
565 0 1
566 0 1
567 0 1
MISSING_ELSE
571 1 1
572 1 1
573 1 1
574 1 1
576 1 1
577 1 1
587 1 1
588 1 1
589 1 1
592 1 1
594 1 1
595 0 1
MISSING_ELSE
598 1 1
599 0 1
MISSING_ELSE
608 1 1
609 1 1
610 1 1
611 1 1
612 1 1
613 1 1
614 1 1
615 1 1
616 1 1
618 1 1
619 0 1
620 0 1
621 0 1
622 0 1
623 0 1
624 0 1
625 0 1
626 0 1
628 1 1
629 1 1
630 1 1
631 1 1
632 1 1
633 1 1
634 1 1
635 1 1


Cond Coverage for Module : usb_fs_rx
TotalCoveredPercent
Conditions1938845.60
Logical1938845.60
Non-Logical00
Event00

 LINE       70
 EXPRESSION (cfg_pinflip_i ? usb_dn_i : usb_dp_i)
             ------1------
-1-StatusTests
0CoveredT1
1Not Covered

 LINE       71
 EXPRESSION (cfg_pinflip_i ? usb_dp_i : usb_dn_i)
             ------1------
-1-StatusTests
0CoveredT1
1Not Covered

 LINE       72
 EXPRESSION (usb_d_i ^ cfg_pinflip_i)
             ---1---   ------2------
-1--2-StatusTests
00CoveredT1
01Not Covered
10CoveredT1
11Not Covered

 LINE       127
 EXPRESSION (usb_d_flipped ? DJ[1:0] : DK[1:0])
             ------1------
-1-StatusTests
0CoveredT1
1CoveredT1

 LINE       153
 EXPRESSION (line_state_q == DT)
            ----------1---------
-1-StatusTests
0CoveredT1
1CoveredT1

 LINE       161
 EXPRESSION (dpair != line_state_q[1:0])
            --------------1-------------
-1-StatusTests
0CoveredT1
1CoveredT1

 LINE       171
 EXPRESSION (diff_state_q == DT)
            ----------1---------
-1-StatusTests
0CoveredT1
1CoveredT1

 LINE       179
 EXPRESSION (ddiff != diff_state_q[1:0])
            --------------1-------------
-1-StatusTests
0CoveredT1
1CoveredT1

 LINE       221
 EXPRESSION ((line_state_q == SE0) || ((line_state_q == DT) && (line_state_qq == SE0)))
             ----------1----------    ------------------------2-----------------------
-1--2-StatusTests
00CoveredT1
01CoveredT1
10CoveredT1

 LINE       221
 SUB-EXPRESSION (line_state_q == SE0)
                ----------1----------
-1-StatusTests
0CoveredT1
1CoveredT1

 LINE       221
 SUB-EXPRESSION ((line_state_q == DT) && (line_state_qq == SE0))
                 ----------1---------    -----------2----------
-1--2-StatusTests
01CoveredT1
10Not Covered
11CoveredT1

 LINE       221
 SUB-EXPRESSION (line_state_q == DT)
                ----------1---------
-1-StatusTests
0CoveredT1
1CoveredT1

 LINE       221
 SUB-EXPRESSION (line_state_qq == SE0)
                -----------1----------
-1-StatusTests
0CoveredT1
1CoveredT1

 LINE       222
 EXPRESSION (cfg_use_diff_rcvr_i ? (use_se ? line_state_q : diff_state_q) : line_state_q)
             ---------1---------
-1-StatusTests
0CoveredT1
1Not Covered

 LINE       222
 SUB-EXPRESSION (use_se ? line_state_q : diff_state_q)
                 ---1--
-1-StatusTests
0Not Covered
1Not Covered

 LINE       242
 EXPRESSION (bit_phase_q == 2'b1)
            ----------1----------
-1-StatusTests
0CoveredT1
1CoveredT1

 LINE       243
 EXPRESSION (bit_phase_q == 2'd2)
            ----------1----------
-1-StatusTests
0CoveredT1
1CoveredT1

 LINE       246
 EXPRESSION ((line_state_rx == DT) ? 0 : ((bit_phase_q + 1)))
             ----------1----------
-1-StatusTests
0CoveredT1
1CoveredT1

 LINE       246
 SUB-EXPRESSION (line_state_rx == DT)
                ----------1----------
-1-StatusTests
0CoveredT1
1CoveredT1

 LINE       276
 EXPRESSION (packet_valid_d & ((~packet_valid_q)))
             -------1------   ---------2---------
-1--2-StatusTests
01CoveredT1
10Not Covered
11Not Covered

 LINE       277
 EXPRESSION (((~packet_valid_d)) & packet_valid_q)
             ---------1---------   -------2------
-1--2-StatusTests
01Not Covered
10CoveredT1
11Not Covered

 LINE       282
 EXPRESSION ((cfg_eop_single_bit_i && (line_history_q[1:0] == 2'b0)) || (line_history_q[3:0] == 4'b0) || bitstuff_error_q || see_preamble)
             ---------------------------1---------------------------    --------------2--------------    --------3-------    ------4-----
-1--2--3--4-StatusTests
0000CoveredT1
0001Not Covered
0010Not Covered
0100Not Covered
1000CoveredT1

 LINE       282
 SUB-EXPRESSION (cfg_eop_single_bit_i && (line_history_q[1:0] == 2'b0))
                 ----------1---------    --------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1
11CoveredT1

 LINE       282
 SUB-EXPRESSION (line_history_q[1:0] == 2'b0)
                --------------1--------------
-1-StatusTests
0CoveredT1
1CoveredT1

 LINE       282
 SUB-EXPRESSION (line_history_q[3:0] == 4'b0)
                --------------1--------------
-1-StatusTests
0CoveredT1
1CoveredT1

 LINE       286
 EXPRESSION ((line_history_q[3:0] == 4'b1001) & ((~tx_en_i)) & ((~in_packet_q)))
             ----------------1---------------   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1
101Not Covered
110Not Covered
111Not Covered

 LINE       286
 SUB-EXPRESSION (line_history_q[3:0] == 4'b1001)
                ----------------1---------------
-1-StatusTests
0CoveredT1
1Not Covered

 LINE       287
 EXPRESSION (see_eop ? 1'b0 : (see_sop ? 1'b1 : in_packet_q))
             ---1---
-1-StatusTests
0CoveredT1
1CoveredT1

 LINE       287
 SUB-EXPRESSION (see_sop ? 1'b1 : in_packet_q)
                 ---1---
-1-StatusTests
0CoveredT1
1Not Covered

 LINE       305
 EXPRESSION (((!packet_valid_q)) && (line_history_q[11:0] == 12'b011001100101))
             ---------1---------    ---------------------2--------------------
-1--2-StatusTests
01Not Covered
10CoveredT1
11Not Covered

 LINE       305
 SUB-EXPRESSION (line_history_q[11:0] == 12'b011001100101)
                ---------------------1--------------------
-1-StatusTests
0CoveredT1
1Not Covered

 LINE       310
 EXPRESSION (packet_valid_q && see_eop)
             -------1------    ---2---
-1--2-StatusTests
01CoveredT1
10Not Covered
11Not Covered

 LINE       322
 EXPRESSION (line_state_valid ? ({line_history_q[9:0], line_state_rx[1:0]}) : line_history_q)
             --------1-------
-1-StatusTests
0CoveredT1
1CoveredT1

 LINE       343
 EXPRESSION ((((~tx_en_i)) & line_state_valid) ? (line_state_q == DJ) : rx_idle_det_q)
             ----------------1----------------
-1-StatusTests
0CoveredT1
1CoveredT1

 LINE       343
 SUB-EXPRESSION (((~tx_en_i)) & line_state_valid)
                 ------1-----   --------2-------
-1--2-StatusTests
01Not Covered
10CoveredT1
11CoveredT1

 LINE       343
 SUB-EXPRESSION (line_state_q == DJ)
                ----------1---------
-1-StatusTests
0CoveredT1
1CoveredT1

 LINE       355
 EXPRESSION (diff_rx_ok_i & ((~tx_en_i)) & (line_history_q[1:0] == 2'b10))
             ------1-----   ------2-----   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1
101Not Covered
110CoveredT1
111CoveredT1

 LINE       355
 SUB-EXPRESSION (line_history_q[1:0] == 2'b10)
                ---------------1--------------
-1-StatusTests
0CoveredT1
1CoveredT1

 LINE       378
 EXPRESSION (packet_valid_q && line_state_valid)
             -------1------    --------2-------
-1--2-StatusTests
01CoveredT1
10Not Covered
11Not Covered

 LINE       418
 EXPRESSION (dvalid_raw && ( ! (bitstuff_history_q[5:0] == 6'b111111) ))
             -----1----    ----------------------2---------------------
-1--2-StatusTests
01CoveredT1
10Not Covered
11Not Covered

 LINE       418
 SUB-EXPRESSION ( ! (bitstuff_history_q[5:0] == 6'b111111) )
                    -------------------1------------------
-1-StatusTests
0CoveredT1
1Not Covered

 LINE       418
 SUB-EXPRESSION (bitstuff_history_q[5:0] == 6'b111111)
                -------------------1------------------
-1-StatusTests
0CoveredT1
1Not Covered

 LINE       424
 EXPRESSION (bitstuff_history_q == 7'b1111111)
            -----------------1----------------
-1-StatusTests
0CoveredT1
1Not Covered

 LINE       431
 EXPRESSION (bitstuff_error && dvalid_raw)
             -------1------    -----2----
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       444
 EXPRESSION (bitstuff_error_q && packet_end)
             --------1-------    -----2----
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       456
 EXPRESSION (full_pid_q[4:1] == (~full_pid_q[8:5]))
            -------------------1-------------------
-1-StatusTests
0CoveredT1
1Not Covered

 LINE       460
 EXPRESSION (dvalid && ((!pid_complete)))
             ---1--    --------2--------
-1--2-StatusTests
01CoveredT1
10Not Covered
11Not Covered

 LINE       474
 EXPRESSION (crc5_q == 5'b01100)
            ----------1---------
-1-StatusTests
0CoveredT1
1Not Covered

 LINE       475
 EXPRESSION (din ^ crc5_q[4])
             -1-   ----2----
-1--2-StatusTests
00CoveredT1
01Not Covered
10CoveredT1
11Not Covered

 LINE       484
 EXPRESSION (dvalid && pid_complete)
             ---1--    ------2-----
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       496
 EXPRESSION (crc16_q == 16'b1000000000001101)
            ----------------1----------------
-1-StatusTests
0CoveredT1
1Not Covered

 LINE       497
 EXPRESSION (din ^ crc16_q[15])
             -1-   -----2-----
-1--2-StatusTests
00CoveredT1
01Not Covered
10CoveredT1
11Not Covered

 LINE       506
 EXPRESSION (dvalid && pid_complete)
             ---1--    ------2-----
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       516
 EXPRESSION (full_pid_q[2:1] == 2'b1)
            ------------1------------
-1-StatusTests
0CoveredT1
1Not Covered

 LINE       517
 EXPRESSION (full_pid_q[2:1] == 2'b11)
            -------------1------------
-1-StatusTests
0CoveredT1
1Not Covered

 LINE       518
 EXPRESSION (full_pid_q[2:1] == 2'b10)
            -------------1------------
-1-StatusTests
0CoveredT1
1Not Covered

 LINE       520
 EXPRESSION ((packet_valid_q & pid_valid & pid_complete) && (usb_pid_e'(full_pid_q[4:1]) == UsbPidPre))
             ---------------------1---------------------    ---------------------2--------------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       520
 SUB-EXPRESSION (packet_valid_q & pid_valid & pid_complete)
                 -------1------   ----2----   ------3-----
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered

 LINE       520
 SUB-EXPRESSION (usb_pid_e'(full_pid_q[4:1]) == UsbPidPre)
                ---------------------1--------------------
-1-StatusTests
0CoveredT1
1Not Covered

 LINE       524
 EXPRESSION (pid_valid && ((!bitstuff_error_q)) && (pkt_is_handshake || (pkt_is_data && crc16_valid) || (pkt_is_token && crc5_valid)))
             ----1----    ----------2----------    -----------------------------------------3----------------------------------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered

 LINE       524
 SUB-EXPRESSION (pkt_is_handshake || (pkt_is_data && crc16_valid) || (pkt_is_token && crc5_valid))
                 --------1-------    --------------2-------------    --------------3-------------
-1--2--3-StatusTests
000CoveredT1
001Not Covered
010Not Covered
100Not Covered

 LINE       524
 SUB-EXPRESSION (pkt_is_data && crc16_valid)
                 -----1-----    -----2-----
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       524
 SUB-EXPRESSION (pkt_is_token && crc5_valid)
                 ------1-----    -----2----
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       531
 EXPRESSION (((pkt_is_data && ((!crc16_valid))) || (pkt_is_token && ((!crc5_valid)))) && packet_end)
             ------------------------------------1-----------------------------------    -----2----
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       531
 SUB-EXPRESSION ((pkt_is_data && ((!crc16_valid))) || (pkt_is_token && ((!crc5_valid))))
                 ----------------1----------------    ----------------2----------------
-1--2-StatusTests
00CoveredT1
01Not Covered
10Not Covered

 LINE       531
 SUB-EXPRESSION (pkt_is_data && ((!crc16_valid)))
                 -----1-----    --------2-------
-1--2-StatusTests
01CoveredT1
10Not Covered
11Not Covered

 LINE       531
 SUB-EXPRESSION (pkt_is_token && ((!crc5_valid)))
                 ------1-----    -------2-------
-1--2-StatusTests
01CoveredT1
10Not Covered
11Not Covered

 LINE       535
 EXPRESSION (((!pid_valid)) && packet_end)
             -------1------    -----2----
-1--2-StatusTests
01Not Covered
10CoveredT1
11Not Covered

 LINE       553
 EXPRESSION (dvalid && pid_complete && pkt_is_token && ((!token_payload_done)))
             ---1--    ------2-----    ------3-----    -----------4-----------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101Not Covered
1110Not Covered
1111Not Covered

 LINE       564
 EXPRESSION (token_payload_done && pkt_is_token)
             ---------1--------    ------2-----
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       594
 EXPRESSION (packet_start || rx_data_buffer_full)
             ------1-----    ---------2---------
-1--2-StatusTests
00CoveredT1
01Not Covered
10Not Covered

 LINE       598
 EXPRESSION (dvalid && pid_complete && pkt_is_data)
             ---1--    ------2-----    -----3-----
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered

Branch Coverage for Module : usb_fs_rx
Line No.TotalCoveredPercent
Branches 89 52 58.43
TERNARY 70 2 1 50.00
TERNARY 71 2 1 50.00
TERNARY 222 3 1 33.33
TERNARY 246 2 2 100.00
TERNARY 287 3 2 66.67
TERNARY 322 2 2 100.00
TERNARY 343 2 2 100.00
IF 122 3 2 66.67
IF 132 3 2 66.67
IF 153 3 3 100.00
IF 171 3 3 100.00
IF 249 3 2 66.67
IF 291 2 2 100.00
IF 299 5 2 40.00
IF 326 3 2 66.67
IF 347 2 2 100.00
CASE 370 5 2 40.00
IF 378 6 1 16.67
IF 396 3 1 33.33
IF 406 3 2 66.67
IF 429 3 1 33.33
IF 437 2 2 100.00
IF 460 3 1 33.33
IF 480 2 1 50.00
IF 484 2 1 50.00
IF 502 2 1 50.00
IF 506 2 1 50.00
IF 549 2 1 50.00
IF 553 2 1 50.00
IF 564 2 1 50.00
IF 594 2 1 50.00
IF 598 2 1 50.00
IF 608 3 2 66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_rx.sv' or '../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_rx.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 70 (cfg_pinflip_i) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1


LineNo. Expression -1-: 71 (cfg_pinflip_i) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1


LineNo. Expression -1-: 222 (cfg_use_diff_rcvr_i) ? -2-: 222 (use_se) ?

Branches:
-1--2-StatusTests
1 1 Not Covered
1 0 Not Covered
0 - Covered T1


LineNo. Expression -1-: 246 ((line_state_rx == DT)) ?

Branches:
-1-StatusTests
1 Covered T1
0 Covered T1


LineNo. Expression -1-: 287 (see_eop) ? -2-: 287 (see_sop) ?

Branches:
-1--2-StatusTests
1 - Covered T1
0 1 Not Covered
0 0 Covered T1


LineNo. Expression -1-: 322 (line_state_valid) ?

Branches:
-1-StatusTests
1 Covered T1
0 Covered T1


LineNo. Expression -1-: 343 (((~tx_en_i) & line_state_valid)) ?

Branches:
-1-StatusTests
1 Covered T1
0 Covered T1


LineNo. Expression -1-: 122 if (tx_en_i) -2-: 127 (usb_d_flipped) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1
0 0 Covered T1


LineNo. Expression -1-: 132 if ((!rst_ni)) -2-: 137 if (link_reset_i)

Branches:
-1--2-StatusTests
1 - Covered T1
0 1 Not Covered
0 0 Covered T1


LineNo. Expression -1-: 153 if ((line_state_q == DT)) -2-: 161 if ((dpair != line_state_q[1:0]))

Branches:
-1--2-StatusTests
1 - Covered T1
0 1 Covered T1
0 0 Covered T1


LineNo. Expression -1-: 171 if ((diff_state_q == DT)) -2-: 179 if ((ddiff != diff_state_q[1:0]))

Branches:
-1--2-StatusTests
1 - Covered T1
0 1 Covered T1
0 0 Covered T1


LineNo. Expression -1-: 249 if ((!rst_ni)) -2-: 252 if (link_reset_i)

Branches:
-1--2-StatusTests
1 - Covered T1
0 1 Not Covered
0 0 Covered T1


LineNo. Expression -1-: 291 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1
0 Covered T1


LineNo. Expression -1-: 299 if (line_state_valid) -2-: 302 if ((~diff_rx_ok_i)) -3-: 305 if (((!packet_valid_q) && (line_history_q[11:0] == 12'b011001100101))) -4-: 310 if ((packet_valid_q && see_eop))

Branches:
-1--2--3--4-StatusTests
1 1 - - Not Covered
1 0 1 - Not Covered
1 0 0 1 Not Covered
1 0 0 0 Covered T1
0 - - - Covered T1


LineNo. Expression -1-: 326 if ((!rst_ni)) -2-: 330 if (link_reset_i)

Branches:
-1--2-StatusTests
1 - Covered T1
0 1 Not Covered
0 0 Covered T1


LineNo. Expression -1-: 347 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1
0 Covered T1


LineNo. Expression -1-: 370 case (line_history_q[3:0])

Branches:
-1-StatusTests
4'b0101 Not Covered
4'b0110 Not Covered
4'b1001 Not Covered
4'b1010 Covered T1
default Covered T1


LineNo. Expression -1-: 378 if ((packet_valid_q && line_state_valid)) -2-: 379 case (line_history_q[3:0])

Branches:
-1--2-StatusTests
1 4'b0101 Not Covered
1 4'b0110 Not Covered
1 4'b1001 Not Covered
1 4'b1010 Not Covered
1 default Not Covered
0 - Covered T1


LineNo. Expression -1-: 396 if (packet_end) -2-: 398 if (dvalid_raw)

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Covered T1


LineNo. Expression -1-: 406 if ((!rst_ni)) -2-: 409 if (link_reset_i)

Branches:
-1--2-StatusTests
1 - Covered T1
0 1 Not Covered
0 0 Covered T1


LineNo. Expression -1-: 429 if (packet_start) -2-: 431 if ((bitstuff_error && dvalid_raw))

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Covered T1


LineNo. Expression -1-: 437 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1
0 Covered T1


LineNo. Expression -1-: 460 if ((dvalid && (!pid_complete))) -2-: 462 if (packet_start)

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Covered T1


LineNo. Expression -1-: 480 if (packet_start)

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1


LineNo. Expression -1-: 484 if ((dvalid && pid_complete))

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1


LineNo. Expression -1-: 502 if (packet_start)

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1


LineNo. Expression -1-: 506 if ((dvalid && pid_complete))

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1


LineNo. Expression -1-: 549 if (packet_start)

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1


LineNo. Expression -1-: 553 if ((((dvalid && pid_complete) && pkt_is_token) && (!token_payload_done)))

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1


LineNo. Expression -1-: 564 if ((token_payload_done && pkt_is_token))

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1


LineNo. Expression -1-: 594 if ((packet_start || rx_data_buffer_full))

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1


LineNo. Expression -1-: 598 if (((dvalid && pid_complete) && pkt_is_data))

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1


LineNo. Expression -1-: 608 if ((!rst_ni)) -2-: 618 if (link_reset_i)

Branches:
-1--2-StatusTests
1 - Covered T1
0 1 Not Covered
0 0 Covered T1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%