Unified Coverage Report :: Module :: usb_fs_tx

Module : usb_fs_tx

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
43.33	50.54	32.76		0.00	33.33	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_tx.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_tx	43.33	50.54	32.76		0.00	33.33	100.00

---

Module Instance : tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_tx

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
43.33	50.54	32.76		0.00	33.33	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
46.67	55.61	32.76		0.00	45.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
72.22	100.00	16.67				100.00	u_usb_fs_nb_pe

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_oe_flop	100.00	100.00				100.00
u_usb_d_flop	100.00	100.00				100.00
u_usb_d_o_flop	100.00	100.00				100.00
u_usb_dn_o_flop	100.00	100.00				100.00
u_usb_dp_o_flop	100.00	100.00				100.00
u_usb_se0_flop	100.00	100.00				100.00
u_usb_se0_o_flop	100.00	100.00				100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : usb_fs_tx

	Line No.	Total	Covered	Percent
TOTAL		184	93	50.54
ALWAYS	87	5	4	80.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	102	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	14	10	71.43
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
ALWAYS	140	70	20	28.57
ALWAYS	270	3	3	100.00
CONT_ASSIGN	278	1	1	100.00
CONT_ASSIGN	281	1	1	100.00
ALWAYS	284	5	3	60.00
ALWAYS	300	32	22	68.75
ALWAYS	344	10	4	40.00
ALWAYS	374	19	6	31.58
ALWAYS	416	8	6	75.00
ALWAYS	459	7	4	57.14
CONT_ASSIGN	507	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_tx.sv' or '../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_tx.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
87	1	1
88	1	1
90	1	1
91	0	1
93	1	1
98	1	1
101	1	1
102	1	1
103	1	1
107	1	1
108	1	1
111	1	1
112	1	1
113	1	1
114	1	1
115	1	1
117	1	1
118	0	1
119	0	1
120	0	1
121	0	1
123	1	1
124	1	1
125	1	1
126	1	1
131	1	1
132	1	1
140	1	1
141	1	1
142	1	1
143	1	1
144	1	1
145	1	1
146	1	1
147	1	1
148	1	1
150	1	1
152	1	1
153	0	1
154	0	1
155	1	1
156	0	1
			MISSING_ELSE
161	0	1
162	0	1
163	0	1
164	0	1
165	0	1
			==> MISSING_ELSE
170	0	1
171	0	1
172	0	1
174	0	1
177	0	1
178	0	1
179	0	1
			==> MISSING_ELSE
184	0	1
185	0	1
186	0	1
187	0	1
188	0	1
189	0	1
190	0	1
191	0	1
193	0	1
194	0	1
195	0	1
196	0	1
198	0	1
199	0	1
202	0	1
207	0	1
208	0	1
209	0	1
211	0	1
212	0	1
			==> MISSING_ELSE
217	0	1
218	0	1
219	0	1
220	0	1
			==> MISSING_ELSE
226	0	1
227	0	1
228	0	1
229	0	1
230	0	1
231	0	1
232	0	1
			==> MISSING_ELSE
240	1	1
245	0	1
246	0	1
248	1	1
250	1	1
251	0	1
252	0	1
256	1	1
258	1	1
259	1	1
260	1	1
262	1	1
			MISSING_ELSE
270	1	1
271	1	1
273	1	1
278	1	1
281	1	1
284	1	1
286	1	1
287	0	1
			MISSING_ELSE
290	1	1
291	0	1
			MISSING_ELSE
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
312	1	1
313	0	1
314	0	1
315	0	1
316	0	1
317	0	1
318	0	1
319	0	1
320	0	1
321	0	1
322	0	1
324	1	1
325	1	1
326	1	1
327	1	1
328	1	1
329	1	1
330	1	1
331	1	1
332	1	1
333	1	1
344	1	1
345	1	1
347	1	1
349	1	1
350	0	1
			MISSING_ELSE
355	0	1
356	0	1
			==> MISSING_ELSE
361	0	1
362	0	1
363	0	1
			==> MISSING_ELSE
374	1	1
375	1	1
376	1	1
377	1	1
379	1	1
380	0	1
381	0	1
383	1	1
384	0	1
386	0	1
388	0	1
390	0	1
392	0	1
393	0	1
396	0	1
399	0	1
403	0	1
408	0	1
409	0	1
			==> MISSING_ELSE
			MISSING_ELSE
416	1	1
417	1	1
418	1	1
420	1	1
421	0	1
422	0	1
424	1	1
425	1	1
459	1	1
460	0	1
461	0	1
462	0	1
464	1	1
465	1	1
466	1	1
507	1	1

---

Cond Coverage for Module : usb_fs_tx

	Total	Covered	Percent
Conditions	58	19	32.76
Logical	58	19	32.76
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (pkt_start_i ? pid_i : pid_q)
             -----1-----

-1-	Status	Tests
0	Covered	T1
1	Not Covered

 LINE       108
 EXPRESSION (bit_history == 6'b111111)
            -------------1------------

-1-	Status	Tests
0	Covered	T1
1	Not Covered

 LINE       131
 EXPRESSION (bit_strobe_i && (se0_shift_reg_q[1:0] == 2'b1))
             ------1-----    ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1
1	1	Not Covered

 LINE       131
 SUB-EXPRESSION (se0_shift_reg_q[1:0] == 2'b1)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1
1	Not Covered

 LINE       171
 EXPRESSION (pid_q[1:0] == 2'b11)
            ----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       226
 EXPRESSION (((!tx_osc_test_mode_i)) && byte_strobe_q)
             -----------1-----------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       270
 EXPRESSION (bit_strobe_i && ((!bitstuff)) && ((!pkt_start_i)))
             ------1-----    ------2------    --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1

 LINE       271
 EXPRESSION (bit_count_q == 3'b0)
            ----------1----------

-1-	Status	Tests
0	Covered	T1
1	Covered	T1

 LINE       281
 EXPRESSION (serial_tx_data ^ crc16_q[15])
             -------1------   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       290
 EXPRESSION (bit_strobe_i && data_payload_q && ((!bitstuff_q4)) && ((!pkt_start_i)))
             ------1-----    -------2------    --------3-------    --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Covered	T1
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Not Covered

 LINE       349
 EXPRESSION (pkt_start_i || test_mode_start)
             -----1-----    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1
0	1	Not Covered
1	0	Not Covered

 LINE       362
 EXPRESSION (bit_strobe_i && ((!serial_tx_oe)))
             ------1-----    --------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       383
 EXPRESSION (bit_strobe_i && out_nrzi_en)
             ------1-----    -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1
1	1	Not Covered

 LINE       431
 EXPRESSION (link_reset_i ? 1'b0 : oe_d)
             ------1-----

-1-	Status	Tests
0	Covered	T1
1	Not Covered

 LINE       440
 EXPRESSION (link_reset_i ? 1'b0 : usb_d_d)
             ------1-----

-1-	Status	Tests
0	Covered	T1
1	Not Covered

 LINE       447
 EXPRESSION (link_reset_i ? 1'b0 : usb_se0_d)
             ------1-----

-1-	Status	Tests
0	Covered	T1
1	Not Covered

 LINE       461
 EXPRESSION (1'b0 ^ cfg_pinflip_i)
             --1-   ------2------

-1-	-2-	Status	Tests
-	0	Not Covered
-	1	Not Covered

 LINE       462
 EXPRESSION (1'b1 ^ cfg_pinflip_i)
             --1-   ------2------

-1-	-2-	Status	Tests
-	0	Not Covered
-	1	Not Covered

 LINE       465
 EXPRESSION ((cfg_pinflip_i ? ((~usb_d_d)) : usb_d_d) & ((~usb_se0_d)))
             --------------------1-------------------   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1

 LINE       465
 SUB-EXPRESSION (cfg_pinflip_i ? ((~usb_d_d)) : usb_d_d)
                 ------1------

-1-	Status	Tests
0	Covered	T1
1	Not Covered

 LINE       466
 EXPRESSION ((cfg_pinflip_i ? usb_d_d : ((~usb_d_d))) & ((~usb_se0_d)))
             --------------------1-------------------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1
1	0	Not Covered
1	1	Not Covered

 LINE       466
 SUB-EXPRESSION (cfg_pinflip_i ? usb_d_d : ((~usb_d_d)))
                 ------1------

-1-	Status	Tests
0	Covered	T1
1	Not Covered

---

FSM Coverage for Module : usb_fs_tx

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	1	14.29	(Not included in score)
Transitions	13	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
Crc161	193	Not Covered
DataOrCrc160	172	Not Covered
Eop	174	Not Covered
Idle	313	Covered	T1
OscTest	153	Not Covered
Pid	162	Not Covered
Sync	156	Not Covered

transitions	Line No.	Covered	Tests
Crc161->Eop	208	Not Covered
Crc161->Idle	313	Not Covered
DataOrCrc160->Crc161	193	Not Covered
DataOrCrc160->Idle	313	Not Covered
Eop->Idle	313	Not Covered
Idle->OscTest	153	Not Covered
Idle->Sync	156	Not Covered
OscTest->Idle	313	Not Covered
Pid->DataOrCrc160	172	Not Covered
Pid->Eop	174	Not Covered
Pid->Idle	313	Not Covered
Sync->Idle	313	Not Covered
Sync->Pid	162	Not Covered

Summary for FSM :: out_state_q

	Total	Covered	Percent
States	3	1	33.33	(Not included in score)
Transitions	4	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: out_state_q

---

states	Line No.	Covered	Tests
OsIdle	422	Covered	T1
OsTransmit	356	Not Covered
OsWaitByte	350	Not Covered

transitions	Line No.	Covered	Tests
OsIdle->OsWaitByte	350	Not Covered
OsTransmit->OsIdle	422	Not Covered
OsWaitByte->OsIdle	422	Not Covered
OsWaitByte->OsTransmit	356	Not Covered

---

Branch Coverage for Module : usb_fs_tx

	Line No.	Total	Covered	Percent
Branches		66	22	33.33
TERNARY	98	2	1	50.00
TERNARY	431	2	1	50.00
TERNARY	440	2	1	50.00
TERNARY	447	2	1	50.00
IF	87	3	2	66.67
IF	111	3	2	66.67
CASE	150	19	1	5.26
IF	240	4	2	50.00
IF	270	2	2	100.00
IF	286	2	1	50.00
IF	290	2	1	50.00
IF	300	3	2	66.67
CASE	347	7	1	14.29
IF	379	8	1	12.50
IF	416	3	2	66.67
IF	459	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_tx.sv' or '../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_tx.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	98	(pkt_start_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1

	LineNo.	Expression
-1-:	431	(link_reset_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1

	LineNo.	Expression
-1-:	440	(link_reset_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1

	LineNo.	Expression
-1-:	447	(link_reset_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1

	LineNo.	Expression
-1-:	87	if ((!rst_ni))
-2-:	90	if (link_reset_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1
0	1	Not Covered
0	0	Covered	T1

	LineNo.	Expression
-1-:	111	if ((!rst_ni))
-2-:	117	if (link_reset_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1
0	1	Not Covered
0	0	Covered	T1

	LineNo.	Expression
-1-:	150	case (state_q)
-2-:	152	if (tx_osc_test_mode_i)
-3-:	155	if (pkt_start_i)
-4-:	161	if (byte_strobe_q)
-5-:	170	if (byte_strobe_q)
-6-:	171	if ((pid_q[1:0] == 2'b11))
-7-:	184	if (byte_strobe_q)
-8-:	185	if (tx_data_avail_i)
-9-:	207	if (byte_strobe_q)
-10-:	217	if (byte_strobe_q)
-11-:	226	if (((!tx_osc_test_mode_i) && byte_strobe_q))
-12-:	229	if (byte_strobe_q)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	Not Covered
Idle	0	1	-	-	-	-	-	-	-	-	-	Not Covered
Idle	0	0	-	-	-	-	-	-	-	-	-	Covered	T1
Sync	-	-	1	-	-	-	-	-	-	-	-	Not Covered
Sync	-	-	0	-	-	-	-	-	-	-	-	Not Covered
Pid	-	-	-	1	1	-	-	-	-	-	-	Not Covered
Pid	-	-	-	1	0	-	-	-	-	-	-	Not Covered
Pid	-	-	-	0	-	-	-	-	-	-	-	Not Covered
DataOrCrc160	-	-	-	-	-	1	1	-	-	-	-	Not Covered
DataOrCrc160	-	-	-	-	-	1	0	-	-	-	-	Not Covered
DataOrCrc160	-	-	-	-	-	0	-	-	-	-	-	Not Covered
Crc161	-	-	-	-	-	-	-	1	-	-	-	Not Covered
Crc161	-	-	-	-	-	-	-	0	-	-	-	Not Covered
Eop	-	-	-	-	-	-	-	-	1	-	-	Not Covered
Eop	-	-	-	-	-	-	-	-	0	-	-	Not Covered
OscTest	-	-	-	-	-	-	-	-	-	1	-	Not Covered
OscTest	-	-	-	-	-	-	-	-	-	0	1	Not Covered
OscTest	-	-	-	-	-	-	-	-	-	0	0	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	240	if (pkt_start_i)
-2-:	248	if (bit_strobe_i)
-3-:	250	if (bitstuff)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	1	Not Covered
0	1	0	Covered	T1
0	0	-	Covered	T1

	LineNo.	Expression
-1-:	270	if (((bit_strobe_i && (!bitstuff)) && (!pkt_start_i)))

Branches:

-1-	Status	Tests
1	Covered	T1
0	Covered	T1

	LineNo.	Expression
-1-:	286	if (pkt_start_i)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1

	LineNo.	Expression
-1-:	290	if ((((bit_strobe_i && data_payload_q) && (!bitstuff_q4)) && (!pkt_start_i)))

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1

	LineNo.	Expression
-1-:	300	if ((!rst_ni))
-2-:	312	if (link_reset_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1
0	1	Not Covered
0	0	Covered	T1

	LineNo.	Expression
-1-:	347	case (out_state_q)
-2-:	349	if ((pkt_start_i || test_mode_start))
-3-:	355	if (byte_strobe_q)
-4-:	362	if ((bit_strobe_i && (!serial_tx_oe)))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
OsIdle	1	-	-	Not Covered
OsIdle	0	-	-	Covered	T1
OsWaitByte	-	1	-	Not Covered
OsWaitByte	-	0	-	Not Covered
OsTransmit	-	-	1	Not Covered
OsTransmit	-	-	0	Not Covered
default	-	-	-	Not Covered

	LineNo.	Expression
-1-:	379	if (pkt_start_i)
-2-:	383	if ((bit_strobe_i && out_nrzi_en))
-3-:	386	if (serial_tx_se0)
-4-:	390	if (dp_eop_q[0])
-5-:	399	if (serial_tx_data)
-6-:	408	if ((!oe_d))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
1	-	-	-	-	-	Not Covered
0	1	1	1	-	-	Not Covered
0	1	1	0	-	-	Not Covered
0	1	0	-	1	-	Not Covered
0	1	0	-	0	-	Not Covered
0	1	-	-	-	1	Not Covered
0	1	-	-	-	0	Not Covered
0	0	-	-	-	-	Covered	T1

	LineNo.	Expression
-1-:	416	if ((!rst_ni))
-2-:	420	if (link_reset_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1
0	1	Not Covered
0	0	Covered	T1

	LineNo.	Expression
-1-:	459	if (link_reset_i)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1

---

Assert Coverage for Module : usb_fs_tx

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutStateValid_A	10725	9119	0	0
StateValid_A	10725	9119	0	0

OutStateValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10725	9119	0	0
T1	10725	9119	0	0

StateValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10725	9119	0	0
T1	10725	9119	0	0