Line Coverage for Module :
prim_reg_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
ALWAYS | 60 | 6 | 6 | 100.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
ALWAYS | 104 | 9 | 9 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
|
|
|
MISSING_ELSE |
74 |
1 |
1 |
98 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
139 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
187 |
1 |
1 |
Cond Coverage for Module :
prim_reg_cdc
| Total | Covered | Percent |
Conditions | 14 | 10 | 71.43 |
Logical | 14 | 10 | 71.43 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T2,T3,T6 |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T6 |
1 | 1 | Covered | T2,T3,T6 |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T2,T3,T6 |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T2,T3,T6 |
1 | 1 | Covered | T2,T3,T6 |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
Branch Coverage for Module :
prim_reg_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
60 |
4 |
4 |
100.00 |
IF |
104 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_src_ni))
-2-: 62 if (src_req)
-3-: 64 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T2,T3,T6 |
0 |
0 |
1 |
Covered |
T2,T3,T6 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 104 if ((!rst_src_ni))
-2-: 107 if (src_req)
-3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T2,T3,T6 |
0 |
0 |
1 |
Covered |
T2,T3,T6 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_reg_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1444682 |
10218 |
0 |
0 |
T2 |
2364 |
17 |
0 |
0 |
T3 |
2627 |
12 |
0 |
0 |
T6 |
2079 |
66 |
0 |
0 |
T7 |
3017 |
15 |
0 |
0 |
T8 |
1332 |
7 |
0 |
0 |
T10 |
1502 |
8 |
0 |
0 |
T11 |
2067 |
13 |
0 |
0 |
T27 |
2961 |
135 |
0 |
0 |
T28 |
1796 |
120 |
0 |
0 |
T29 |
5167 |
109 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
393406 |
342496 |
0 |
0 |
T1 |
8042 |
4892 |
0 |
0 |
T2 |
1772 |
1592 |
0 |
0 |
T3 |
1094 |
892 |
0 |
0 |
T4 |
1298 |
1090 |
0 |
0 |
T5 |
6454 |
6322 |
0 |
0 |
T6 |
690 |
492 |
0 |
0 |
T7 |
2638 |
2438 |
0 |
0 |
T8 |
1050 |
860 |
0 |
0 |
T9 |
1992 |
1852 |
0 |
0 |
T10 |
1064 |
782 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1444682 |
569 |
0 |
0 |
T2 |
2364 |
2 |
0 |
0 |
T3 |
2627 |
1 |
0 |
0 |
T6 |
2079 |
4 |
0 |
0 |
T7 |
3017 |
2 |
0 |
0 |
T8 |
1332 |
1 |
0 |
0 |
T10 |
1502 |
1 |
0 |
0 |
T11 |
2067 |
1 |
0 |
0 |
T27 |
2961 |
16 |
0 |
0 |
T28 |
1796 |
12 |
0 |
0 |
T29 |
5167 |
15 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1444682 |
1391604 |
0 |
0 |
T1 |
21450 |
18238 |
0 |
0 |
T2 |
4728 |
4474 |
0 |
0 |
T3 |
5254 |
5034 |
0 |
0 |
T4 |
2834 |
2678 |
0 |
0 |
T5 |
17216 |
17116 |
0 |
0 |
T6 |
4158 |
4016 |
0 |
0 |
T7 |
6034 |
5846 |
0 |
0 |
T8 |
2664 |
2542 |
0 |
0 |
T9 |
4782 |
4554 |
0 |
0 |
T10 |
3004 |
2688 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 17 | 14 | 82.35 |
CONT_ASSIGN | 54 | 0 | 0 | |
ALWAYS | 60 | 5 | 4 | 80.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
ALWAYS | 104 | 7 | 5 | 71.43 |
CONT_ASSIGN | 139 | 0 | 0 | |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
|
unreachable |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
|
unreachable |
64 |
1 |
1 |
65 |
0 |
1 |
|
|
|
MISSING_ELSE |
74 |
1 |
1 |
98 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
112 |
|
unreachable |
113 |
|
unreachable |
114 |
1 |
1 |
123 |
0 |
1 |
124 |
0 |
1 |
|
|
|
MISSING_ELSE |
139 |
|
unreachable |
144 |
1 |
1 |
145 |
1 |
1 |
187 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc
| Total | Covered | Percent |
Conditions | 13 | 4 | 30.77 |
Logical | 13 | 4 | 30.77 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
Branch Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
4 |
66.67 |
IF |
60 |
3 |
2 |
66.67 |
IF |
104 |
3 |
2 |
66.67 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_src_ni))
-2-: 62 if (src_req)
-3-: 64 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Unreachable |
|
0 |
0 |
1 |
Not Covered |
|
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 104 if ((!rst_src_ni))
-2-: 107 if (src_req)
-3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Unreachable |
|
0 |
0 |
1 |
Not Covered |
|
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
722341 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
196703 |
171248 |
0 |
0 |
T1 |
4021 |
2446 |
0 |
0 |
T2 |
886 |
796 |
0 |
0 |
T3 |
547 |
446 |
0 |
0 |
T4 |
649 |
545 |
0 |
0 |
T5 |
3227 |
3161 |
0 |
0 |
T6 |
345 |
246 |
0 |
0 |
T7 |
1319 |
1219 |
0 |
0 |
T8 |
525 |
430 |
0 |
0 |
T9 |
996 |
926 |
0 |
0 |
T10 |
532 |
391 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
722341 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
722341 |
695802 |
0 |
0 |
T1 |
10725 |
9119 |
0 |
0 |
T2 |
2364 |
2237 |
0 |
0 |
T3 |
2627 |
2517 |
0 |
0 |
T4 |
1417 |
1339 |
0 |
0 |
T5 |
8608 |
8558 |
0 |
0 |
T6 |
2079 |
2008 |
0 |
0 |
T7 |
3017 |
2923 |
0 |
0 |
T8 |
1332 |
1271 |
0 |
0 |
T9 |
2391 |
2277 |
0 |
0 |
T10 |
1502 |
1344 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
ALWAYS | 60 | 6 | 6 | 100.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
ALWAYS | 104 | 9 | 9 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
|
|
|
MISSING_ELSE |
74 |
1 |
1 |
98 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
139 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
187 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T2,T3,T6 |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T6 |
1 | 1 | Covered | T2,T3,T6 |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T2,T3,T6 |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T2,T3,T6 |
1 | 1 | Covered | T2,T3,T6 |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
60 |
4 |
4 |
100.00 |
IF |
104 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_src_ni))
-2-: 62 if (src_req)
-3-: 64 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T2,T3,T6 |
0 |
0 |
1 |
Covered |
T2,T3,T6 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 104 if ((!rst_src_ni))
-2-: 107 if (src_req)
-3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T2,T3,T6 |
0 |
0 |
1 |
Covered |
T2,T3,T6 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
722341 |
10218 |
0 |
0 |
T2 |
2364 |
17 |
0 |
0 |
T3 |
2627 |
12 |
0 |
0 |
T6 |
2079 |
66 |
0 |
0 |
T7 |
3017 |
15 |
0 |
0 |
T8 |
1332 |
7 |
0 |
0 |
T10 |
1502 |
8 |
0 |
0 |
T11 |
2067 |
13 |
0 |
0 |
T27 |
2961 |
135 |
0 |
0 |
T28 |
1796 |
120 |
0 |
0 |
T29 |
5167 |
109 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
196703 |
171248 |
0 |
0 |
T1 |
4021 |
2446 |
0 |
0 |
T2 |
886 |
796 |
0 |
0 |
T3 |
547 |
446 |
0 |
0 |
T4 |
649 |
545 |
0 |
0 |
T5 |
3227 |
3161 |
0 |
0 |
T6 |
345 |
246 |
0 |
0 |
T7 |
1319 |
1219 |
0 |
0 |
T8 |
525 |
430 |
0 |
0 |
T9 |
996 |
926 |
0 |
0 |
T10 |
532 |
391 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
722341 |
569 |
0 |
0 |
T2 |
2364 |
2 |
0 |
0 |
T3 |
2627 |
1 |
0 |
0 |
T6 |
2079 |
4 |
0 |
0 |
T7 |
3017 |
2 |
0 |
0 |
T8 |
1332 |
1 |
0 |
0 |
T10 |
1502 |
1 |
0 |
0 |
T11 |
2067 |
1 |
0 |
0 |
T27 |
2961 |
16 |
0 |
0 |
T28 |
1796 |
12 |
0 |
0 |
T29 |
5167 |
15 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
722341 |
695802 |
0 |
0 |
T1 |
10725 |
9119 |
0 |
0 |
T2 |
2364 |
2237 |
0 |
0 |
T3 |
2627 |
2517 |
0 |
0 |
T4 |
1417 |
1339 |
0 |
0 |
T5 |
8608 |
8558 |
0 |
0 |
T6 |
2079 |
2008 |
0 |
0 |
T7 |
3017 |
2923 |
0 |
0 |
T8 |
1332 |
1271 |
0 |
0 |
T9 |
2391 |
2277 |
0 |
0 |
T10 |
1502 |
1344 |
0 |
0 |