Unified Coverage Report :: Module :: usb_fs_nb_in_pe

Module : usb_fs_nb_in_pe

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
41.55	52.83	17.14		0.00	37.78	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_in_pe.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_nb_in_pe	41.55	52.83	17.14		0.00	37.78	100.00

---

Module Instance : tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_nb_in_pe

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
41.55	52.83	17.14		0.00	37.78	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
41.55	52.83	17.14		0.00	37.78	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
72.22	100.00	16.67				100.00	u_usb_fs_nb_pe

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : usb_fs_nb_in_pe

	Line No.	Total	Covered	Percent
TOTAL		106	56	52.83
CONT_ASSIGN	102	1	1	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
ALWAYS	166	49	9	18.37
ALWAYS	268	3	3	100.00
ALWAYS	276	3	3	100.00
ALWAYS	285	8	6	75.00
ALWAYS	298	6	4	66.67
ALWAYS	310	7	5	71.43
ALWAYS	324	6	4	66.67
ALWAYS	336	5	4	80.00
ALWAYS	346	5	4	80.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_in_pe.sv' or '../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_in_pe.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
102	1	1
116	1	1
117	1	1
119	1	1
125	1	1
129	1	1
133	1	1
139	1	1
140	1	1
147	1	1
148	1	1
151	1	1
153	1	1
156	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
171	1	1
172	1	1
174	1	1
175	0	1
178	1	1
183	0	1
185	0	1
190	0	1
191	0	1
192	0	1
193	0	1
194	0	1
195	0	1
196	0	1
197	0	1
199	0	1
200	0	1
206	0	1
207	0	1
208	0	1
209	0	1
211	0	1
212	0	1
214	0	1
218	0	1
223	0	1
224	0	1
			==> MISSING_ELSE
232	0	1
234	0	1
235	0	1
236	0	1
237	0	1
238	0	1
240	0	1
245	0	1
246	0	1
247	0	1
248	0	1
249	0	1
250	0	1
251	0	1
252	0	1
253	0	1
255	0	1
268	1	1
269	1	1
271	1	1
276	1	1
277	1	1
279	1	1
285	1	1
286	1	1
287	1	1
288	1	1
289	1	1
290	1	1
292	0	1
293	0	1
298	1	1
299	1	1
301	1	1
302	1	1
303	0	1
304	0	1
			==> MISSING_ELSE
310	1	1
311	1	1
312	1	1
314	1	1
315	0	1
316	0	1
318	1	1
324	1	1
326	1	1
327	0	1
328	1	1
329	0	1
			MISSING_ELSE
332	1	1
336	1	1
337	1	1
338	1	1
339	0	1
341	1	1
346	1	1
347	1	1
349	1	1
350	0	1
352	1	1

---

Cond Coverage for Module : usb_fs_nb_in_pe

	Total	Covered	Percent
Conditions	70	12	17.14
Logical	70	12	17.14
Non-Logical	0	0
Event	0	0

 LINE       119
 EXPRESSION (rx_pkt_end_i && rx_pkt_valid_i && (rx_pid_type == UsbPidTypeToken) && (rx_addr_i == dev_addr_i))
             ------1-----    -------2------    ----------------3---------------    ------------4------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Not Covered

 LINE       119
 SUB-EXPRESSION (rx_pid_type == UsbPidTypeToken)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1
1	Not Covered

 LINE       119
 SUB-EXPRESSION (rx_addr_i == dev_addr_i)
                ------------1------------

-1-	Status	Tests
0	Covered	T1
1	Covered	T1

 LINE       125
 EXPRESSION (token_received && (rx_pid == UsbPidSetup))
             -------1------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       125
 SUB-EXPRESSION (rx_pid == UsbPidSetup)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1
1	Not Covered

 LINE       129
 EXPRESSION (token_received && (rx_pid == UsbPidIn))
             -------1------    ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       129
 SUB-EXPRESSION (rx_pid == UsbPidIn)
                ----------1---------

-1-	Status	Tests
0	Covered	T1
1	Not Covered

 LINE       133
 EXPRESSION (rx_pkt_end_i && rx_pkt_valid_i && (rx_pid == UsbPidAck))
             ------1-----    -------2------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       133
 SUB-EXPRESSION (rx_pid == UsbPidAck)
                ----------1----------

-1-	Status	Tests
0	Covered	T1
1	Not Covered

 LINE       140
 EXPRESSION (ep_in_hw ? rx_endp_i : '0)
             ----1---

-1-	Status	Tests
0	Not Covered
1	Covered	T1

 LINE       151
 EXPRESSION (in_ep_enabled_i[in_ep_index_d] & ep_in_hw)
             ---------------1--------------   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1
1	0	Not Covered
1	1	Not Covered

 LINE       153
 EXPRESSION (in_ep_has_data_i[in_ep_index] & ((~in_ep_data_done_i[in_ep_index])))
             --------------1--------------   -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       156
 EXPRESSION ((logic'((in_xact_state == StSendData))) & more_data_to_send)
             -------------------1-------------------   --------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       174
 EXPRESSION (ep_active && in_token_received)
             ----1----    --------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       206
 EXPRESSION (((!more_data_to_send)) || (((&in_ep_get_addr_o)) && tx_data_get_i))
             -----------1----------    --------------------2-------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       206
 SUB-EXPRESSION (((&in_ep_get_addr_o)) && tx_data_get_i)
                 ----------1----------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       236
 EXPRESSION (timeout_cntdown_q == '0)
            ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       288
 EXPRESSION (link_reset_i || ((!link_active_i)))
             ------1-----    ---------2--------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T1
1	0	Not Covered

 LINE       301
 EXPRESSION (in_xact_state == StIdle)
            ------------1------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1

 LINE       303
 EXPRESSION ((in_xact_state == StSendData) && tx_data_get_i)
             --------------1--------------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       303
 SUB-EXPRESSION (in_xact_state == StSendData)
                --------------1--------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       326
 EXPRESSION (setup_token_received && ep_active)
             ----------1---------    ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       328
 EXPRESSION ((in_xact_state == StWaitAck) && ack_received)
             --------------1-------------    ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       328
 SUB-EXPRESSION (in_xact_state == StWaitAck)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1
1	Not Covered

 LINE       349
 EXPRESSION ((in_xact_state == StSendData) && tx_data_get_i)
             --------------1--------------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       349
 SUB-EXPRESSION (in_xact_state == StSendData)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1
1	Not Covered

---

FSM Coverage for Module : usb_fs_nb_in_pe

Summary for FSM :: in_xact_state

	Total	Covered	Percent
States	6	1	16.67	(Not included in score)
Transitions	12	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: in_xact_state

---

states	Line No.	Covered	Tests
StIdle	289	Covered	T1
StRcvdIn	175	Not Covered
StSendData	190	Not Covered
StWaitAck	235	Not Covered
StWaitAckStart	212	Not Covered
StWaitTxEnd	214	Not Covered

transitions	Line No.	Covered	Tests
StIdle->StRcvdIn	175	Not Covered
StRcvdIn->StIdle	289	Not Covered
StRcvdIn->StSendData	190	Not Covered
StSendData->StIdle	289	Not Covered
StSendData->StWaitAckStart	212	Not Covered
StSendData->StWaitTxEnd	214	Not Covered
StWaitAck->StIdle	289	Not Covered
StWaitAck->StRcvdIn	249	Not Covered
StWaitAckStart->StIdle	289	Not Covered
StWaitAckStart->StWaitAck	235	Not Covered
StWaitTxEnd->StIdle	289	Not Covered
StWaitTxEnd->StWaitAckStart	224	Not Covered

---

Branch Coverage for Module : usb_fs_nb_in_pe

	Line No.	Total	Covered	Percent
Branches		45	17	37.78
TERNARY	140	2	1	50.00
CASE	172	20	1	5.00
IF	268	2	2	100.00
IF	276	2	2	100.00
IF	285	3	2	66.67
IF	298	4	2	50.00
IF	310	3	2	66.67
IF	326	3	1	33.33
IF	336	3	2	66.67
IF	346	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_in_pe.sv' or '../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_in_pe.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	140	(ep_in_hw) ? 

Branches:

-1-	Status	Tests
1	Covered	T1
0	Not Covered

	LineNo.	Expression
-1-:	172	case (in_xact_state)
-2-:	174	if ((ep_active && in_token_received))
-3-:	185	if (in_ep_iso_i[in_ep_index])
-4-:	192	if (in_ep_stall_i[in_ep_index])
-5-:	195	if (in_ep_has_data_i[in_ep_index])
-6-:	206	if (((!more_data_to_send) || ((&in_ep_get_addr_o) && tx_data_get_i)))
-7-:	207	if (in_ep_iso_i[in_ep_index])
-8-:	211	if (tx_pkt_end_i)
-9-:	223	if (tx_pkt_end_i)
-10-:	234	if (rx_pkt_start_i)
-11-:	236	if ((timeout_cntdown_q == '0))
-12-:	245	if (ack_received)
-13-:	248	if (in_token_received)
-14-:	251	if (rx_pkt_end_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StIdle	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1
StRcvdIn	-	1	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StRcvdIn	-	0	1	-	-	-	-	-	-	-	-	-	-	Not Covered
StRcvdIn	-	0	0	1	-	-	-	-	-	-	-	-	-	Not Covered
StRcvdIn	-	0	0	0	-	-	-	-	-	-	-	-	-	Not Covered
StSendData	-	-	-	-	1	1	-	-	-	-	-	-	-	Not Covered
StSendData	-	-	-	-	1	0	1	-	-	-	-	-	-	Not Covered
StSendData	-	-	-	-	1	0	0	-	-	-	-	-	-	Not Covered
StSendData	-	-	-	-	0	-	-	-	-	-	-	-	-	Not Covered
StWaitTxEnd	-	-	-	-	-	-	-	1	-	-	-	-	-	Not Covered
StWaitTxEnd	-	-	-	-	-	-	-	0	-	-	-	-	-	Not Covered
StWaitAckStart	-	-	-	-	-	-	-	-	1	-	-	-	-	Not Covered
StWaitAckStart	-	-	-	-	-	-	-	-	0	1	-	-	-	Not Covered
StWaitAckStart	-	-	-	-	-	-	-	-	0	0	-	-	-	Not Covered
StWaitAck	-	-	-	-	-	-	-	-	-	-	1	-	-	Not Covered
StWaitAck	-	-	-	-	-	-	-	-	-	-	0	1	-	Not Covered
StWaitAck	-	-	-	-	-	-	-	-	-	-	0	0	1	Not Covered
StWaitAck	-	-	-	-	-	-	-	-	-	-	0	0	0	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	268	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1
0	Covered	T1

	LineNo.	Expression
-1-:	276	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1
0	Covered	T1

	LineNo.	Expression
-1-:	285	if ((!rst_ni))
-2-:	288	if ((link_reset_i || (!link_active_i)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1
0	1	Covered	T1
0	0	Not Covered

	LineNo.	Expression
-1-:	298	if ((!rst_ni))
-2-:	301	if ((in_xact_state == StIdle))
-3-:	303	if (((in_xact_state == StSendData) && tx_data_get_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1
0	1	-	Covered	T1
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	310	if ((!rst_ni))
-2-:	314	if (in_token_received)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1
0	1	Not Covered
0	0	Covered	T1

	LineNo.	Expression
-1-:	326	if ((setup_token_received && ep_active))
-2-:	328	if (((in_xact_state == StWaitAck) && ack_received))

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Covered	T1

	LineNo.	Expression
-1-:	336	if ((!rst_ni))
-2-:	338	if (link_reset_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1
0	1	Not Covered
0	0	Covered	T1

	LineNo.	Expression
-1-:	346	if ((!rst_ni))
-2-:	349	if (((in_xact_state == StSendData) && tx_data_get_i))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1
0	1	Not Covered
0	0	Covered	T1

---

Assert Coverage for Module : usb_fs_nb_in_pe

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
InXactStateValid_A	10725	9119	0	0

InXactStateValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10725	9119	0	0
T1	10725	9119	0	0