Module Definition
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Module Instance : tb.dut.gen_no_stubbed_memory.u_memory_2p.i_prim_ram_2p_async_adv.u_mem.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
16.24 15.38 33.33 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
16.24 15.38 33.33 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_mem


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_generic_ram_2p
Line No.TotalCoveredPercent
TOTAL13215.38
CONT_ASSIGN49100.00
CONT_ASSIGN6000
CONT_ASSIGN6000
CONT_ASSIGN6000
CONT_ASSIGN6000
CONT_ASSIGN6100
CONT_ASSIGN6100
CONT_ASSIGN6100
CONT_ASSIGN6100
ALWAYS766116.67
ALWAYS916116.67
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_2p_0/rtl/prim_generic_ram_2p.sv' or '../src/lowrisc_prim_generic_ram_2p_0/rtl/prim_generic_ram_2p.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 0 1
60 unreachable
61 unreachable
76 1 1
77 0 1
78 0 1
79 0 1
80 0 1
==> MISSING_ELSE
85 0 1
MISSING_ELSE
91 1 1
92 0 1
93 0 1
94 0 1
95 0 1
==> MISSING_ELSE
100 0 1
MISSING_ELSE


Branch Coverage for Module : prim_generic_ram_2p
Line No.TotalCoveredPercent
Branches 6 2 33.33
IF 76 3 1 33.33
IF 91 3 1 33.33

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_2p_0/rtl/prim_generic_ram_2p.sv' or '../src/lowrisc_prim_generic_ram_2p_0/rtl/prim_generic_ram_2p.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 76 if (a_req_i) -2-: 77 if (a_write_i)

Branches:
-1--2-StatusTests
1 1 Not Covered
1 0 Not Covered
0 - Covered T1


LineNo. Expression -1-: 91 if (b_req_i) -2-: 92 if (b_write_i)

Branches:
-1--2-StatusTests
1 1 Not Covered
1 0 Not Covered
0 - Covered T1


Assert Coverage for Module : prim_generic_ram_2p
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 8 8 100.00 0 0.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 8 8 100.00 0 0.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_wmask[0].MaskCheckPortA_A 10725 0 0 0
gen_wmask[0].MaskCheckPortB_A 10725 0 0 0
gen_wmask[1].MaskCheckPortA_A 10725 0 0 0
gen_wmask[1].MaskCheckPortB_A 10725 0 0 0
gen_wmask[2].MaskCheckPortA_A 10725 0 0 0
gen_wmask[2].MaskCheckPortB_A 10725 0 0 0
gen_wmask[3].MaskCheckPortA_A 10725 0 0 0
gen_wmask[3].MaskCheckPortB_A 10725 0 0 0


gen_wmask[0].MaskCheckPortA_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10725 0 0 0

gen_wmask[0].MaskCheckPortB_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10725 0 0 0

gen_wmask[1].MaskCheckPortA_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10725 0 0 0

gen_wmask[1].MaskCheckPortB_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10725 0 0 0

gen_wmask[2].MaskCheckPortA_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10725 0 0 0

gen_wmask[2].MaskCheckPortB_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10725 0 0 0

gen_wmask[3].MaskCheckPortA_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10725 0 0 0

gen_wmask[3].MaskCheckPortB_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10725 0 0 0

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