Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=16}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=16}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=16}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	68	0	68	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=16}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	17	0	17	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=16}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	68	0	68	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	276	1		T6	8		T7	2		T9	2
all_values[1]	276	1		T6	8		T7	2		T9	2
all_values[2]	276	1		T6	8		T7	2		T9	2
all_values[3]	276	1		T6	8		T7	2		T9	2
all_values[4]	276	1		T6	8		T7	2		T9	2
all_values[5]	276	1		T6	8		T7	2		T9	2
all_values[6]	276	1		T6	8		T7	2		T9	2
all_values[7]	276	1		T6	8		T7	2		T9	2
all_values[8]	276	1		T6	8		T7	2		T9	2
all_values[9]	276	1		T6	8		T7	2		T9	2
all_values[10]	276	1		T6	8		T7	2		T9	2
all_values[11]	276	1		T6	8		T7	2		T9	2
all_values[12]	276	1		T6	8		T7	2		T9	2
all_values[13]	276	1		T6	8		T7	2		T9	2
all_values[14]	276	1		T6	8		T7	2		T9	2
all_values[15]	276	1		T6	8		T7	2		T9	2
all_values[16]	276	1		T6	8		T7	2		T9	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2725	1		T6	67		T7	34		T9	34
auto[1]	1967	1		T6	69		T32	44		T29	53

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1357	1		T6	23		T7	34		T9	34
auto[1]	3335	1		T6	113		T32	60		T29	115

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	68	0	68	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	57	1		T6	1		T7	2		T9	2
all_values[0]	auto[0]	auto[1]	111	1		T6	1		T29	6		T31	1
all_values[0]	auto[1]	auto[0]	21	1		T6	1		T32	5		T70	3
all_values[0]	auto[1]	auto[1]	87	1		T6	5		T29	2		T30	4
all_values[1]	auto[0]	auto[0]	68	1		T6	2		T7	2		T9	2
all_values[1]	auto[0]	auto[1]	98	1		T6	1		T32	3		T29	7
all_values[1]	auto[1]	auto[0]	15	1		T6	1		T30	2		T31	1
all_values[1]	auto[1]	auto[1]	95	1		T6	4		T29	1		T31	1
all_values[2]	auto[0]	auto[0]	49	1		T6	2		T7	2		T9	2
all_values[2]	auto[0]	auto[1]	103	1		T32	4		T29	7		T30	5
all_values[2]	auto[1]	auto[0]	16	1		T6	2		T31	1		T70	1
all_values[2]	auto[1]	auto[1]	108	1		T6	4		T32	1		T29	1
all_values[3]	auto[0]	auto[0]	62	1		T6	1		T7	2		T9	2
all_values[3]	auto[0]	auto[1]	93	1		T6	1		T29	5		T30	1
all_values[3]	auto[1]	auto[0]	20	1		T32	1		T30	1		T71	4
all_values[3]	auto[1]	auto[1]	101	1		T6	6		T29	3		T30	3
all_values[4]	auto[0]	auto[0]	57	1		T7	2		T9	2		T12	2
all_values[4]	auto[0]	auto[1]	99	1		T6	7		T32	1		T29	6
all_values[4]	auto[1]	auto[0]	17	1		T30	1		T70	2		T72	1
all_values[4]	auto[1]	auto[1]	103	1		T6	1		T32	4		T29	1
all_values[5]	auto[0]	auto[0]	69	1		T7	2		T9	2		T12	2
all_values[5]	auto[0]	auto[1]	86	1		T6	4		T32	1		T31	3
all_values[5]	auto[1]	auto[0]	26	1		T29	2		T30	4		T31	1
all_values[5]	auto[1]	auto[1]	95	1		T6	4		T32	4		T33	4
all_values[6]	auto[0]	auto[0]	59	1		T6	1		T7	2		T9	2
all_values[6]	auto[0]	auto[1]	104	1		T6	3		T32	1		T29	4
all_values[6]	auto[1]	auto[0]	17	1		T29	1		T30	1		T73	3
all_values[6]	auto[1]	auto[1]	96	1		T6	4		T32	4		T29	3
all_values[7]	auto[0]	auto[0]	61	1		T7	2		T9	2		T12	2
all_values[7]	auto[0]	auto[1]	107	1		T6	6		T32	4		T29	4
all_values[7]	auto[1]	auto[0]	19	1		T29	2		T30	2		T31	1
all_values[7]	auto[1]	auto[1]	89	1		T6	2		T32	1		T33	3
all_values[8]	auto[0]	auto[0]	68	1		T6	1		T7	2		T9	2
all_values[8]	auto[0]	auto[1]	82	1		T6	1		T32	3		T29	4
all_values[8]	auto[1]	auto[0]	19	1		T6	2		T32	1		T73	1
all_values[8]	auto[1]	auto[1]	107	1		T6	4		T32	1		T29	4
all_values[9]	auto[0]	auto[0]	61	1		T7	2		T9	2		T12	2
all_values[9]	auto[0]	auto[1]	99	1		T6	5		T32	1		T29	5
all_values[9]	auto[1]	auto[0]	22	1		T31	1		T73	1		T70	1
all_values[9]	auto[1]	auto[1]	94	1		T6	3		T32	4		T29	2
all_values[10]	auto[0]	auto[0]	64	1		T7	2		T9	2		T12	2
all_values[10]	auto[0]	auto[1]	99	1		T6	5		T32	3		T31	1
all_values[10]	auto[1]	auto[0]	27	1		T30	4		T31	1		T33	1
all_values[10]	auto[1]	auto[1]	86	1		T6	3		T32	2		T29	6
all_values[11]	auto[0]	auto[0]	51	1		T6	1		T7	2		T9	2
all_values[11]	auto[0]	auto[1]	105	1		T6	3		T32	4		T30	2
all_values[11]	auto[1]	auto[0]	12	1		T63	1		T74	1		T75	4
all_values[11]	auto[1]	auto[1]	108	1		T6	4		T32	1		T29	7
all_values[12]	auto[0]	auto[0]	60	1		T6	2		T7	2		T9	2
all_values[12]	auto[0]	auto[1]	100	1		T6	2		T29	5		T30	3
all_values[12]	auto[1]	auto[0]	13	1		T30	1		T70	1		T72	2
all_values[12]	auto[1]	auto[1]	103	1		T6	4		T32	4		T29	3
all_values[13]	auto[0]	auto[0]	56	1		T7	2		T9	2		T12	2
all_values[13]	auto[0]	auto[1]	104	1		T6	5		T32	3		T30	3
all_values[13]	auto[1]	auto[0]	14	1		T32	1		T29	1		T33	2
all_values[13]	auto[1]	auto[1]	102	1		T6	3		T32	1		T29	6
all_values[14]	auto[0]	auto[0]	61	1		T7	2		T9	2		T32	1
all_values[14]	auto[0]	auto[1]	90	1		T6	2		T29	6		T33	3
all_values[14]	auto[1]	auto[0]	37	1		T32	4		T29	1		T31	2
all_values[14]	auto[1]	auto[1]	88	1		T6	6		T29	1		T30	5
all_values[15]	auto[0]	auto[0]	50	1		T6	2		T7	2		T9	2
all_values[15]	auto[0]	auto[1]	129	1		T6	3		T32	4		T29	7
all_values[15]	auto[1]	auto[0]	17	1		T6	3		T71	1		T76	1
all_values[15]	auto[1]	auto[1]	80	1		T32	1		T29	1		T30	5
all_values[16]	auto[0]	auto[0]	65	1		T7	2		T9	2		T32	1
all_values[16]	auto[0]	auto[1]	98	1		T6	5		T29	3		T30	4
all_values[16]	auto[1]	auto[0]	27	1		T6	1		T32	4		T72	3
all_values[16]	auto[1]	auto[1]	86	1		T6	2		T29	5		T30	1