| | | | | | | |
prim_generic_ram_2p |
16.24 |
15.38 |
|
|
|
33.33 |
0.00 |
prim_sync_reqack |
30.56 |
72.22 |
0.00 |
|
|
50.00 |
0.00 |
prim_reg_cdc_arb |
37.90 |
49.67 |
62.79 |
|
|
39.13 |
0.00 |
prim_reg_cdc_arb |
19.57 |
|
|
|
|
39.13 |
0.00 |
prim_reg_cdc_arb ( parameter DataWidth=10,ResetVal=0,DstWrReq=1 ) |
45.79 |
66.00 |
25.58 |
|
|
|
|
prim_reg_cdc_arb ( parameter DataWidth=2,ResetVal=0,DstWrReq=0 ) |
66.67 |
33.33 |
100.00 |
|
|
|
|
usb_fs_nb_in_pe |
41.55 |
52.83 |
17.14 |
|
0.00 |
37.78 |
100.00 |
usb_fs_nb_out_pe |
43.24 |
54.84 |
20.16 |
|
0.00 |
41.18 |
100.00 |
usb_fs_tx |
43.33 |
50.54 |
32.76 |
|
0.00 |
33.33 |
100.00 |
usbdev_linkstate |
45.35 |
50.96 |
36.23 |
|
7.41 |
32.14 |
100.00 |
prim_generic_clock_mux2 |
48.15 |
100.00 |
44.44 |
|
|
|
0.00 |
usb_fs_rx |
59.90 |
75.68 |
45.60 |
|
|
58.43 |
|
tlul_adapter_sram |
60.72 |
75.38 |
38.94 |
|
|
50.00 |
78.57 |
usb_fs_tx_mux |
63.33 |
100.00 |
40.00 |
|
|
50.00 |
|
prim_fifo_sync_cnt |
63.89 |
77.78 |
|
|
|
50.00 |
|
prim_fifo_sync_cnt |
50.00 |
|
|
|
|
50.00 |
|
prim_fifo_sync_cnt ( parameter Depth=1,Width=2,Secure=0 ) |
77.78 |
77.78 |
|
|
|
|
|
prim_fifo_sync_cnt ( parameter Depth=8,Width=4,Secure=0 ) |
77.78 |
77.78 |
|
|
|
|
|
usbdev_iomux |
65.62 |
81.25 |
|
|
|
50.00 |
|
prim_fifo_sync |
69.12 |
90.91 |
41.95 |
|
|
60.28 |
83.33 |
prim_fifo_sync |
83.33 |
|
|
|
|
|
83.33 |
prim_fifo_sync ( parameter Width=108,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=65,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 ) |
100.00 |
100.00 |
|
|
|
|
|
prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 ) |
42.31 |
|
42.31 |
|
|
|
|
prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 ) |
86.36 |
86.36 |
|
|
|
|
|
prim_fifo_sync ( parameter Width=17,Pass=0,Depth=8,OutputZeroIfEmpty=1,Secure=0,DepthW=4,gen_normal_fifo.PTRV_W=3,gen_normal_fifo.PTR_WIDTH=4 ) |
66.61 |
90.91 |
42.31 |
|
|
|
|
prim_fifo_sync ( parameter Width=17,Pass=0,Depth=8,OutputZeroIfEmpty=1,Secure=0,DepthW=4,gen_normal_fifo.PTRV_W=3,gen_normal_fifo.PTR_WIDTH=4 + Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 ) |
60.00 |
|
|
|
|
60.00 |
|
prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 ) |
63.47 |
90.91 |
41.18 |
|
|
58.33 |
|
prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 ) |
42.31 |
|
42.31 |
|
|
|
|
prim_fifo_sync ( parameter Width=5,Pass=0,Depth=8,OutputZeroIfEmpty=0,Secure=0,DepthW=4,gen_normal_fifo.PTRV_W=3,gen_normal_fifo.PTR_WIDTH=4 ) |
63.51 |
86.36 |
41.67 |
|
|
62.50 |
|
usbdev_usbif |
69.47 |
85.71 |
38.60 |
|
|
53.57 |
100.00 |
usb_fs_nb_pe |
72.22 |
100.00 |
16.67 |
|
|
|
100.00 |
usbdev |
72.77 |
83.19 |
35.82 |
89.69 |
|
55.17 |
100.00 |
prim_ram_2p_async_adv |
77.45 |
76.47 |
33.33 |
|
|
100.00 |
100.00 |
prim_subreg_arb |
88.89 |
66.67 |
100.00 |
|
|
100.00 |
|
prim_subreg_arb |
100.00 |
|
|
|
|
100.00 |
|
prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 + DW=7,SwAccess=0,Mubi=0 + DW=5,SwAccess=0,Mubi=0 ) |
100.00 |
100.00 |
|
|
|
|
|
prim_subreg_arb ( parameter DW=1,SwAccess=1,Mubi=0 ) |
0.00 |
0.00 |
|
|
|
|
|
prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 ) |
100.00 |
100.00 |
100.00 |
|
|
|
|
prim_subreg_arb ( parameter DW=5,SwAccess=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg_arb ( parameter DW=7,SwAccess=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_intr_hw |
89.58 |
100.00 |
58.33 |
|
|
100.00 |
100.00 |
prim_reg_cdc |
92.86 |
100.00 |
71.43 |
|
|
100.00 |
100.00 |
tlul_assert |
95.24 |
100.00 |
|
|
|
85.71 |
100.00 |
tlul_rsp_intg_gen |
95.83 |
91.67 |
|
|
|
|
100.00 |
tlul_rsp_intg_gen |
100.00 |
|
|
|
|
|
100.00 |
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=0,EnableDataIntgGen=0 ) |
83.33 |
83.33 |
|
|
|
|
|
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=1,EnableDataIntgGen=1 ) |
100.00 |
100.00 |
|
|
|
|
|
tlul_socket_1n |
97.67 |
98.21 |
97.73 |
|
|
94.74 |
100.00 |
tlul_adapter_reg |
98.98 |
100.00 |
95.92 |
|
|
100.00 |
100.00 |
usbdev_reg_top |
99.60 |
99.72 |
98.70 |
|
|
100.00 |
100.00 |
tlul_data_integ_dec |
100.00 |
100.00 |
|
|
|
|
|
tlul_cmd_intg_chk |
100.00 |
100.00 |
|
|
|
|
100.00 |
prim_alert_sender |
100.00 |
|
|
100.00 |
|
|
|
tlul_fifo_sync |
100.00 |
|
100.00 |
|
|
100.00 |
|
prim_edge_detector |
100.00 |
100.00 |
|
|
|
100.00 |
|
prim_onehot_check |
100.00 |
|
|
100.00 |
|
|
|
prim_subreg |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
prim_subreg |
100.00 |
100.00 |
|
|
|
100.00 |
|
prim_subreg ( parameter DW=1,SwAccess=3,RESVAL=0,Mubi=0 + DW=1,SwAccess=0,RESVAL,Mubi=0 + DW=1,SwAccess=1,RESVAL=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg ( parameter DW=5,SwAccess=0,RESVAL=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg ( parameter DW=7,SwAccess=0,RESVAL=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_filter |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
prim_secded_inv_39_32_dec |
100.00 |
|
|
100.00 |
|
|
|
prim_generic_buf |
100.00 |
100.00 |
|
|
|
|
|
prim_pulse_sync |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
prim_subreg_ext |
100.00 |
100.00 |
|
|
|
|
|
prim_secded_inv_39_32_enc |
100.00 |
100.00 |
|
|
|
|
|
tlul_sram_byte |
100.00 |
100.00 |
|
|
|
|
|
tlul_err |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
prim_secded_inv_64_57_enc |
100.00 |
100.00 |
|
|
|
|
|
prim_secded_inv_64_57_dec |
100.00 |
|
|
100.00 |
|
|
|
prim_generic_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
usbdev_csr_assert_fpv |
100.00 |
|
|
|
|
|
100.00 |
tlul_data_integ_enc |
|
|
|
|
|
|
|
prim_reg_we_check |
|
|
|
|
|
|
|
prim_clock_mux2 |
|
|
|
|
|
|
|
prim_buf |
|
|
|
|
|
|
|
prim_flop |
|
|
|
|
|
|
|
prim_ram_2p_adv |
|
|
|
|
|
|
|
prim_flop_2sync |
|
|
|
|
|
|
|
tb |
|
|
|
|
|
|
|
prim_ram_2p |
|
|
|
|
|
|
|