Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
77.02	89.84	75.69	95.05	3.12	87.16	92.01	96.28

Total tests in report: 153

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
51.61	51.61	66.13	66.13	57.06	57.06	78.39	78.39	0.00	0.00	71.64	71.64	67.21	67.21	20.82	20.82	/workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.3909944190
63.45	11.85	88.66	22.53	69.50	12.44	87.53	9.14	3.12	3.12	86.12	14.48	87.50	20.29	21.75	0.93	/workspace/coverage/default/0.usbdev_sec_cm.1923151994
70.31	6.86	89.42	0.76	71.06	1.56	90.65	3.12	3.12	0.00	86.12	0.00	87.50	0.00	64.31	42.57	/workspace/coverage/cover_reg_top/8.usbdev_intr_test.2747269370
73.35	3.04	89.92	0.50	73.57	2.51	93.01	2.37	3.12	0.00	86.29	0.17	88.93	1.43	78.62	14.31	/workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2495182044
74.50	1.15	89.99	0.06	73.62	0.05	93.23	0.22	3.12	0.00	86.38	0.09	89.14	0.20	86.06	7.43	/workspace/coverage/cover_reg_top/20.usbdev_intr_test.3506769250
75.31	0.80	90.09	0.10	74.13	0.51	94.19	0.97	3.12	0.00	86.90	0.52	89.14	0.00	89.59	3.53	/workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.2847176361
75.76	0.45	90.09	0.00	74.13	0.00	94.19	0.00	3.12	0.00	86.90	0.00	89.14	0.00	92.75	3.16	/workspace/coverage/cover_reg_top/39.usbdev_intr_test.3312082930
76.20	0.44	90.09	0.00	74.13	0.00	94.19	0.00	3.12	0.00	86.90	0.00	92.01	2.87	92.94	0.19	/workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1428419695
76.49	0.29	90.11	0.02	75.18	1.05	95.05	0.86	3.12	0.00	87.03	0.13	92.01	0.00	92.94	0.00	/workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.1589025096
76.70	0.21	90.11	0.00	75.18	0.00	95.05	0.00	3.12	0.00	87.03	0.00	92.01	0.00	94.42	1.49	/workspace/coverage/cover_reg_top/25.usbdev_intr_test.1468909824
76.81	0.11	90.11	0.00	75.18	0.00	95.05	0.00	3.12	0.00	87.03	0.00	92.01	0.00	95.17	0.74	/workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.1909729651
76.89	0.08	90.11	0.00	75.56	0.38	95.05	0.00	3.12	0.00	87.03	0.00	92.01	0.00	95.35	0.19	/workspace/coverage/cover_reg_top/3.usbdev_tl_errors.3789666767
76.97	0.08	90.11	0.00	75.56	0.00	95.05	0.00	3.12	0.00	87.03	0.00	92.01	0.00	95.91	0.56	/workspace/coverage/cover_reg_top/37.usbdev_intr_test.4191549145
77.00	0.03	90.11	0.00	75.56	0.00	95.05	0.00	3.12	0.00	87.03	0.00	92.01	0.00	96.10	0.19	/workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.3916437454
77.02	0.03	90.11	0.00	75.56	0.00	95.05	0.00	3.12	0.00	87.03	0.00	92.01	0.00	96.28	0.19	/workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.388763511
77.05	0.02	90.22	0.10	75.56	0.00	95.05	0.00	3.12	0.00	87.07	0.04	92.01	0.00	96.28	0.00	/workspace/coverage/default/2.usbdev_sec_cm.2513724366
77.07	0.02	90.22	0.00	75.61	0.05	95.05	0.00	3.12	0.00	87.16	0.09	92.01	0.00	96.28	0.00	/workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1636291118
77.07	0.01	90.22	0.00	75.64	0.03	95.05	0.00	3.12	0.00	87.16	0.00	92.01	0.00	96.28	0.00	/workspace/coverage/cover_reg_top/0.usbdev_tl_errors.1975893022
77.07	0.01	90.22	0.00	75.67	0.03	95.05	0.00	3.12	0.00	87.16	0.00	92.01	0.00	96.28	0.00	/workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.3453527885
77.08	0.01	90.22	0.00	75.69	0.03	95.05	0.00	3.12	0.00	87.16	0.00	92.01	0.00	96.28	0.00	/workspace/coverage/default/1.usbdev_sec_cm.3003492132

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.332355650
/workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1958195291
/workspace/coverage/cover_reg_top/0.usbdev_intr_test.3856134301
/workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.2286766667
/workspace/coverage/cover_reg_top/0.usbdev_mem_walk.1419479562
/workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.2127738308
/workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.1478464265
/workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.3261721546
/workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.3493875653
/workspace/coverage/cover_reg_top/1.usbdev_csr_rw.2900711866
/workspace/coverage/cover_reg_top/1.usbdev_intr_test.1714140227
/workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.1668197512
/workspace/coverage/cover_reg_top/1.usbdev_mem_walk.1210542532
/workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.3985622591
/workspace/coverage/cover_reg_top/1.usbdev_tl_errors.3206598625
/workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.2967006516
/workspace/coverage/cover_reg_top/10.usbdev_csr_rw.2405633660
/workspace/coverage/cover_reg_top/10.usbdev_intr_test.394017982
/workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.3772872960
/workspace/coverage/cover_reg_top/10.usbdev_tl_errors.456605831
/workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2779841038
/workspace/coverage/cover_reg_top/11.usbdev_csr_rw.2844674658
/workspace/coverage/cover_reg_top/11.usbdev_intr_test.3842193257
/workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.638213683
/workspace/coverage/cover_reg_top/11.usbdev_tl_errors.3016865670
/workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1706666766
/workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.3156642105
/workspace/coverage/cover_reg_top/12.usbdev_csr_rw.1744409813
/workspace/coverage/cover_reg_top/12.usbdev_intr_test.2132000595
/workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3942518690
/workspace/coverage/cover_reg_top/12.usbdev_tl_errors.3604844506
/workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.125517290
/workspace/coverage/cover_reg_top/13.usbdev_csr_rw.3615003199
/workspace/coverage/cover_reg_top/13.usbdev_intr_test.2659292123
/workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.491676448
/workspace/coverage/cover_reg_top/13.usbdev_tl_errors.2289216077
/workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.2345434417
/workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.3854158894
/workspace/coverage/cover_reg_top/14.usbdev_csr_rw.3961713181
/workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.550108355
/workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3095583971
/workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.2580661723
/workspace/coverage/cover_reg_top/15.usbdev_csr_rw.2190932445
/workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3469007569
/workspace/coverage/cover_reg_top/15.usbdev_tl_errors.3050885709
/workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.3189355353
/workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3741615396
/workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1032938009
/workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.2798216428
/workspace/coverage/cover_reg_top/17.usbdev_csr_rw.2289798338
/workspace/coverage/cover_reg_top/17.usbdev_intr_test.875039415
/workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.2480714593
/workspace/coverage/cover_reg_top/17.usbdev_tl_errors.2488038914
/workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.1174070128
/workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.651854834
/workspace/coverage/cover_reg_top/18.usbdev_csr_rw.1384255224
/workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.2537971792
/workspace/coverage/cover_reg_top/18.usbdev_tl_errors.785775775
/workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.889874702
/workspace/coverage/cover_reg_top/19.usbdev_csr_rw.854790011
/workspace/coverage/cover_reg_top/19.usbdev_intr_test.3369718019
/workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.1847614461
/workspace/coverage/cover_reg_top/19.usbdev_tl_errors.1486528325
/workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2314516075
/workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.1013210204
/workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.1244323750
/workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.1355941637
/workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.3615722938
/workspace/coverage/cover_reg_top/2.usbdev_intr_test.3847413535
/workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.3876792715
/workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.548200051
/workspace/coverage/cover_reg_top/2.usbdev_tl_errors.657767835
/workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.2191635301
/workspace/coverage/cover_reg_top/22.usbdev_intr_test.3374105027
/workspace/coverage/cover_reg_top/23.usbdev_intr_test.2663408565
/workspace/coverage/cover_reg_top/24.usbdev_intr_test.3133793263
/workspace/coverage/cover_reg_top/26.usbdev_intr_test.2255391865
/workspace/coverage/cover_reg_top/28.usbdev_intr_test.4032690387
/workspace/coverage/cover_reg_top/29.usbdev_intr_test.847119557
/workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.566368268
/workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.995423748
/workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2649032543
/workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2685286028
/workspace/coverage/cover_reg_top/3.usbdev_intr_test.3440944529
/workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2895646409
/workspace/coverage/cover_reg_top/3.usbdev_mem_walk.1849104887
/workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.2784896295
/workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.2306679702
/workspace/coverage/cover_reg_top/30.usbdev_intr_test.574170169
/workspace/coverage/cover_reg_top/31.usbdev_intr_test.215306777
/workspace/coverage/cover_reg_top/32.usbdev_intr_test.2862704164
/workspace/coverage/cover_reg_top/33.usbdev_intr_test.2582910550
/workspace/coverage/cover_reg_top/36.usbdev_intr_test.1372688506
/workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2662589420
/workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.3240866822
/workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2231666575
/workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2160665454
/workspace/coverage/cover_reg_top/4.usbdev_csr_rw.2392359434
/workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.678774886
/workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.395937731
/workspace/coverage/cover_reg_top/4.usbdev_tl_errors.30687274
/workspace/coverage/cover_reg_top/40.usbdev_intr_test.2174200637
/workspace/coverage/cover_reg_top/41.usbdev_intr_test.1764097533
/workspace/coverage/cover_reg_top/42.usbdev_intr_test.487970790
/workspace/coverage/cover_reg_top/43.usbdev_intr_test.1966507591
/workspace/coverage/cover_reg_top/46.usbdev_intr_test.1132090596
/workspace/coverage/cover_reg_top/47.usbdev_intr_test.3423610086
/workspace/coverage/cover_reg_top/48.usbdev_intr_test.3909453592
/workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1995364519
/workspace/coverage/cover_reg_top/5.usbdev_csr_rw.171087636
/workspace/coverage/cover_reg_top/5.usbdev_intr_test.2220454464
/workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.8790351
/workspace/coverage/cover_reg_top/5.usbdev_tl_errors.2317421081
/workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.1310951379
/workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3198284568
/workspace/coverage/cover_reg_top/6.usbdev_intr_test.1993614804
/workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.4016589510
/workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1472951409
/workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.3702552139
/workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.2077758925
/workspace/coverage/cover_reg_top/7.usbdev_csr_rw.20583025
/workspace/coverage/cover_reg_top/7.usbdev_intr_test.1234712413
/workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.804726442
/workspace/coverage/cover_reg_top/7.usbdev_tl_errors.2863204268
/workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1755995397
/workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.1799318827
/workspace/coverage/cover_reg_top/8.usbdev_csr_rw.1303157546
/workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.253953068
/workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.1513303793
/workspace/coverage/cover_reg_top/9.usbdev_csr_rw.442426714
/workspace/coverage/cover_reg_top/9.usbdev_intr_test.1876395767
/workspace/coverage/cover_reg_top/9.usbdev_tl_errors.168444735
/workspace/coverage/default/3.usbdev_sec_cm.3925342591

Total test records in report: 153

tests.html | tests1.html | tests2.html

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/3.usbdev_sec_cm.3925342591	Jan 14 01:10:34 PM PST 24	Jan 14 01:10:36 PM PST 24	83876015 ps
T2	/workspace/coverage/default/1.usbdev_sec_cm.3003492132	Jan 14 01:10:30 PM PST 24	Jan 14 01:10:32 PM PST 24	149055522 ps
T3	/workspace/coverage/default/0.usbdev_sec_cm.1923151994	Jan 14 01:10:31 PM PST 24	Jan 14 01:10:33 PM PST 24	99607476 ps
T4	/workspace/coverage/default/2.usbdev_sec_cm.2513724366	Jan 14 01:10:41 PM PST 24	Jan 14 01:10:43 PM PST 24	287479355 ps
T5	/workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.550108355	Jan 14 01:15:27 PM PST 24	Jan 14 01:15:29 PM PST 24	72164817 ps
T6	/workspace/coverage/cover_reg_top/8.usbdev_intr_test.2747269370	Jan 14 01:15:17 PM PST 24	Jan 14 01:15:19 PM PST 24	24372793 ps
T7	/workspace/coverage/cover_reg_top/10.usbdev_tl_errors.456605831	Jan 14 01:15:14 PM PST 24	Jan 14 01:15:18 PM PST 24	119325936 ps
T8	/workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.3909944190	Jan 14 01:15:25 PM PST 24	Jan 14 01:15:27 PM PST 24	73158556 ps
T9	/workspace/coverage/cover_reg_top/1.usbdev_tl_errors.3206598625	Jan 14 01:15:07 PM PST 24	Jan 14 01:15:14 PM PST 24	121495377 ps
T10	/workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2662589420	Jan 14 01:15:12 PM PST 24	Jan 14 01:15:18 PM PST 24	77276309 ps
T24	/workspace/coverage/cover_reg_top/19.usbdev_csr_rw.854790011	Jan 14 01:15:26 PM PST 24	Jan 14 01:15:28 PM PST 24	65666914 ps
T11	/workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.678774886	Jan 14 01:15:12 PM PST 24	Jan 14 01:15:17 PM PST 24	46929280 ps
T23	/workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.2847176361	Jan 14 01:15:29 PM PST 24	Jan 14 01:15:34 PM PST 24	262713265 ps
T32	/workspace/coverage/cover_reg_top/23.usbdev_intr_test.2663408565	Jan 14 01:15:35 PM PST 24	Jan 14 01:15:39 PM PST 24	27317053 ps
T34	/workspace/coverage/cover_reg_top/11.usbdev_csr_rw.2844674658	Jan 14 01:15:24 PM PST 24	Jan 14 01:15:26 PM PST 24	35808804 ps
T35	/workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.253953068	Jan 14 01:15:25 PM PST 24	Jan 14 01:15:28 PM PST 24	68433828 ps
T12	/workspace/coverage/cover_reg_top/3.usbdev_tl_errors.3789666767	Jan 14 01:15:11 PM PST 24	Jan 14 01:15:17 PM PST 24	51115990 ps
T29	/workspace/coverage/cover_reg_top/20.usbdev_intr_test.3506769250	Jan 14 01:15:44 PM PST 24	Jan 14 01:15:46 PM PST 24	49646340 ps
T36	/workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.638213683	Jan 14 01:15:23 PM PST 24	Jan 14 01:15:25 PM PST 24	102582131 ps
T30	/workspace/coverage/cover_reg_top/40.usbdev_intr_test.2174200637	Jan 14 01:15:46 PM PST 24	Jan 14 01:15:47 PM PST 24	30502294 ps
T13	/workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2495182044	Jan 14 01:15:12 PM PST 24	Jan 14 01:15:17 PM PST 24	114708389 ps
T19	/workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.2127738308	Jan 14 01:15:12 PM PST 24	Jan 14 01:15:17 PM PST 24	148649704 ps
T14	/workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.1668197512	Jan 14 01:15:08 PM PST 24	Jan 14 01:15:15 PM PST 24	63943957 ps
T20	/workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1755995397	Jan 14 01:15:25 PM PST 24	Jan 14 01:15:29 PM PST 24	316211727 ps
T21	/workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.3453527885	Jan 14 01:15:20 PM PST 24	Jan 14 01:15:25 PM PST 24	416067200 ps
T22	/workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1428419695	Jan 14 01:15:09 PM PST 24	Jan 14 01:15:15 PM PST 24	70131325 ps
T15	/workspace/coverage/cover_reg_top/15.usbdev_tl_errors.3050885709	Jan 14 01:15:22 PM PST 24	Jan 14 01:15:25 PM PST 24	69355218 ps
T31	/workspace/coverage/cover_reg_top/7.usbdev_intr_test.1234712413	Jan 14 01:15:12 PM PST 24	Jan 14 01:15:17 PM PST 24	30974215 ps
T43	/workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.995423748	Jan 14 01:15:11 PM PST 24	Jan 14 01:15:23 PM PST 24	366024197 ps
T16	/workspace/coverage/cover_reg_top/1.usbdev_mem_walk.1210542532	Jan 14 01:15:09 PM PST 24	Jan 14 01:15:16 PM PST 24	86991920 ps
T44	/workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.1847614461	Jan 14 01:15:44 PM PST 24	Jan 14 01:15:46 PM PST 24	71205819 ps
T17	/workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.2286766667	Jan 14 01:15:11 PM PST 24	Jan 14 01:15:17 PM PST 24	65042595 ps
T18	/workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.3876792715	Jan 14 01:15:08 PM PST 24	Jan 14 01:15:15 PM PST 24	153473629 ps
T33	/workspace/coverage/cover_reg_top/41.usbdev_intr_test.1764097533	Jan 14 01:15:35 PM PST 24	Jan 14 01:15:39 PM PST 24	25901646 ps
T73	/workspace/coverage/cover_reg_top/26.usbdev_intr_test.2255391865	Jan 14 01:15:27 PM PST 24	Jan 14 01:15:29 PM PST 24	23558408 ps
T54	/workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2779841038	Jan 14 01:15:21 PM PST 24	Jan 14 01:15:24 PM PST 24	52722613 ps
T70	/workspace/coverage/cover_reg_top/37.usbdev_intr_test.4191549145	Jan 14 01:15:31 PM PST 24	Jan 14 01:15:33 PM PST 24	26852444 ps
T45	/workspace/coverage/cover_reg_top/17.usbdev_csr_rw.2289798338	Jan 14 01:15:34 PM PST 24	Jan 14 01:15:40 PM PST 24	51409275 ps
T72	/workspace/coverage/cover_reg_top/1.usbdev_intr_test.1714140227	Jan 14 01:15:09 PM PST 24	Jan 14 01:15:14 PM PST 24	22343159 ps
T55	/workspace/coverage/cover_reg_top/14.usbdev_csr_rw.3961713181	Jan 14 01:15:20 PM PST 24	Jan 14 01:15:22 PM PST 24	47584960 ps
T37	/workspace/coverage/cover_reg_top/0.usbdev_tl_errors.1975893022	Jan 14 01:15:10 PM PST 24	Jan 14 01:15:17 PM PST 24	258621167 ps
T46	/workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.1013210204	Jan 14 01:15:18 PM PST 24	Jan 14 01:15:21 PM PST 24	172237730 ps
T71	/workspace/coverage/cover_reg_top/32.usbdev_intr_test.2862704164	Jan 14 01:15:44 PM PST 24	Jan 14 01:15:45 PM PST 24	32371124 ps
T83	/workspace/coverage/cover_reg_top/7.usbdev_csr_rw.20583025	Jan 14 01:15:20 PM PST 24	Jan 14 01:15:22 PM PST 24	40795867 ps
T62	/workspace/coverage/cover_reg_top/6.usbdev_intr_test.1993614804	Jan 14 01:15:12 PM PST 24	Jan 14 01:15:16 PM PST 24	23543192 ps
T47	/workspace/coverage/cover_reg_top/13.usbdev_csr_rw.3615003199	Jan 14 01:15:21 PM PST 24	Jan 14 01:15:23 PM PST 24	35679749 ps
T81	/workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.3916437454	Jan 14 01:15:09 PM PST 24	Jan 14 01:15:15 PM PST 24	32397107 ps
T76	/workspace/coverage/cover_reg_top/10.usbdev_intr_test.394017982	Jan 14 01:15:18 PM PST 24	Jan 14 01:15:19 PM PST 24	27656822 ps
T82	/workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.2580661723	Jan 14 01:15:26 PM PST 24	Jan 14 01:15:28 PM PST 24	45772386 ps
T84	/workspace/coverage/cover_reg_top/42.usbdev_intr_test.487970790	Jan 14 01:15:45 PM PST 24	Jan 14 01:15:47 PM PST 24	18640520 ps
T56	/workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.548200051	Jan 14 01:15:09 PM PST 24	Jan 14 01:15:15 PM PST 24	215697033 ps
T40	/workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.388763511	Jan 14 01:15:21 PM PST 24	Jan 14 01:15:25 PM PST 24	395641451 ps
T63	/workspace/coverage/cover_reg_top/3.usbdev_intr_test.3440944529	Jan 14 01:15:18 PM PST 24	Jan 14 01:15:19 PM PST 24	37532081 ps
T57	/workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.4016589510	Jan 14 01:15:12 PM PST 24	Jan 14 01:15:17 PM PST 24	132142281 ps
T85	/workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.1799318827	Jan 14 01:15:25 PM PST 24	Jan 14 01:15:27 PM PST 24	29890626 ps
T38	/workspace/coverage/cover_reg_top/4.usbdev_tl_errors.30687274	Jan 14 01:15:17 PM PST 24	Jan 14 01:15:20 PM PST 24	153251082 ps
T86	/workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.2967006516	Jan 14 01:15:12 PM PST 24	Jan 14 01:15:17 PM PST 24	75487530 ps
T74	/workspace/coverage/cover_reg_top/39.usbdev_intr_test.3312082930	Jan 14 01:15:36 PM PST 24	Jan 14 01:15:39 PM PST 24	28132909 ps
T48	/workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2685286028	Jan 14 01:15:11 PM PST 24	Jan 14 01:15:15 PM PST 24	30959767 ps
T77	/workspace/coverage/cover_reg_top/25.usbdev_intr_test.1468909824	Jan 14 01:15:44 PM PST 24	Jan 14 01:15:45 PM PST 24	61543285 ps
T25	/workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.1589025096	Jan 14 01:15:05 PM PST 24	Jan 14 01:15:10 PM PST 24	78083619 ps
T87	/workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.3985622591	Jan 14 01:15:17 PM PST 24	Jan 14 01:15:20 PM PST 24	109872494 ps
T88	/workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.1513303793	Jan 14 01:15:21 PM PST 24	Jan 14 01:15:23 PM PST 24	36588486 ps
T51	/workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2895646409	Jan 14 01:15:12 PM PST 24	Jan 14 01:15:18 PM PST 24	76802163 ps
T89	/workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.2077758925	Jan 14 01:15:25 PM PST 24	Jan 14 01:15:28 PM PST 24	34969144 ps
T90	/workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.3615722938	Jan 14 01:15:18 PM PST 24	Jan 14 01:15:20 PM PST 24	25455472 ps
T91	/workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.332355650	Jan 14 01:15:07 PM PST 24	Jan 14 01:15:14 PM PST 24	161795233 ps
T39	/workspace/coverage/cover_reg_top/17.usbdev_tl_errors.2488038914	Jan 14 01:15:33 PM PST 24	Jan 14 01:15:40 PM PST 24	207538094 ps
T75	/workspace/coverage/cover_reg_top/36.usbdev_intr_test.1372688506	Jan 14 01:15:31 PM PST 24	Jan 14 01:15:33 PM PST 24	26913800 ps
T64	/workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.1310951379	Jan 14 01:15:13 PM PST 24	Jan 14 01:15:19 PM PST 24	330503894 ps
T53	/workspace/coverage/cover_reg_top/8.usbdev_csr_rw.1303157546	Jan 14 01:15:16 PM PST 24	Jan 14 01:15:19 PM PST 24	51772659 ps
T92	/workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2649032543	Jan 14 01:15:11 PM PST 24	Jan 14 01:15:16 PM PST 24	30100752 ps
T80	/workspace/coverage/cover_reg_top/13.usbdev_intr_test.2659292123	Jan 14 01:15:22 PM PST 24	Jan 14 01:15:24 PM PST 24	44888594 ps
T41	/workspace/coverage/cover_reg_top/12.usbdev_tl_errors.3604844506	Jan 14 01:15:25 PM PST 24	Jan 14 01:15:29 PM PST 24	232556684 ps
T42	/workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1472951409	Jan 14 01:15:13 PM PST 24	Jan 14 01:15:19 PM PST 24	99502535 ps
T52	/workspace/coverage/cover_reg_top/9.usbdev_csr_rw.442426714	Jan 14 01:15:28 PM PST 24	Jan 14 01:15:30 PM PST 24	51562043 ps
T93	/workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.1478464265	Jan 14 01:15:03 PM PST 24	Jan 14 01:15:11 PM PST 24	266731923 ps
T94	/workspace/coverage/cover_reg_top/46.usbdev_intr_test.1132090596	Jan 14 01:15:43 PM PST 24	Jan 14 01:15:44 PM PST 24	23710747 ps
T58	/workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1995364519	Jan 14 01:15:14 PM PST 24	Jan 14 01:15:18 PM PST 24	46809820 ps
T95	/workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.889874702	Jan 14 01:15:36 PM PST 24	Jan 14 01:15:40 PM PST 24	54704259 ps
T59	/workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.491676448	Jan 14 01:15:27 PM PST 24	Jan 14 01:15:29 PM PST 24	71386022 ps
T49	/workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.566368268	Jan 14 01:15:10 PM PST 24	Jan 14 01:15:15 PM PST 24	191910244 ps
T96	/workspace/coverage/cover_reg_top/31.usbdev_intr_test.215306777	Jan 14 01:15:34 PM PST 24	Jan 14 01:15:39 PM PST 24	28406475 ps
T78	/workspace/coverage/cover_reg_top/29.usbdev_intr_test.847119557	Jan 14 01:15:34 PM PST 24	Jan 14 01:15:39 PM PST 24	19300896 ps
T60	/workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.3702552139	Jan 14 01:15:10 PM PST 24	Jan 14 01:15:17 PM PST 24	377803846 ps
T69	/workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.2345434417	Jan 14 01:15:21 PM PST 24	Jan 14 01:15:26 PM PST 24	300148999 ps
T97	/workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2160665454	Jan 14 01:15:12 PM PST 24	Jan 14 01:15:18 PM PST 24	67021930 ps
T98	/workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2314516075	Jan 14 01:15:45 PM PST 24	Jan 14 01:15:50 PM PST 24	254352784 ps
T99	/workspace/coverage/cover_reg_top/1.usbdev_csr_rw.2900711866	Jan 14 01:15:08 PM PST 24	Jan 14 01:15:13 PM PST 24	29758530 ps
T100	/workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.3261721546	Jan 14 01:15:09 PM PST 24	Jan 14 01:15:17 PM PST 24	312367518 ps
T101	/workspace/coverage/cover_reg_top/47.usbdev_intr_test.3423610086	Jan 14 01:15:40 PM PST 24	Jan 14 01:15:43 PM PST 24	43183348 ps
T102	/workspace/coverage/cover_reg_top/19.usbdev_tl_errors.1486528325	Jan 14 01:15:32 PM PST 24	Jan 14 01:15:35 PM PST 24	132645211 ps
T103	/workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1032938009	Jan 14 01:15:25 PM PST 24	Jan 14 01:15:30 PM PST 24	291758579 ps
T61	/workspace/coverage/cover_reg_top/5.usbdev_csr_rw.171087636	Jan 14 01:15:13 PM PST 24	Jan 14 01:15:17 PM PST 24	68259952 ps
T65	/workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1706666766	Jan 14 01:15:20 PM PST 24	Jan 14 01:15:23 PM PST 24	268269060 ps
T104	/workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.2537971792	Jan 14 01:15:24 PM PST 24	Jan 14 01:15:27 PM PST 24	149443665 ps
T105	/workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.3854158894	Jan 14 01:15:24 PM PST 24	Jan 14 01:15:26 PM PST 24	46791858 ps
T106	/workspace/coverage/cover_reg_top/12.usbdev_csr_rw.1744409813	Jan 14 01:15:25 PM PST 24	Jan 14 01:15:27 PM PST 24	56753485 ps
T107	/workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.2798216428	Jan 14 01:15:31 PM PST 24	Jan 14 01:15:34 PM PST 24	65066930 ps
T108	/workspace/coverage/cover_reg_top/19.usbdev_intr_test.3369718019	Jan 14 01:15:36 PM PST 24	Jan 14 01:15:39 PM PST 24	32892045 ps
T66	/workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.2306679702	Jan 14 01:15:05 PM PST 24	Jan 14 01:15:14 PM PST 24	282391512 ps
T109	/workspace/coverage/cover_reg_top/4.usbdev_csr_rw.2392359434	Jan 14 01:15:14 PM PST 24	Jan 14 01:15:18 PM PST 24	39697459 ps
T110	/workspace/coverage/cover_reg_top/11.usbdev_intr_test.3842193257	Jan 14 01:15:22 PM PST 24	Jan 14 01:15:24 PM PST 24	24116671 ps
T111	/workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1958195291	Jan 14 01:15:04 PM PST 24	Jan 14 01:15:09 PM PST 24	39137711 ps
T112	/workspace/coverage/cover_reg_top/48.usbdev_intr_test.3909453592	Jan 14 01:15:46 PM PST 24	Jan 14 01:15:47 PM PST 24	30243979 ps
T50	/workspace/coverage/cover_reg_top/10.usbdev_csr_rw.2405633660	Jan 14 01:15:24 PM PST 24	Jan 14 01:15:25 PM PST 24	36989680 ps
T113	/workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.8790351	Jan 14 01:15:11 PM PST 24	Jan 14 01:15:16 PM PST 24	140307061 ps
T114	/workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.2784896295	Jan 14 01:15:11 PM PST 24	Jan 14 01:15:15 PM PST 24	35264576 ps
T115	/workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3198284568	Jan 14 01:15:25 PM PST 24	Jan 14 01:15:28 PM PST 24	75381071 ps
T116	/workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3469007569	Jan 14 01:15:29 PM PST 24	Jan 14 01:15:31 PM PST 24	88375091 ps
T117	/workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.3156642105	Jan 14 01:15:20 PM PST 24	Jan 14 01:15:23 PM PST 24	63147365 ps
T26	/workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1636291118	Jan 14 01:15:11 PM PST 24	Jan 14 01:15:15 PM PST 24	34721663 ps
T118	/workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3095583971	Jan 14 01:15:29 PM PST 24	Jan 14 01:15:31 PM PST 24	116231395 ps
T119	/workspace/coverage/cover_reg_top/13.usbdev_tl_errors.2289216077	Jan 14 01:15:20 PM PST 24	Jan 14 01:15:23 PM PST 24	86325506 ps
T120	/workspace/coverage/cover_reg_top/18.usbdev_csr_rw.1384255224	Jan 14 01:15:37 PM PST 24	Jan 14 01:15:39 PM PST 24	40276458 ps
T121	/workspace/coverage/cover_reg_top/12.usbdev_intr_test.2132000595	Jan 14 01:15:24 PM PST 24	Jan 14 01:15:26 PM PST 24	41804227 ps
T122	/workspace/coverage/cover_reg_top/11.usbdev_tl_errors.3016865670	Jan 14 01:15:24 PM PST 24	Jan 14 01:15:27 PM PST 24	53326821 ps
T123	/workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3741615396	Jan 14 01:15:26 PM PST 24	Jan 14 01:15:28 PM PST 24	41422266 ps
T79	/workspace/coverage/cover_reg_top/33.usbdev_intr_test.2582910550	Jan 14 01:15:31 PM PST 24	Jan 14 01:15:33 PM PST 24	25983477 ps
T124	/workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.651854834	Jan 14 01:15:25 PM PST 24	Jan 14 01:15:28 PM PST 24	66368978 ps
T125	/workspace/coverage/cover_reg_top/2.usbdev_tl_errors.657767835	Jan 14 01:15:17 PM PST 24	Jan 14 01:15:20 PM PST 24	85360722 ps
T126	/workspace/coverage/cover_reg_top/18.usbdev_tl_errors.785775775	Jan 14 01:15:32 PM PST 24	Jan 14 01:15:35 PM PST 24	110199043 ps
T127	/workspace/coverage/cover_reg_top/7.usbdev_tl_errors.2863204268	Jan 14 01:15:12 PM PST 24	Jan 14 01:15:18 PM PST 24	153245973 ps
T128	/workspace/coverage/cover_reg_top/22.usbdev_intr_test.3374105027	Jan 14 01:15:34 PM PST 24	Jan 14 01:15:39 PM PST 24	20109049 ps
T129	/workspace/coverage/cover_reg_top/28.usbdev_intr_test.4032690387	Jan 14 01:15:34 PM PST 24	Jan 14 01:15:39 PM PST 24	45057612 ps
T130	/workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3942518690	Jan 14 01:15:22 PM PST 24	Jan 14 01:15:24 PM PST 24	78596576 ps
T131	/workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.804726442	Jan 14 01:15:13 PM PST 24	Jan 14 01:15:17 PM PST 24	81793138 ps
T132	/workspace/coverage/cover_reg_top/5.usbdev_intr_test.2220454464	Jan 14 01:15:19 PM PST 24	Jan 14 01:15:21 PM PST 24	30611736 ps
T133	/workspace/coverage/cover_reg_top/0.usbdev_intr_test.3856134301	Jan 14 01:15:11 PM PST 24	Jan 14 01:15:15 PM PST 24	36610732 ps
T134	/workspace/coverage/cover_reg_top/9.usbdev_intr_test.1876395767	Jan 14 01:15:18 PM PST 24	Jan 14 01:15:20 PM PST 24	25918390 ps
T135	/workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.1244323750	Jan 14 01:15:18 PM PST 24	Jan 14 01:15:23 PM PST 24	196312710 ps
T136	/workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.3772872960	Jan 14 01:15:26 PM PST 24	Jan 14 01:15:28 PM PST 24	48791987 ps
T137	/workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.3189355353	Jan 14 01:15:26 PM PST 24	Jan 14 01:15:29 PM PST 24	59205441 ps
T138	/workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.2480714593	Jan 14 01:15:27 PM PST 24	Jan 14 01:15:29 PM PST 24	42762413 ps
T139	/workspace/coverage/cover_reg_top/17.usbdev_intr_test.875039415	Jan 14 01:15:31 PM PST 24	Jan 14 01:15:33 PM PST 24	38216208 ps
T28	/workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.1355941637	Jan 14 01:15:04 PM PST 24	Jan 14 01:15:09 PM PST 24	42897896 ps
T140	/workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.3493875653	Jan 14 01:15:17 PM PST 24	Jan 14 01:15:19 PM PST 24	60653984 ps
T67	/workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.1174070128	Jan 14 01:15:33 PM PST 24	Jan 14 01:15:42 PM PST 24	286785004 ps
T68	/workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.1909729651	Jan 14 01:15:25 PM PST 24	Jan 14 01:15:30 PM PST 24	247078933 ps
T141	/workspace/coverage/cover_reg_top/0.usbdev_mem_walk.1419479562	Jan 14 01:15:04 PM PST 24	Jan 14 01:15:10 PM PST 24	322942144 ps
T142	/workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.3240866822	Jan 14 01:15:10 PM PST 24	Jan 14 01:15:23 PM PST 24	450363344 ps
T143	/workspace/coverage/cover_reg_top/43.usbdev_intr_test.1966507591	Jan 14 01:15:39 PM PST 24	Jan 14 01:15:43 PM PST 24	32123954 ps
T144	/workspace/coverage/cover_reg_top/2.usbdev_intr_test.3847413535	Jan 14 01:15:08 PM PST 24	Jan 14 01:15:14 PM PST 24	24707801 ps
T145	/workspace/coverage/cover_reg_top/9.usbdev_tl_errors.168444735	Jan 14 01:15:24 PM PST 24	Jan 14 01:15:28 PM PST 24	263730648 ps
T146	/workspace/coverage/cover_reg_top/24.usbdev_intr_test.3133793263	Jan 14 01:15:45 PM PST 24	Jan 14 01:15:46 PM PST 24	20769998 ps
T147	/workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.125517290	Jan 14 01:15:26 PM PST 24	Jan 14 01:15:28 PM PST 24	49069278 ps
T148	/workspace/coverage/cover_reg_top/5.usbdev_tl_errors.2317421081	Jan 14 01:15:25 PM PST 24	Jan 14 01:15:28 PM PST 24	85884482 ps
T149	/workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.395937731	Jan 14 01:15:11 PM PST 24	Jan 14 01:15:15 PM PST 24	81594070 ps
T150	/workspace/coverage/cover_reg_top/30.usbdev_intr_test.574170169	Jan 14 01:15:35 PM PST 24	Jan 14 01:15:39 PM PST 24	27124662 ps
T27	/workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2231666575	Jan 14 01:15:14 PM PST 24	Jan 14 01:15:17 PM PST 24	57664425 ps
T151	/workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.2191635301	Jan 14 01:15:09 PM PST 24	Jan 14 01:15:17 PM PST 24	241484980 ps
T152	/workspace/coverage/cover_reg_top/15.usbdev_csr_rw.2190932445	Jan 14 01:15:29 PM PST 24	Jan 14 01:15:30 PM PST 24	29423774 ps
T153	/workspace/coverage/cover_reg_top/3.usbdev_mem_walk.1849104887	Jan 14 01:15:11 PM PST 24	Jan 14 01:15:18 PM PST 24	149337620 ps

Test location	/workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.3909944190
Short name	T8
Test name
Test status
Simulation time	73158556 ps
CPU time	1.05 seconds
Started	Jan 14 01:15:25 PM PST 24
Finished	Jan 14 01:15:27 PM PST 24
Peak memory	202232 kb
Host	smart-da5283de-b4b4-4a15-a2db-bec389e14f63
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909944190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_c sr_outstanding.3909944190
Directory	/workspace/9.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/default/0.usbdev_sec_cm.1923151994
Short name	T3
Test name
Test status
Simulation time	99607476 ps
CPU time	0.92 seconds
Started	Jan 14 01:10:31 PM PST 24
Finished	Jan 14 01:10:33 PM PST 24
Peak memory	220740 kb
Host	smart-ee3eaa19-2c5d-4768-bb81-add4f1df1425
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1923151994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.1923151994
Directory	/workspace/0.usbdev_sec_cm/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_intr_test.2747269370
Short name	T6
Test name
Test status
Simulation time	24372793 ps
CPU time	0.64 seconds
Started	Jan 14 01:15:17 PM PST 24
Finished	Jan 14 01:15:19 PM PST 24
Peak memory	201328 kb
Host	smart-90c51b57-2ff0-4fb3-a36a-7ff0cefe08ac
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2747269370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.2747269370
Directory	/workspace/8.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2495182044
Short name	T13
Test name
Test status
Simulation time	114708389 ps
CPU time	1.67 seconds
Started	Jan 14 01:15:12 PM PST 24
Finished	Jan 14 01:15:17 PM PST 24
Peak memory	202316 kb
Host	smart-b04a7479-50e4-4d55-b76b-11363969c891
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2495182044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.2495182044
Directory	/workspace/8.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/20.usbdev_intr_test.3506769250
Short name	T29
Test name
Test status
Simulation time	49646340 ps
CPU time	0.68 seconds
Started	Jan 14 01:15:44 PM PST 24
Finished	Jan 14 01:15:46 PM PST 24
Peak memory	201332 kb
Host	smart-c72b4720-aea9-4d2c-b7e6-ca1132979e2e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3506769250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.3506769250
Directory	/workspace/20.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.2847176361
Short name	T23
Test name
Test status
Simulation time	262713265 ps
CPU time	4.35 seconds
Started	Jan 14 01:15:29 PM PST 24
Finished	Jan 14 01:15:34 PM PST 24
Peak memory	202324 kb
Host	smart-0e8e1ce4-e6a4-43dc-8c21-63bc8b46da1d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2847176361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.2847176361
Directory	/workspace/15.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/39.usbdev_intr_test.3312082930
Short name	T74
Test name
Test status
Simulation time	28132909 ps
CPU time	0.66 seconds
Started	Jan 14 01:15:36 PM PST 24
Finished	Jan 14 01:15:39 PM PST 24
Peak memory	201316 kb
Host	smart-815da1b7-cddc-4606-b9bb-a9090bba744f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3312082930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.3312082930
Directory	/workspace/39.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1428419695
Short name	T22
Test name
Test status
Simulation time	70131325 ps
CPU time	1.05 seconds
Started	Jan 14 01:15:09 PM PST 24
Finished	Jan 14 01:15:15 PM PST 24
Peak memory	202224 kb
Host	smart-f0d23299-7290-4e79-9564-ffd35bc2854a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428419695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.1428419695
Directory	/workspace/6.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.1589025096
Short name	T25
Test name
Test status
Simulation time	78083619 ps
CPU time	0.83 seconds
Started	Jan 14 01:15:05 PM PST 24
Finished	Jan 14 01:15:10 PM PST 24
Peak memory	201952 kb
Host	smart-68516c4a-5f82-4d02-ae1e-3a5556a8023f
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589025096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.1589025096
Directory	/workspace/3.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/25.usbdev_intr_test.1468909824
Short name	T77
Test name
Test status
Simulation time	61543285 ps
CPU time	0.63 seconds
Started	Jan 14 01:15:44 PM PST 24
Finished	Jan 14 01:15:45 PM PST 24
Peak memory	201332 kb
Host	smart-010a657a-10a5-4557-8a96-e56942a48ed1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1468909824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.1468909824
Directory	/workspace/25.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.1909729651
Short name	T68
Test name
Test status
Simulation time	247078933 ps
CPU time	4.5 seconds
Started	Jan 14 01:15:25 PM PST 24
Finished	Jan 14 01:15:30 PM PST 24
Peak memory	202260 kb
Host	smart-0ec0fb7f-29ed-4800-919a-19f05dbd0098
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1909729651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.1909729651
Directory	/workspace/14.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_tl_errors.3789666767
Short name	T12
Test name
Test status
Simulation time	51115990 ps
CPU time	1.52 seconds
Started	Jan 14 01:15:11 PM PST 24
Finished	Jan 14 01:15:17 PM PST 24
Peak memory	202316 kb
Host	smart-b4f24733-5ac3-4f92-ad31-47b9a186bc50
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3789666767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.3789666767
Directory	/workspace/3.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/37.usbdev_intr_test.4191549145
Short name	T70
Test name
Test status
Simulation time	26852444 ps
CPU time	0.61 seconds
Started	Jan 14 01:15:31 PM PST 24
Finished	Jan 14 01:15:33 PM PST 24
Peak memory	201428 kb
Host	smart-ca618fb5-a7a4-4c39-8e83-8d17b05655aa
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4191549145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.4191549145
Directory	/workspace/37.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.3916437454
Short name	T81
Test name
Test status
Simulation time	32397107 ps
CPU time	1.37 seconds
Started	Jan 14 01:15:09 PM PST 24
Finished	Jan 14 01:15:15 PM PST 24
Peak memory	210568 kb
Host	smart-de544f74-5e46-44f7-88a3-d29ba1534bc8
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916437454 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_mem_rw_with_rand_reset.3916437454
Directory	/workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.388763511
Short name	T40
Test name
Test status
Simulation time	395641451 ps
CPU time	3.05 seconds
Started	Jan 14 01:15:21 PM PST 24
Finished	Jan 14 01:15:25 PM PST 24
Peak memory	202216 kb
Host	smart-7e29488b-4441-4df4-b9b0-27d6c90e57b4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=388763511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.388763511
Directory	/workspace/10.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/default/2.usbdev_sec_cm.2513724366
Short name	T4
Test name
Test status
Simulation time	287479355 ps
CPU time	1.1 seconds
Started	Jan 14 01:10:41 PM PST 24
Finished	Jan 14 01:10:43 PM PST 24
Peak memory	220784 kb
Host	smart-8b3023db-aba6-472f-b618-5db57705aaaa
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2513724366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.2513724366
Directory	/workspace/2.usbdev_sec_cm/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1636291118
Short name	T26
Test name
Test status
Simulation time	34721663 ps
CPU time	0.78 seconds
Started	Jan 14 01:15:11 PM PST 24
Finished	Jan 14 01:15:15 PM PST 24
Peak memory	202100 kb
Host	smart-402acc86-b4af-41a6-b642-6ccd635f1361
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636291118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.1636291118
Directory	/workspace/0.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_tl_errors.1975893022
Short name	T37
Test name
Test status
Simulation time	258621167 ps
CPU time	2.71 seconds
Started	Jan 14 01:15:10 PM PST 24
Finished	Jan 14 01:15:17 PM PST 24
Peak memory	202348 kb
Host	smart-a7de4e47-f20f-48fb-8e6d-e761710ca37e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1975893022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.1975893022
Directory	/workspace/0.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.3453527885
Short name	T21
Test name
Test status
Simulation time	416067200 ps
CPU time	4.47 seconds
Started	Jan 14 01:15:20 PM PST 24
Finished	Jan 14 01:15:25 PM PST 24
Peak memory	202264 kb
Host	smart-76c1b223-8c7f-4cb1-a203-bedf009b35a0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3453527885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.3453527885
Directory	/workspace/8.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/default/1.usbdev_sec_cm.3003492132
Short name	T2
Test name
Test status
Simulation time	149055522 ps
CPU time	1.06 seconds
Started	Jan 14 01:10:30 PM PST 24
Finished	Jan 14 01:10:32 PM PST 24
Peak memory	220652 kb
Host	smart-29aade6a-a47e-4cde-ad55-46a7ea0ed206
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3003492132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.3003492132
Directory	/workspace/1.usbdev_sec_cm/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.332355650
Short name	T91
Test name
Test status
Simulation time	161795233 ps
CPU time	2.06 seconds
Started	Jan 14 01:15:07 PM PST 24
Finished	Jan 14 01:15:14 PM PST 24
Peak memory	202184 kb
Host	smart-ee1431a2-8a35-4628-83ad-b56c9a81458f
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332355650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.332355650
Directory	/workspace/0.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1958195291
Short name	T111
Test name
Test status
Simulation time	39137711 ps
CPU time	1.03 seconds
Started	Jan 14 01:15:04 PM PST 24
Finished	Jan 14 01:15:09 PM PST 24
Peak memory	202336 kb
Host	smart-b527e242-2d83-4d94-91bd-d6e86a394c84
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958195291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.1958195291
Directory	/workspace/0.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_intr_test.3856134301
Short name	T133
Test name
Test status
Simulation time	36610732 ps
CPU time	0.63 seconds
Started	Jan 14 01:15:11 PM PST 24
Finished	Jan 14 01:15:15 PM PST 24
Peak memory	201412 kb
Host	smart-f7d202df-b208-4961-80b2-18530875f7ac
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3856134301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.3856134301
Directory	/workspace/0.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.2286766667
Short name	T17
Test name
Test status
Simulation time	65042595 ps
CPU time	2.11 seconds
Started	Jan 14 01:15:11 PM PST 24
Finished	Jan 14 01:15:17 PM PST 24
Peak memory	202176 kb
Host	smart-335a1480-46ea-40ab-af65-6726e8ccc3e8
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2286766667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.2286766667
Directory	/workspace/0.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_mem_walk.1419479562
Short name	T141
Test name
Test status
Simulation time	322942144 ps
CPU time	2.58 seconds
Started	Jan 14 01:15:04 PM PST 24
Finished	Jan 14 01:15:10 PM PST 24
Peak memory	202212 kb
Host	smart-d53eb4af-6555-4908-87d5-df59e7f99bfc
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1419479562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.1419479562
Directory	/workspace/0.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.2127738308
Short name	T19
Test name
Test status
Simulation time	148649704 ps
CPU time	1.46 seconds
Started	Jan 14 01:15:12 PM PST 24
Finished	Jan 14 01:15:17 PM PST 24
Peak memory	202344 kb
Host	smart-038511ea-3737-4bd0-8b76-76d6d171bde3
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127738308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_c sr_outstanding.2127738308
Directory	/workspace/0.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.1478464265
Short name	T93
Test name
Test status
Simulation time	266731923 ps
CPU time	2.99 seconds
Started	Jan 14 01:15:03 PM PST 24
Finished	Jan 14 01:15:11 PM PST 24
Peak memory	202308 kb
Host	smart-194a3599-8018-4769-9d76-75dfcb637230
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1478464265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.1478464265
Directory	/workspace/0.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.3261721546
Short name	T100
Test name
Test status
Simulation time	312367518 ps
CPU time	3.75 seconds
Started	Jan 14 01:15:09 PM PST 24
Finished	Jan 14 01:15:17 PM PST 24
Peak memory	202292 kb
Host	smart-c5e8113e-249c-484b-b58c-1c6746b368c8
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261721546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.3261721546
Directory	/workspace/1.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.3493875653
Short name	T140
Test name
Test status
Simulation time	60653984 ps
CPU time	0.95 seconds
Started	Jan 14 01:15:17 PM PST 24
Finished	Jan 14 01:15:19 PM PST 24
Peak memory	202284 kb
Host	smart-a3141080-8115-46d2-93a5-0ebb79d0dab7
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493875653 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_mem_rw_with_rand_reset.3493875653
Directory	/workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_rw.2900711866
Short name	T99
Test name
Test status
Simulation time	29758530 ps
CPU time	0.84 seconds
Started	Jan 14 01:15:08 PM PST 24
Finished	Jan 14 01:15:13 PM PST 24
Peak memory	202120 kb
Host	smart-85847a31-9406-44ef-95b9-1fcf1bf54274
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900711866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.2900711866
Directory	/workspace/1.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_intr_test.1714140227
Short name	T72
Test name
Test status
Simulation time	22343159 ps
CPU time	0.69 seconds
Started	Jan 14 01:15:09 PM PST 24
Finished	Jan 14 01:15:14 PM PST 24
Peak memory	201400 kb
Host	smart-4f874542-f22b-4e77-a4c9-40f132d1d8db
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1714140227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.1714140227
Directory	/workspace/1.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.1668197512
Short name	T14
Test name
Test status
Simulation time	63943957 ps
CPU time	2.29 seconds
Started	Jan 14 01:15:08 PM PST 24
Finished	Jan 14 01:15:15 PM PST 24
Peak memory	202304 kb
Host	smart-4bc9ef12-a379-4133-9f17-83b22853a5a3
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1668197512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.1668197512
Directory	/workspace/1.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_mem_walk.1210542532
Short name	T16
Test name
Test status
Simulation time	86991920 ps
CPU time	2.24 seconds
Started	Jan 14 01:15:09 PM PST 24
Finished	Jan 14 01:15:16 PM PST 24
Peak memory	202172 kb
Host	smart-9fd3ab7e-9d8e-41d2-86fd-37d934755c2a
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1210542532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.1210542532
Directory	/workspace/1.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.3985622591
Short name	T87
Test name
Test status
Simulation time	109872494 ps
CPU time	1.44 seconds
Started	Jan 14 01:15:17 PM PST 24
Finished	Jan 14 01:15:20 PM PST 24
Peak memory	202356 kb
Host	smart-aefa412c-324d-443a-9769-8d84ccaf92b5
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985622591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_c sr_outstanding.3985622591
Directory	/workspace/1.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_tl_errors.3206598625
Short name	T9
Test name
Test status
Simulation time	121495377 ps
CPU time	2.29 seconds
Started	Jan 14 01:15:07 PM PST 24
Finished	Jan 14 01:15:14 PM PST 24
Peak memory	202264 kb
Host	smart-2a958bd2-f16c-4d97-a8be-1568638be04c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3206598625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.3206598625
Directory	/workspace/1.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.2967006516
Short name	T86
Test name
Test status
Simulation time	75487530 ps
CPU time	1.33 seconds
Started	Jan 14 01:15:12 PM PST 24
Finished	Jan 14 01:15:17 PM PST 24
Peak memory	210412 kb
Host	smart-e84434a1-25f6-4335-8e46-1e39edefdf5a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967006516 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_mem_rw_with_rand_reset.2967006516
Directory	/workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_csr_rw.2405633660
Short name	T50
Test name
Test status
Simulation time	36989680 ps
CPU time	0.83 seconds
Started	Jan 14 01:15:24 PM PST 24
Finished	Jan 14 01:15:25 PM PST 24
Peak memory	202156 kb
Host	smart-ad2ed1c7-680f-4bdf-9ae9-eb9ad3878052
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405633660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.2405633660
Directory	/workspace/10.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_intr_test.394017982
Short name	T76
Test name
Test status
Simulation time	27656822 ps
CPU time	0.62 seconds
Started	Jan 14 01:15:18 PM PST 24
Finished	Jan 14 01:15:19 PM PST 24
Peak memory	201296 kb
Host	smart-3cf36bbd-78f2-435d-8453-313a6c2c98f3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=394017982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.394017982
Directory	/workspace/10.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.3772872960
Short name	T136
Test name
Test status
Simulation time	48791987 ps
CPU time	1.1 seconds
Started	Jan 14 01:15:26 PM PST 24
Finished	Jan 14 01:15:28 PM PST 24
Peak memory	202300 kb
Host	smart-8d16afb0-3078-4fc1-9029-2ee470777f8a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772872960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_ csr_outstanding.3772872960
Directory	/workspace/10.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_tl_errors.456605831
Short name	T7
Test name
Test status
Simulation time	119325936 ps
CPU time	1.74 seconds
Started	Jan 14 01:15:14 PM PST 24
Finished	Jan 14 01:15:18 PM PST 24
Peak memory	202272 kb
Host	smart-6178b323-f9e7-4957-afb6-a9e779deddf6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=456605831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.456605831
Directory	/workspace/10.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2779841038
Short name	T54
Test name
Test status
Simulation time	52722613 ps
CPU time	2.03 seconds
Started	Jan 14 01:15:21 PM PST 24
Finished	Jan 14 01:15:24 PM PST 24
Peak memory	210444 kb
Host	smart-acb7ad9f-4c24-4a80-b4ab-66f537914f09
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779841038 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_mem_rw_with_rand_reset.2779841038
Directory	/workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_csr_rw.2844674658
Short name	T34
Test name
Test status
Simulation time	35808804 ps
CPU time	0.8 seconds
Started	Jan 14 01:15:24 PM PST 24
Finished	Jan 14 01:15:26 PM PST 24
Peak memory	202020 kb
Host	smart-1cc094f1-1305-4792-965e-78cac636828a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844674658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.2844674658
Directory	/workspace/11.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_intr_test.3842193257
Short name	T110
Test name
Test status
Simulation time	24116671 ps
CPU time	0.65 seconds
Started	Jan 14 01:15:22 PM PST 24
Finished	Jan 14 01:15:24 PM PST 24
Peak memory	201332 kb
Host	smart-597244fd-d783-45dc-a7a9-4b3909bf1258
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3842193257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.3842193257
Directory	/workspace/11.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.638213683
Short name	T36
Test name
Test status
Simulation time	102582131 ps
CPU time	1.16 seconds
Started	Jan 14 01:15:23 PM PST 24
Finished	Jan 14 01:15:25 PM PST 24
Peak memory	202252 kb
Host	smart-ba03bf28-65ea-46dc-a479-723fee04546a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638213683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_c sr_outstanding.638213683
Directory	/workspace/11.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_tl_errors.3016865670
Short name	T122
Test name
Test status
Simulation time	53326821 ps
CPU time	1.72 seconds
Started	Jan 14 01:15:24 PM PST 24
Finished	Jan 14 01:15:27 PM PST 24
Peak memory	202204 kb
Host	smart-a338c1d0-da20-4387-bd9e-88ac5910d84c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3016865670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.3016865670
Directory	/workspace/11.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1706666766
Short name	T65
Test name
Test status
Simulation time	268269060 ps
CPU time	2.7 seconds
Started	Jan 14 01:15:20 PM PST 24
Finished	Jan 14 01:15:23 PM PST 24
Peak memory	202244 kb
Host	smart-6b76f4a0-881f-413d-a031-029e94967afa
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1706666766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.1706666766
Directory	/workspace/11.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.3156642105
Short name	T117
Test name
Test status
Simulation time	63147365 ps
CPU time	1.74 seconds
Started	Jan 14 01:15:20 PM PST 24
Finished	Jan 14 01:15:23 PM PST 24
Peak memory	210612 kb
Host	smart-0956e2a6-8a13-4659-b238-3fb32c8ec509
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156642105 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_mem_rw_with_rand_reset.3156642105
Directory	/workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_csr_rw.1744409813
Short name	T106
Test name
Test status
Simulation time	56753485 ps
CPU time	1.02 seconds
Started	Jan 14 01:15:25 PM PST 24
Finished	Jan 14 01:15:27 PM PST 24
Peak memory	202360 kb
Host	smart-98071466-b71e-4311-9759-4514eb079819
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744409813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.1744409813
Directory	/workspace/12.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_intr_test.2132000595
Short name	T121
Test name
Test status
Simulation time	41804227 ps
CPU time	0.69 seconds
Started	Jan 14 01:15:24 PM PST 24
Finished	Jan 14 01:15:26 PM PST 24
Peak memory	201336 kb
Host	smart-9fe5826a-8e93-4bb4-b7e9-002322100d3d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2132000595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.2132000595
Directory	/workspace/12.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3942518690
Short name	T130
Test name
Test status
Simulation time	78596576 ps
CPU time	1.03 seconds
Started	Jan 14 01:15:22 PM PST 24
Finished	Jan 14 01:15:24 PM PST 24
Peak memory	202340 kb
Host	smart-b1a25922-7def-4f76-89d4-da32e4f91753
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942518690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_ csr_outstanding.3942518690
Directory	/workspace/12.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_tl_errors.3604844506
Short name	T41
Test name
Test status
Simulation time	232556684 ps
CPU time	2.87 seconds
Started	Jan 14 01:15:25 PM PST 24
Finished	Jan 14 01:15:29 PM PST 24
Peak memory	202372 kb
Host	smart-e00f49d9-b900-4f6f-ba82-d920344bc9b0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3604844506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.3604844506
Directory	/workspace/12.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.125517290
Short name	T147
Test name
Test status
Simulation time	49069278 ps
CPU time	1.25 seconds
Started	Jan 14 01:15:26 PM PST 24
Finished	Jan 14 01:15:28 PM PST 24
Peak memory	210572 kb
Host	smart-e524b39e-887f-463e-9ffc-daa3b632c212
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125517290 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_mem_rw_with_rand_reset.125517290
Directory	/workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_csr_rw.3615003199
Short name	T47
Test name
Test status
Simulation time	35679749 ps
CPU time	1.02 seconds
Started	Jan 14 01:15:21 PM PST 24
Finished	Jan 14 01:15:23 PM PST 24
Peak memory	202376 kb
Host	smart-d4abbd5e-e591-473b-a9a5-7a6117054db8
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615003199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.3615003199
Directory	/workspace/13.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_intr_test.2659292123
Short name	T80
Test name
Test status
Simulation time	44888594 ps
CPU time	0.66 seconds
Started	Jan 14 01:15:22 PM PST 24
Finished	Jan 14 01:15:24 PM PST 24
Peak memory	201240 kb
Host	smart-8c33bc81-ee25-46d6-9c21-6ae10bf7b937
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2659292123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.2659292123
Directory	/workspace/13.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.491676448
Short name	T59
Test name
Test status
Simulation time	71386022 ps
CPU time	1.01 seconds
Started	Jan 14 01:15:27 PM PST 24
Finished	Jan 14 01:15:29 PM PST 24
Peak memory	201992 kb
Host	smart-ad6a12a3-76dd-48c0-a973-db20adec8360
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491676448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_c sr_outstanding.491676448
Directory	/workspace/13.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_tl_errors.2289216077
Short name	T119
Test name
Test status
Simulation time	86325506 ps
CPU time	2.49 seconds
Started	Jan 14 01:15:20 PM PST 24
Finished	Jan 14 01:15:23 PM PST 24
Peak memory	202208 kb
Host	smart-b6fc7cbc-841c-43ee-befa-2e7d91caa1ac
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2289216077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.2289216077
Directory	/workspace/13.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.2345434417
Short name	T69
Test name
Test status
Simulation time	300148999 ps
CPU time	4.41 seconds
Started	Jan 14 01:15:21 PM PST 24
Finished	Jan 14 01:15:26 PM PST 24
Peak memory	202280 kb
Host	smart-f4e399f3-2be3-4c36-8450-867ad9f6f723
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2345434417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.2345434417
Directory	/workspace/13.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.3854158894
Short name	T105
Test name
Test status
Simulation time	46791858 ps
CPU time	1.19 seconds
Started	Jan 14 01:15:24 PM PST 24
Finished	Jan 14 01:15:26 PM PST 24
Peak memory	202268 kb
Host	smart-fc6da7fe-f3e1-47f5-b543-0e01427b8a2b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854158894 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_mem_rw_with_rand_reset.3854158894
Directory	/workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_csr_rw.3961713181
Short name	T55
Test name
Test status
Simulation time	47584960 ps
CPU time	0.8 seconds
Started	Jan 14 01:15:20 PM PST 24
Finished	Jan 14 01:15:22 PM PST 24
Peak memory	202084 kb
Host	smart-fc869a2d-47e5-461a-a066-265eb362d62b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961713181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.3961713181
Directory	/workspace/14.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.550108355
Short name	T5
Test name
Test status
Simulation time	72164817 ps
CPU time	1.03 seconds
Started	Jan 14 01:15:27 PM PST 24
Finished	Jan 14 01:15:29 PM PST 24
Peak memory	202048 kb
Host	smart-56133fd5-0384-4b8d-8e27-0ca45fd86f4a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550108355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_c sr_outstanding.550108355
Directory	/workspace/14.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3095583971
Short name	T118
Test name
Test status
Simulation time	116231395 ps
CPU time	1.52 seconds
Started	Jan 14 01:15:29 PM PST 24
Finished	Jan 14 01:15:31 PM PST 24
Peak memory	202276 kb
Host	smart-bb2977f2-3188-4df7-a107-283a78b9f021
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3095583971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.3095583971
Directory	/workspace/14.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.2580661723
Short name	T82
Test name
Test status
Simulation time	45772386 ps
CPU time	1.14 seconds
Started	Jan 14 01:15:26 PM PST 24
Finished	Jan 14 01:15:28 PM PST 24
Peak memory	202232 kb
Host	smart-e751a1b8-0685-4e37-8cbc-ae2cb68c8f8c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580661723 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_mem_rw_with_rand_reset.2580661723
Directory	/workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_csr_rw.2190932445
Short name	T152
Test name
Test status
Simulation time	29423774 ps
CPU time	0.79 seconds
Started	Jan 14 01:15:29 PM PST 24
Finished	Jan 14 01:15:30 PM PST 24
Peak memory	202144 kb
Host	smart-d84f979e-79a2-4b19-8cbc-2a20440268de
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190932445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.2190932445
Directory	/workspace/15.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3469007569
Short name	T116
Test name
Test status
Simulation time	88375091 ps
CPU time	1.13 seconds
Started	Jan 14 01:15:29 PM PST 24
Finished	Jan 14 01:15:31 PM PST 24
Peak memory	202360 kb
Host	smart-c562207a-0d23-48f1-a47c-33e87fa9cb27
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469007569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_ csr_outstanding.3469007569
Directory	/workspace/15.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_tl_errors.3050885709
Short name	T15
Test name
Test status
Simulation time	69355218 ps
CPU time	1.87 seconds
Started	Jan 14 01:15:22 PM PST 24
Finished	Jan 14 01:15:25 PM PST 24
Peak memory	202204 kb
Host	smart-da75af6a-7de8-4d0b-ba85-23512ebf8434
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3050885709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.3050885709
Directory	/workspace/15.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.3189355353
Short name	T137
Test name
Test status
Simulation time	59205441 ps
CPU time	1.47 seconds
Started	Jan 14 01:15:26 PM PST 24
Finished	Jan 14 01:15:29 PM PST 24
Peak memory	210528 kb
Host	smart-a684c6b8-7fa7-4794-9851-59016e76d122
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189355353 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_mem_rw_with_rand_reset.3189355353
Directory	/workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3741615396
Short name	T123
Test name
Test status
Simulation time	41422266 ps
CPU time	1.01 seconds
Started	Jan 14 01:15:26 PM PST 24
Finished	Jan 14 01:15:28 PM PST 24
Peak memory	202252 kb
Host	smart-a401af29-d821-48c2-a6ee-07dd9d7388c4
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741615396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_ csr_outstanding.3741615396
Directory	/workspace/16.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1032938009
Short name	T103
Test name
Test status
Simulation time	291758579 ps
CPU time	3.14 seconds
Started	Jan 14 01:15:25 PM PST 24
Finished	Jan 14 01:15:30 PM PST 24
Peak memory	202232 kb
Host	smart-cb702faf-831a-47e7-ac6e-6acc8b2ae0f9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1032938009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.1032938009
Directory	/workspace/16.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.2798216428
Short name	T107
Test name
Test status
Simulation time	65066930 ps
CPU time	1.46 seconds
Started	Jan 14 01:15:31 PM PST 24
Finished	Jan 14 01:15:34 PM PST 24
Peak memory	210404 kb
Host	smart-7befce8a-6356-4fce-900f-da2bbb48f3e9
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798216428 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_mem_rw_with_rand_reset.2798216428
Directory	/workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_csr_rw.2289798338
Short name	T45
Test name
Test status
Simulation time	51409275 ps
CPU time	0.92 seconds
Started	Jan 14 01:15:34 PM PST 24
Finished	Jan 14 01:15:40 PM PST 24
Peak memory	202096 kb
Host	smart-f9cfaff0-0048-4c60-bc00-f0dc91bed28a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289798338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.2289798338
Directory	/workspace/17.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_intr_test.875039415
Short name	T139
Test name
Test status
Simulation time	38216208 ps
CPU time	0.66 seconds
Started	Jan 14 01:15:31 PM PST 24
Finished	Jan 14 01:15:33 PM PST 24
Peak memory	201312 kb
Host	smart-c604316f-779d-4e60-9049-39b47fd0458d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=875039415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.875039415
Directory	/workspace/17.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.2480714593
Short name	T138
Test name
Test status
Simulation time	42762413 ps
CPU time	1.06 seconds
Started	Jan 14 01:15:27 PM PST 24
Finished	Jan 14 01:15:29 PM PST 24
Peak memory	202396 kb
Host	smart-29df6964-3066-4f33-86f4-61daa6357bee
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480714593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_ csr_outstanding.2480714593
Directory	/workspace/17.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_tl_errors.2488038914
Short name	T39
Test name
Test status
Simulation time	207538094 ps
CPU time	2.53 seconds
Started	Jan 14 01:15:33 PM PST 24
Finished	Jan 14 01:15:40 PM PST 24
Peak memory	202204 kb
Host	smart-c534e9d9-cec9-4ab1-9a88-3817deb6b1ff
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2488038914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.2488038914
Directory	/workspace/17.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.1174070128
Short name	T67
Test name
Test status
Simulation time	286785004 ps
CPU time	4.51 seconds
Started	Jan 14 01:15:33 PM PST 24
Finished	Jan 14 01:15:42 PM PST 24
Peak memory	202244 kb
Host	smart-4b3115e1-84a6-4e41-8635-078890b56fa3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1174070128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.1174070128
Directory	/workspace/17.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.651854834
Short name	T124
Test name
Test status
Simulation time	66368978 ps
CPU time	2.21 seconds
Started	Jan 14 01:15:25 PM PST 24
Finished	Jan 14 01:15:28 PM PST 24
Peak memory	210644 kb
Host	smart-a077976d-7652-4cac-a3e9-434d15d70550
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651854834 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_mem_rw_with_rand_reset.651854834
Directory	/workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_csr_rw.1384255224
Short name	T120
Test name
Test status
Simulation time	40276458 ps
CPU time	0.8 seconds
Started	Jan 14 01:15:37 PM PST 24
Finished	Jan 14 01:15:39 PM PST 24
Peak memory	201988 kb
Host	smart-f9a91191-0e7d-4094-8e83-02bd24a20626
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384255224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.1384255224
Directory	/workspace/18.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.2537971792
Short name	T104
Test name
Test status
Simulation time	149443665 ps
CPU time	1.51 seconds
Started	Jan 14 01:15:24 PM PST 24
Finished	Jan 14 01:15:27 PM PST 24
Peak memory	202264 kb
Host	smart-a547947c-f852-4112-95b1-bf7fc98b94d7
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537971792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_ csr_outstanding.2537971792
Directory	/workspace/18.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_tl_errors.785775775
Short name	T126
Test name
Test status
Simulation time	110199043 ps
CPU time	1.53 seconds
Started	Jan 14 01:15:32 PM PST 24
Finished	Jan 14 01:15:35 PM PST 24
Peak memory	202240 kb
Host	smart-e6f72cdc-135c-4940-aa83-7072dec7a744
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=785775775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.785775775
Directory	/workspace/18.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.889874702
Short name	T95
Test name
Test status
Simulation time	54704259 ps
CPU time	1.35 seconds
Started	Jan 14 01:15:36 PM PST 24
Finished	Jan 14 01:15:40 PM PST 24
Peak memory	202284 kb
Host	smart-41e85670-11ce-43bb-8e94-ba468f54c5bf
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889874702 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_mem_rw_with_rand_reset.889874702
Directory	/workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_csr_rw.854790011
Short name	T24
Test name
Test status
Simulation time	65666914 ps
CPU time	1.02 seconds
Started	Jan 14 01:15:26 PM PST 24
Finished	Jan 14 01:15:28 PM PST 24
Peak memory	202344 kb
Host	smart-1c1d766f-cc6a-4b64-bbbd-2bc5f61485c6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854790011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.854790011
Directory	/workspace/19.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_intr_test.3369718019
Short name	T108
Test name
Test status
Simulation time	32892045 ps
CPU time	0.64 seconds
Started	Jan 14 01:15:36 PM PST 24
Finished	Jan 14 01:15:39 PM PST 24
Peak memory	201340 kb
Host	smart-6bb30c33-b20a-4ac3-86cd-ffa4fdb0f769
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3369718019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.3369718019
Directory	/workspace/19.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.1847614461
Short name	T44
Test name
Test status
Simulation time	71205819 ps
CPU time	1.4 seconds
Started	Jan 14 01:15:44 PM PST 24
Finished	Jan 14 01:15:46 PM PST 24
Peak memory	202292 kb
Host	smart-db107ff6-c5d5-43db-a266-c10f2b22c069
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847614461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_ csr_outstanding.1847614461
Directory	/workspace/19.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_tl_errors.1486528325
Short name	T102
Test name
Test status
Simulation time	132645211 ps
CPU time	1.75 seconds
Started	Jan 14 01:15:32 PM PST 24
Finished	Jan 14 01:15:35 PM PST 24
Peak memory	202204 kb
Host	smart-f1db5636-4b75-46d5-8251-f3932c87917e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1486528325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.1486528325
Directory	/workspace/19.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2314516075
Short name	T98
Test name
Test status
Simulation time	254352784 ps
CPU time	4.27 seconds
Started	Jan 14 01:15:45 PM PST 24
Finished	Jan 14 01:15:50 PM PST 24
Peak memory	202292 kb
Host	smart-3514ca16-71a1-433c-9a95-a9d54b80ae7a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2314516075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.2314516075
Directory	/workspace/19.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.1013210204
Short name	T46
Test name
Test status
Simulation time	172237730 ps
CPU time	2.04 seconds
Started	Jan 14 01:15:18 PM PST 24
Finished	Jan 14 01:15:21 PM PST 24
Peak memory	202184 kb
Host	smart-67421ee3-a6b3-40ab-bdbe-60f3f833d207
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013210204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.1013210204
Directory	/workspace/2.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.1244323750
Short name	T135
Test name
Test status
Simulation time	196312710 ps
CPU time	4.65 seconds
Started	Jan 14 01:15:18 PM PST 24
Finished	Jan 14 01:15:23 PM PST 24
Peak memory	202280 kb
Host	smart-2b1902cd-c232-48cf-b18d-91667e4fb69f
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244323750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.1244323750
Directory	/workspace/2.usbdev_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.1355941637
Short name	T28
Test name
Test status
Simulation time	42897896 ps
CPU time	0.78 seconds
Started	Jan 14 01:15:04 PM PST 24
Finished	Jan 14 01:15:09 PM PST 24
Peak memory	201960 kb
Host	smart-5b13d2cb-5915-4ecb-99a1-7aa433255ae8
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355941637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.1355941637
Directory	/workspace/2.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.3615722938
Short name	T90
Test name
Test status
Simulation time	25455472 ps
CPU time	0.93 seconds
Started	Jan 14 01:15:18 PM PST 24
Finished	Jan 14 01:15:20 PM PST 24
Peak memory	210448 kb
Host	smart-ff4d57ba-65af-4eb1-ad7e-ac68ab304c68
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615722938 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_mem_rw_with_rand_reset.3615722938
Directory	/workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_intr_test.3847413535
Short name	T144
Test name
Test status
Simulation time	24707801 ps
CPU time	0.64 seconds
Started	Jan 14 01:15:08 PM PST 24
Finished	Jan 14 01:15:14 PM PST 24
Peak memory	201452 kb
Host	smart-43ee3ecd-1453-47c4-bb2e-d0fff15662b2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3847413535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.3847413535
Directory	/workspace/2.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.3876792715
Short name	T18
Test name
Test status
Simulation time	153473629 ps
CPU time	2.29 seconds
Started	Jan 14 01:15:08 PM PST 24
Finished	Jan 14 01:15:15 PM PST 24
Peak memory	202340 kb
Host	smart-821c6159-eb87-493c-bc95-533254173411
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3876792715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.3876792715
Directory	/workspace/2.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.548200051
Short name	T56
Test name
Test status
Simulation time	215697033 ps
CPU time	1.57 seconds
Started	Jan 14 01:15:09 PM PST 24
Finished	Jan 14 01:15:15 PM PST 24
Peak memory	202104 kb
Host	smart-8b1fd2ea-1754-49fc-9d16-77459ea17d0d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548200051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_cs r_outstanding.548200051
Directory	/workspace/2.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_tl_errors.657767835
Short name	T125
Test name
Test status
Simulation time	85360722 ps
CPU time	1.29 seconds
Started	Jan 14 01:15:17 PM PST 24
Finished	Jan 14 01:15:20 PM PST 24
Peak memory	202332 kb
Host	smart-ab52b261-9008-4e5f-9def-06123ec3c180
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=657767835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.657767835
Directory	/workspace/2.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.2191635301
Short name	T151
Test name
Test status
Simulation time	241484980 ps
CPU time	4.39 seconds
Started	Jan 14 01:15:09 PM PST 24
Finished	Jan 14 01:15:17 PM PST 24
Peak memory	202232 kb
Host	smart-b122bf35-79a4-436e-901e-0ab230623ad0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2191635301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.2191635301
Directory	/workspace/2.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/22.usbdev_intr_test.3374105027
Short name	T128
Test name
Test status
Simulation time	20109049 ps
CPU time	0.65 seconds
Started	Jan 14 01:15:34 PM PST 24
Finished	Jan 14 01:15:39 PM PST 24
Peak memory	201048 kb
Host	smart-c20df172-5b01-486a-8b83-bc0ed730f786
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3374105027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.3374105027
Directory	/workspace/22.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.usbdev_intr_test.2663408565
Short name	T32
Test name
Test status
Simulation time	27317053 ps
CPU time	0.61 seconds
Started	Jan 14 01:15:35 PM PST 24
Finished	Jan 14 01:15:39 PM PST 24
Peak memory	201264 kb
Host	smart-f056226d-f129-4e90-ad15-81a9200e113b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2663408565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.2663408565
Directory	/workspace/23.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.usbdev_intr_test.3133793263
Short name	T146
Test name
Test status
Simulation time	20769998 ps
CPU time	0.65 seconds
Started	Jan 14 01:15:45 PM PST 24
Finished	Jan 14 01:15:46 PM PST 24
Peak memory	201324 kb
Host	smart-acb4e32d-0086-4923-aba6-e7981c1598a1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3133793263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.3133793263
Directory	/workspace/24.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.usbdev_intr_test.2255391865
Short name	T73
Test name
Test status
Simulation time	23558408 ps
CPU time	0.63 seconds
Started	Jan 14 01:15:27 PM PST 24
Finished	Jan 14 01:15:29 PM PST 24
Peak memory	201308 kb
Host	smart-d0590191-cf13-44d2-82c6-dac5be7720cb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2255391865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.2255391865
Directory	/workspace/26.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.usbdev_intr_test.4032690387
Short name	T129
Test name
Test status
Simulation time	45057612 ps
CPU time	0.64 seconds
Started	Jan 14 01:15:34 PM PST 24
Finished	Jan 14 01:15:39 PM PST 24
Peak memory	201256 kb
Host	smart-5dc243f2-df8f-4e33-ace5-3e7ab61014f4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4032690387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.4032690387
Directory	/workspace/28.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.usbdev_intr_test.847119557
Short name	T78
Test name
Test status
Simulation time	19300896 ps
CPU time	0.67 seconds
Started	Jan 14 01:15:34 PM PST 24
Finished	Jan 14 01:15:39 PM PST 24
Peak memory	201180 kb
Host	smart-c728bc23-d6f0-4ffe-8447-13189254992e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=847119557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.847119557
Directory	/workspace/29.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.566368268
Short name	T49
Test name
Test status
Simulation time	191910244 ps
CPU time	1.95 seconds
Started	Jan 14 01:15:10 PM PST 24
Finished	Jan 14 01:15:15 PM PST 24
Peak memory	202208 kb
Host	smart-d4217adc-1b49-449c-81f3-11f0b1dffc2c
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566368268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.566368268
Directory	/workspace/3.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.995423748
Short name	T43
Test name
Test status
Simulation time	366024197 ps
CPU time	8.57 seconds
Started	Jan 14 01:15:11 PM PST 24
Finished	Jan 14 01:15:23 PM PST 24
Peak memory	202224 kb
Host	smart-666d8b85-4631-4bfd-bcb7-66d366d3cd22
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995423748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.995423748
Directory	/workspace/3.usbdev_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2649032543
Short name	T92
Test name
Test status
Simulation time	30100752 ps
CPU time	1.28 seconds
Started	Jan 14 01:15:11 PM PST 24
Finished	Jan 14 01:15:16 PM PST 24
Peak memory	210492 kb
Host	smart-af7d9173-78fe-4528-aebf-36465c0265bd
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649032543 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_mem_rw_with_rand_reset.2649032543
Directory	/workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2685286028
Short name	T48
Test name
Test status
Simulation time	30959767 ps
CPU time	0.77 seconds
Started	Jan 14 01:15:11 PM PST 24
Finished	Jan 14 01:15:15 PM PST 24
Peak memory	202004 kb
Host	smart-6fb475e7-d1c3-48fc-b105-85c20e6528b0
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685286028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.2685286028
Directory	/workspace/3.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_intr_test.3440944529
Short name	T63
Test name
Test status
Simulation time	37532081 ps
CPU time	0.7 seconds
Started	Jan 14 01:15:18 PM PST 24
Finished	Jan 14 01:15:19 PM PST 24
Peak memory	201380 kb
Host	smart-4504d793-eefa-404b-af7c-3009751a6e10
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3440944529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.3440944529
Directory	/workspace/3.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2895646409
Short name	T51
Test name
Test status
Simulation time	76802163 ps
CPU time	2.08 seconds
Started	Jan 14 01:15:12 PM PST 24
Finished	Jan 14 01:15:18 PM PST 24
Peak memory	202200 kb
Host	smart-df341df0-f234-4031-9896-44e0d71a07b3
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2895646409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.2895646409
Directory	/workspace/3.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_mem_walk.1849104887
Short name	T153
Test name
Test status
Simulation time	149337620 ps
CPU time	3.78 seconds
Started	Jan 14 01:15:11 PM PST 24
Finished	Jan 14 01:15:18 PM PST 24
Peak memory	202092 kb
Host	smart-cb6bba00-9599-4233-a728-407e80b54691
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1849104887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.1849104887
Directory	/workspace/3.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.2784896295
Short name	T114
Test name
Test status
Simulation time	35264576 ps
CPU time	0.87 seconds
Started	Jan 14 01:15:11 PM PST 24
Finished	Jan 14 01:15:15 PM PST 24
Peak memory	202276 kb
Host	smart-873463c2-57b1-4d2b-8609-3b2a10bcd4b7
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784896295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_c sr_outstanding.2784896295
Directory	/workspace/3.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.2306679702
Short name	T66
Test name
Test status
Simulation time	282391512 ps
CPU time	2.89 seconds
Started	Jan 14 01:15:05 PM PST 24
Finished	Jan 14 01:15:14 PM PST 24
Peak memory	202304 kb
Host	smart-3c45b68f-a577-4a30-a32b-ff3749c436c0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2306679702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.2306679702
Directory	/workspace/3.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.usbdev_intr_test.574170169
Short name	T150
Test name
Test status
Simulation time	27124662 ps
CPU time	0.67 seconds
Started	Jan 14 01:15:35 PM PST 24
Finished	Jan 14 01:15:39 PM PST 24
Peak memory	201092 kb
Host	smart-eb057501-b2cc-4959-9d0e-1fcbbdf2ea2a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=574170169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.574170169
Directory	/workspace/30.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.usbdev_intr_test.215306777
Short name	T96
Test name
Test status
Simulation time	28406475 ps
CPU time	0.68 seconds
Started	Jan 14 01:15:34 PM PST 24
Finished	Jan 14 01:15:39 PM PST 24
Peak memory	201176 kb
Host	smart-5915ba86-359d-4311-9e35-db88fc94e506
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=215306777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.215306777
Directory	/workspace/31.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.usbdev_intr_test.2862704164
Short name	T71
Test name
Test status
Simulation time	32371124 ps
CPU time	0.62 seconds
Started	Jan 14 01:15:44 PM PST 24
Finished	Jan 14 01:15:45 PM PST 24
Peak memory	201344 kb
Host	smart-7f7bd397-8fc4-4b2b-bd06-b75b43753bbf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2862704164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.2862704164
Directory	/workspace/32.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.usbdev_intr_test.2582910550
Short name	T79
Test name
Test status
Simulation time	25983477 ps
CPU time	0.63 seconds
Started	Jan 14 01:15:31 PM PST 24
Finished	Jan 14 01:15:33 PM PST 24
Peak memory	201424 kb
Host	smart-eee5aa7d-cb0c-4253-8ee1-c87958ef4983
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2582910550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.2582910550
Directory	/workspace/33.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.usbdev_intr_test.1372688506
Short name	T75
Test name
Test status
Simulation time	26913800 ps
CPU time	0.6 seconds
Started	Jan 14 01:15:31 PM PST 24
Finished	Jan 14 01:15:33 PM PST 24
Peak memory	201420 kb
Host	smart-b2d77b76-4e0c-446c-b8b7-b925d1c91e34
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1372688506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.1372688506
Directory	/workspace/36.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2662589420
Short name	T10
Test name
Test status
Simulation time	77276309 ps
CPU time	1.94 seconds
Started	Jan 14 01:15:12 PM PST 24
Finished	Jan 14 01:15:18 PM PST 24
Peak memory	202340 kb
Host	smart-c8ce29cc-8cfb-498d-bf9f-f5aa32d55e0a
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662589420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.2662589420
Directory	/workspace/4.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.3240866822
Short name	T142
Test name
Test status
Simulation time	450363344 ps
CPU time	8.84 seconds
Started	Jan 14 01:15:10 PM PST 24
Finished	Jan 14 01:15:23 PM PST 24
Peak memory	202360 kb
Host	smart-7a1e3e37-8b4d-4d42-95d2-4a4cfaa241e4
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240866822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.3240866822
Directory	/workspace/4.usbdev_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2231666575
Short name	T27
Test name
Test status
Simulation time	57664425 ps
CPU time	0.79 seconds
Started	Jan 14 01:15:14 PM PST 24
Finished	Jan 14 01:15:17 PM PST 24
Peak memory	202004 kb
Host	smart-42c891eb-ee5a-45f6-be5f-c1e7386593dd
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231666575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.2231666575
Directory	/workspace/4.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2160665454
Short name	T97
Test name
Test status
Simulation time	67021930 ps
CPU time	1.63 seconds
Started	Jan 14 01:15:12 PM PST 24
Finished	Jan 14 01:15:18 PM PST 24
Peak memory	210508 kb
Host	smart-0fe39de2-b3c7-4f24-8ecf-203d5d8f1a55
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160665454 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_mem_rw_with_rand_reset.2160665454
Directory	/workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_rw.2392359434
Short name	T109
Test name
Test status
Simulation time	39697459 ps
CPU time	1.03 seconds
Started	Jan 14 01:15:14 PM PST 24
Finished	Jan 14 01:15:18 PM PST 24
Peak memory	202336 kb
Host	smart-5226e773-af3f-48ae-83e1-ef44d8502c54
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392359434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.2392359434
Directory	/workspace/4.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.678774886
Short name	T11
Test name
Test status
Simulation time	46929280 ps
CPU time	1.31 seconds
Started	Jan 14 01:15:12 PM PST 24
Finished	Jan 14 01:15:17 PM PST 24
Peak memory	202308 kb
Host	smart-010c0d60-efe6-470b-b862-b0fee646990f
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=678774886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.678774886
Directory	/workspace/4.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.395937731
Short name	T149
Test name
Test status
Simulation time	81594070 ps
CPU time	1 seconds
Started	Jan 14 01:15:11 PM PST 24
Finished	Jan 14 01:15:15 PM PST 24
Peak memory	202300 kb
Host	smart-86c8271d-6493-4a3a-ba39-911789f2cac3
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395937731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_cs r_outstanding.395937731
Directory	/workspace/4.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_tl_errors.30687274
Short name	T38
Test name
Test status
Simulation time	153251082 ps
CPU time	1.83 seconds
Started	Jan 14 01:15:17 PM PST 24
Finished	Jan 14 01:15:20 PM PST 24
Peak memory	202364 kb
Host	smart-a320c07a-175f-43e9-bb37-8fa23c56de31
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=30687274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.30687274
Directory	/workspace/4.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/40.usbdev_intr_test.2174200637
Short name	T30
Test name
Test status
Simulation time	30502294 ps
CPU time	0.64 seconds
Started	Jan 14 01:15:46 PM PST 24
Finished	Jan 14 01:15:47 PM PST 24
Peak memory	200680 kb
Host	smart-c1c0ea0c-00cf-45c6-872c-45a430696a31
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2174200637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.2174200637
Directory	/workspace/40.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.usbdev_intr_test.1764097533
Short name	T33
Test name
Test status
Simulation time	25901646 ps
CPU time	0.72 seconds
Started	Jan 14 01:15:35 PM PST 24
Finished	Jan 14 01:15:39 PM PST 24
Peak memory	201384 kb
Host	smart-cda36307-fb03-46b2-af09-7cadd12b7318
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1764097533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.1764097533
Directory	/workspace/41.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.usbdev_intr_test.487970790
Short name	T84
Test name
Test status
Simulation time	18640520 ps
CPU time	0.64 seconds
Started	Jan 14 01:15:45 PM PST 24
Finished	Jan 14 01:15:47 PM PST 24
Peak memory	201360 kb
Host	smart-9b98126f-272d-412d-b65a-db1d85e292fb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=487970790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.487970790
Directory	/workspace/42.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.usbdev_intr_test.1966507591
Short name	T143
Test name
Test status
Simulation time	32123954 ps
CPU time	0.69 seconds
Started	Jan 14 01:15:39 PM PST 24
Finished	Jan 14 01:15:43 PM PST 24
Peak memory	201284 kb
Host	smart-0bb19a12-67d4-4239-83cc-fd64913dacb0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1966507591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.1966507591
Directory	/workspace/43.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.usbdev_intr_test.1132090596
Short name	T94
Test name
Test status
Simulation time	23710747 ps
CPU time	0.6 seconds
Started	Jan 14 01:15:43 PM PST 24
Finished	Jan 14 01:15:44 PM PST 24
Peak memory	201388 kb
Host	smart-255339b6-6247-4e7e-96cd-46a1fd8ffd79
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1132090596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.1132090596
Directory	/workspace/46.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.usbdev_intr_test.3423610086
Short name	T101
Test name
Test status
Simulation time	43183348 ps
CPU time	0.66 seconds
Started	Jan 14 01:15:40 PM PST 24
Finished	Jan 14 01:15:43 PM PST 24
Peak memory	201404 kb
Host	smart-5988f9b6-31ca-4959-a943-b7e2ef452080
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3423610086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.3423610086
Directory	/workspace/47.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.usbdev_intr_test.3909453592
Short name	T112
Test name
Test status
Simulation time	30243979 ps
CPU time	0.66 seconds
Started	Jan 14 01:15:46 PM PST 24
Finished	Jan 14 01:15:47 PM PST 24
Peak memory	201240 kb
Host	smart-1932798c-cb5f-4d8a-9ccc-365a32e5f710
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3909453592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.3909453592
Directory	/workspace/48.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1995364519
Short name	T58
Test name
Test status
Simulation time	46809820 ps
CPU time	1.29 seconds
Started	Jan 14 01:15:14 PM PST 24
Finished	Jan 14 01:15:18 PM PST 24
Peak memory	218656 kb
Host	smart-d68a36a5-5ad0-4b64-b4a0-b131bb3f33e7
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995364519 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_mem_rw_with_rand_reset.1995364519
Directory	/workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_csr_rw.171087636
Short name	T61
Test name
Test status
Simulation time	68259952 ps
CPU time	0.99 seconds
Started	Jan 14 01:15:13 PM PST 24
Finished	Jan 14 01:15:17 PM PST 24
Peak memory	202388 kb
Host	smart-a7c49f86-848e-4dab-8462-f5a9efa54c25
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171087636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.171087636
Directory	/workspace/5.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_intr_test.2220454464
Short name	T132
Test name
Test status
Simulation time	30611736 ps
CPU time	0.65 seconds
Started	Jan 14 01:15:19 PM PST 24
Finished	Jan 14 01:15:21 PM PST 24
Peak memory	201416 kb
Host	smart-7c074a12-e049-4d0b-ad15-faf99dbab812
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2220454464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.2220454464
Directory	/workspace/5.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.8790351
Short name	T113
Test name
Test status
Simulation time	140307061 ps
CPU time	1.72 seconds
Started	Jan 14 01:15:11 PM PST 24
Finished	Jan 14 01:15:16 PM PST 24
Peak memory	202328 kb
Host	smart-f2764373-7467-4bb0-9750-a76f90613336
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8790351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_ outstanding.8790351
Directory	/workspace/5.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_tl_errors.2317421081
Short name	T148
Test name
Test status
Simulation time	85884482 ps
CPU time	1.17 seconds
Started	Jan 14 01:15:25 PM PST 24
Finished	Jan 14 01:15:28 PM PST 24
Peak memory	202320 kb
Host	smart-2dd11c93-fb72-4a23-a193-2aef5860ca32
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2317421081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.2317421081
Directory	/workspace/5.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.1310951379
Short name	T64
Test name
Test status
Simulation time	330503894 ps
CPU time	3.09 seconds
Started	Jan 14 01:15:13 PM PST 24
Finished	Jan 14 01:15:19 PM PST 24
Peak memory	202352 kb
Host	smart-51fe731c-17f3-4dec-b164-9dc1b7bad9db
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1310951379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.1310951379
Directory	/workspace/5.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3198284568
Short name	T115
Test name
Test status
Simulation time	75381071 ps
CPU time	1.48 seconds
Started	Jan 14 01:15:25 PM PST 24
Finished	Jan 14 01:15:28 PM PST 24
Peak memory	210540 kb
Host	smart-3b3ca672-c961-4f70-8c55-658958422b01
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198284568 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_mem_rw_with_rand_reset.3198284568
Directory	/workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_intr_test.1993614804
Short name	T62
Test name
Test status
Simulation time	23543192 ps
CPU time	0.61 seconds
Started	Jan 14 01:15:12 PM PST 24
Finished	Jan 14 01:15:16 PM PST 24
Peak memory	201384 kb
Host	smart-5e629ebb-aaed-4a79-9e82-dfc26b5bf441
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1993614804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.1993614804
Directory	/workspace/6.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.4016589510
Short name	T57
Test name
Test status
Simulation time	132142281 ps
CPU time	1.34 seconds
Started	Jan 14 01:15:12 PM PST 24
Finished	Jan 14 01:15:17 PM PST 24
Peak memory	202244 kb
Host	smart-42b89aad-d861-4c62-bfee-ebb197c440c8
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016589510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_c sr_outstanding.4016589510
Directory	/workspace/6.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1472951409
Short name	T42
Test name
Test status
Simulation time	99502535 ps
CPU time	3.2 seconds
Started	Jan 14 01:15:13 PM PST 24
Finished	Jan 14 01:15:19 PM PST 24
Peak memory	202340 kb
Host	smart-dd7596fd-9bdf-49e6-82d1-305ef57d322a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1472951409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.1472951409
Directory	/workspace/6.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.3702552139
Short name	T60
Test name
Test status
Simulation time	377803846 ps
CPU time	3.11 seconds
Started	Jan 14 01:15:10 PM PST 24
Finished	Jan 14 01:15:17 PM PST 24
Peak memory	202216 kb
Host	smart-6408d819-4793-4dd0-8141-219943056c43
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3702552139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.3702552139
Directory	/workspace/6.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.2077758925
Short name	T89
Test name
Test status
Simulation time	34969144 ps
CPU time	1 seconds
Started	Jan 14 01:15:25 PM PST 24
Finished	Jan 14 01:15:28 PM PST 24
Peak memory	202248 kb
Host	smart-1bf525b8-d1b4-405e-80a4-0dc702e720b5
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077758925 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_mem_rw_with_rand_reset.2077758925
Directory	/workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_csr_rw.20583025
Short name	T83
Test name
Test status
Simulation time	40795867 ps
CPU time	1 seconds
Started	Jan 14 01:15:20 PM PST 24
Finished	Jan 14 01:15:22 PM PST 24
Peak memory	202368 kb
Host	smart-4f50cf99-487e-44cd-8791-6a92ae52e709
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20583025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.20583025
Directory	/workspace/7.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_intr_test.1234712413
Short name	T31
Test name
Test status
Simulation time	30974215 ps
CPU time	0.63 seconds
Started	Jan 14 01:15:12 PM PST 24
Finished	Jan 14 01:15:17 PM PST 24
Peak memory	201352 kb
Host	smart-8708461c-305a-44af-8bc0-e3deb5eb8769
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1234712413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.1234712413
Directory	/workspace/7.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.804726442
Short name	T131
Test name
Test status
Simulation time	81793138 ps
CPU time	1.11 seconds
Started	Jan 14 01:15:13 PM PST 24
Finished	Jan 14 01:15:17 PM PST 24
Peak memory	202348 kb
Host	smart-44b390f9-63de-46c5-984a-a7b2dd36e45e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804726442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_cs r_outstanding.804726442
Directory	/workspace/7.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_tl_errors.2863204268
Short name	T127
Test name
Test status
Simulation time	153245973 ps
CPU time	1.72 seconds
Started	Jan 14 01:15:12 PM PST 24
Finished	Jan 14 01:15:18 PM PST 24
Peak memory	202256 kb
Host	smart-615b4b90-6673-4d75-a6b8-60172bffdcba
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2863204268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.2863204268
Directory	/workspace/7.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1755995397
Short name	T20
Test name
Test status
Simulation time	316211727 ps
CPU time	3.08 seconds
Started	Jan 14 01:15:25 PM PST 24
Finished	Jan 14 01:15:29 PM PST 24
Peak memory	202304 kb
Host	smart-7073e10a-5e5d-4f88-914f-01d886c78339
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1755995397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.1755995397
Directory	/workspace/7.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.1799318827
Short name	T85
Test name
Test status
Simulation time	29890626 ps
CPU time	1.18 seconds
Started	Jan 14 01:15:25 PM PST 24
Finished	Jan 14 01:15:27 PM PST 24
Peak memory	210504 kb
Host	smart-cf93f1e3-eb10-45bf-a602-2b4f3938ab9c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799318827 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_mem_rw_with_rand_reset.1799318827
Directory	/workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_csr_rw.1303157546
Short name	T53
Test name
Test status
Simulation time	51772659 ps
CPU time	0.83 seconds
Started	Jan 14 01:15:16 PM PST 24
Finished	Jan 14 01:15:19 PM PST 24
Peak memory	201908 kb
Host	smart-8cacbf73-3e2d-4b99-a95f-74d673c812e8
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303157546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.1303157546
Directory	/workspace/8.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.253953068
Short name	T35
Test name
Test status
Simulation time	68433828 ps
CPU time	1.1 seconds
Started	Jan 14 01:15:25 PM PST 24
Finished	Jan 14 01:15:28 PM PST 24
Peak memory	202332 kb
Host	smart-4667015f-54fd-4cbd-93e3-05b7a4b3da60
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253953068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_cs r_outstanding.253953068
Directory	/workspace/8.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.1513303793
Short name	T88
Test name
Test status
Simulation time	36588486 ps
CPU time	1.35 seconds
Started	Jan 14 01:15:21 PM PST 24
Finished	Jan 14 01:15:23 PM PST 24
Peak memory	210760 kb
Host	smart-a554b0ba-0f69-41d2-8fb5-c6934bac27db
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513303793 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_mem_rw_with_rand_reset.1513303793
Directory	/workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_csr_rw.442426714
Short name	T52
Test name
Test status
Simulation time	51562043 ps
CPU time	0.86 seconds
Started	Jan 14 01:15:28 PM PST 24
Finished	Jan 14 01:15:30 PM PST 24
Peak memory	201988 kb
Host	smart-a6eed0f7-ffb9-4ea1-a2d6-c051da9bd000
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442426714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.442426714
Directory	/workspace/9.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_intr_test.1876395767
Short name	T134
Test name
Test status
Simulation time	25918390 ps
CPU time	0.64 seconds
Started	Jan 14 01:15:18 PM PST 24
Finished	Jan 14 01:15:20 PM PST 24
Peak memory	201344 kb
Host	smart-733e2ca4-f44c-434b-873d-993f28e81253
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1876395767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.1876395767
Directory	/workspace/9.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_tl_errors.168444735
Short name	T145
Test name
Test status
Simulation time	263730648 ps
CPU time	2.81 seconds
Started	Jan 14 01:15:24 PM PST 24
Finished	Jan 14 01:15:28 PM PST 24
Peak memory	202236 kb
Host	smart-f668829a-a993-4cd9-9df7-f7e705ff1d41
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=168444735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.168444735
Directory	/workspace/9.usbdev_tl_errors/latest

Test location	/workspace/coverage/default/3.usbdev_sec_cm.3925342591
Short name	T1
Test name
Test status
Simulation time	83876015 ps
CPU time	0.91 seconds
Started	Jan 14 01:10:34 PM PST 24
Finished	Jan 14 01:10:36 PM PST 24
Peak memory	220828 kb
Host	smart-fb9bb9ca-2210-4e5f-bd93-266d382d7c4d
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3925342591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.3925342591
Directory	/workspace/3.usbdev_sec_cm/latest