Summary for Variable cp_intr_pin
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
17 |
0 |
17 |
100.00 |
User Defined Bins for cp_intr_pin
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_pins[0] |
276 |
1 |
|
T6 |
8 |
|
T7 |
2 |
|
T9 |
2 |
all_pins[1] |
276 |
1 |
|
T6 |
8 |
|
T7 |
2 |
|
T9 |
2 |
all_pins[2] |
276 |
1 |
|
T6 |
8 |
|
T7 |
2 |
|
T9 |
2 |
all_pins[3] |
276 |
1 |
|
T6 |
8 |
|
T7 |
2 |
|
T9 |
2 |
all_pins[4] |
276 |
1 |
|
T6 |
8 |
|
T7 |
2 |
|
T9 |
2 |
all_pins[5] |
276 |
1 |
|
T6 |
8 |
|
T7 |
2 |
|
T9 |
2 |
all_pins[6] |
276 |
1 |
|
T6 |
8 |
|
T7 |
2 |
|
T9 |
2 |
all_pins[7] |
276 |
1 |
|
T6 |
8 |
|
T7 |
2 |
|
T9 |
2 |
all_pins[8] |
276 |
1 |
|
T6 |
8 |
|
T7 |
2 |
|
T9 |
2 |
all_pins[9] |
276 |
1 |
|
T6 |
8 |
|
T7 |
2 |
|
T9 |
2 |
all_pins[10] |
276 |
1 |
|
T6 |
8 |
|
T7 |
2 |
|
T9 |
2 |
all_pins[11] |
276 |
1 |
|
T6 |
8 |
|
T7 |
2 |
|
T9 |
2 |
all_pins[12] |
276 |
1 |
|
T6 |
8 |
|
T7 |
2 |
|
T9 |
2 |
all_pins[13] |
276 |
1 |
|
T6 |
8 |
|
T7 |
2 |
|
T9 |
2 |
all_pins[14] |
276 |
1 |
|
T6 |
8 |
|
T7 |
2 |
|
T9 |
2 |
all_pins[15] |
276 |
1 |
|
T6 |
8 |
|
T7 |
2 |
|
T9 |
2 |
all_pins[16] |
276 |
1 |
|
T6 |
8 |
|
T7 |
2 |
|
T9 |
2 |
Summary for Variable cp_intr_pin_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for cp_intr_pin_value
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x0] |
3899 |
1 |
|
T6 |
103 |
|
T7 |
34 |
|
T9 |
34 |
values[0x1] |
793 |
1 |
|
T6 |
33 |
|
T32 |
22 |
|
T29 |
21 |
transitions[0x0=>0x1] |
580 |
1 |
|
T6 |
22 |
|
T32 |
12 |
|
T29 |
12 |
transitions[0x1=>0x0] |
587 |
1 |
|
T6 |
22 |
|
T32 |
12 |
|
T29 |
12 |
Summary for Cross cp_intr_pins_all_values
Samples crossed: cp_intr_pin cp_intr_pin_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
68 |
0 |
68 |
100.00 |
|
Automatically Generated Cross Bins for cp_intr_pins_all_values
Bins
cp_intr_pin | cp_intr_pin_value | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_pins[0] |
values[0x0] |
239 |
1 |
|
T6 |
6 |
|
T7 |
2 |
|
T9 |
2 |
all_pins[0] |
values[0x1] |
37 |
1 |
|
T6 |
2 |
|
T29 |
2 |
|
T30 |
3 |
all_pins[0] |
transitions[0x0=>0x1] |
27 |
1 |
|
T6 |
1 |
|
T29 |
2 |
|
T30 |
3 |
all_pins[0] |
transitions[0x1=>0x0] |
35 |
1 |
|
T31 |
1 |
|
T33 |
2 |
|
T73 |
1 |
all_pins[1] |
values[0x0] |
231 |
1 |
|
T6 |
7 |
|
T7 |
2 |
|
T9 |
2 |
all_pins[1] |
values[0x1] |
45 |
1 |
|
T6 |
1 |
|
T31 |
1 |
|
T33 |
2 |
all_pins[1] |
transitions[0x0=>0x1] |
37 |
1 |
|
T6 |
1 |
|
T33 |
1 |
|
T73 |
1 |
all_pins[1] |
transitions[0x1=>0x0] |
52 |
1 |
|
T6 |
3 |
|
T32 |
1 |
|
T31 |
1 |
all_pins[2] |
values[0x0] |
216 |
1 |
|
T6 |
5 |
|
T7 |
2 |
|
T9 |
2 |
all_pins[2] |
values[0x1] |
60 |
1 |
|
T6 |
3 |
|
T32 |
1 |
|
T31 |
2 |
all_pins[2] |
transitions[0x0=>0x1] |
46 |
1 |
|
T6 |
1 |
|
T32 |
1 |
|
T31 |
2 |
all_pins[2] |
transitions[0x1=>0x0] |
35 |
1 |
|
T6 |
3 |
|
T29 |
3 |
|
T30 |
2 |
all_pins[3] |
values[0x0] |
227 |
1 |
|
T6 |
3 |
|
T7 |
2 |
|
T9 |
2 |
all_pins[3] |
values[0x1] |
49 |
1 |
|
T6 |
5 |
|
T29 |
3 |
|
T30 |
2 |
all_pins[3] |
transitions[0x0=>0x1] |
36 |
1 |
|
T6 |
5 |
|
T29 |
2 |
|
T30 |
2 |
all_pins[3] |
transitions[0x1=>0x0] |
44 |
1 |
|
T32 |
3 |
|
T30 |
1 |
|
T31 |
2 |
all_pins[4] |
values[0x0] |
219 |
1 |
|
T6 |
8 |
|
T7 |
2 |
|
T9 |
2 |
all_pins[4] |
values[0x1] |
57 |
1 |
|
T32 |
3 |
|
T29 |
1 |
|
T30 |
1 |
all_pins[4] |
transitions[0x0=>0x1] |
42 |
1 |
|
T29 |
1 |
|
T30 |
1 |
|
T31 |
2 |
all_pins[4] |
transitions[0x1=>0x0] |
28 |
1 |
|
T6 |
3 |
|
T33 |
2 |
|
T70 |
1 |
all_pins[5] |
values[0x0] |
233 |
1 |
|
T6 |
5 |
|
T7 |
2 |
|
T9 |
2 |
all_pins[5] |
values[0x1] |
43 |
1 |
|
T6 |
3 |
|
T32 |
3 |
|
T33 |
3 |
all_pins[5] |
transitions[0x0=>0x1] |
27 |
1 |
|
T6 |
1 |
|
T33 |
2 |
|
T70 |
2 |
all_pins[5] |
transitions[0x1=>0x0] |
22 |
1 |
|
T30 |
1 |
|
T33 |
1 |
|
T70 |
1 |
all_pins[6] |
values[0x0] |
238 |
1 |
|
T6 |
6 |
|
T7 |
2 |
|
T9 |
2 |
all_pins[6] |
values[0x1] |
38 |
1 |
|
T6 |
2 |
|
T32 |
3 |
|
T30 |
1 |
all_pins[6] |
transitions[0x0=>0x1] |
31 |
1 |
|
T6 |
2 |
|
T32 |
3 |
|
T30 |
1 |
all_pins[6] |
transitions[0x1=>0x0] |
31 |
1 |
|
T6 |
1 |
|
T32 |
1 |
|
T33 |
2 |
all_pins[7] |
values[0x0] |
238 |
1 |
|
T6 |
7 |
|
T7 |
2 |
|
T9 |
2 |
all_pins[7] |
values[0x1] |
38 |
1 |
|
T6 |
1 |
|
T32 |
1 |
|
T33 |
3 |
all_pins[7] |
transitions[0x0=>0x1] |
23 |
1 |
|
T33 |
2 |
|
T70 |
1 |
|
T62 |
1 |
all_pins[7] |
transitions[0x1=>0x0] |
33 |
1 |
|
T6 |
2 |
|
T30 |
2 |
|
T73 |
2 |
all_pins[8] |
values[0x0] |
228 |
1 |
|
T6 |
5 |
|
T7 |
2 |
|
T9 |
2 |
all_pins[8] |
values[0x1] |
48 |
1 |
|
T6 |
3 |
|
T32 |
1 |
|
T30 |
2 |
all_pins[8] |
transitions[0x0=>0x1] |
32 |
1 |
|
T6 |
2 |
|
T30 |
2 |
|
T73 |
2 |
all_pins[8] |
transitions[0x1=>0x0] |
28 |
1 |
|
T32 |
2 |
|
T29 |
1 |
|
T30 |
1 |
all_pins[9] |
values[0x0] |
232 |
1 |
|
T6 |
7 |
|
T7 |
2 |
|
T9 |
2 |
all_pins[9] |
values[0x1] |
44 |
1 |
|
T6 |
1 |
|
T32 |
3 |
|
T29 |
1 |
all_pins[9] |
transitions[0x0=>0x1] |
35 |
1 |
|
T6 |
1 |
|
T32 |
2 |
|
T30 |
1 |
all_pins[9] |
transitions[0x1=>0x0] |
37 |
1 |
|
T32 |
1 |
|
T29 |
2 |
|
T31 |
2 |
all_pins[10] |
values[0x0] |
230 |
1 |
|
T6 |
8 |
|
T7 |
2 |
|
T9 |
2 |
all_pins[10] |
values[0x1] |
46 |
1 |
|
T32 |
2 |
|
T29 |
3 |
|
T31 |
2 |
all_pins[10] |
transitions[0x0=>0x1] |
35 |
1 |
|
T32 |
2 |
|
T29 |
1 |
|
T31 |
2 |
all_pins[10] |
transitions[0x1=>0x0] |
39 |
1 |
|
T6 |
1 |
|
T29 |
1 |
|
T30 |
2 |
all_pins[11] |
values[0x0] |
226 |
1 |
|
T6 |
7 |
|
T7 |
2 |
|
T9 |
2 |
all_pins[11] |
values[0x1] |
50 |
1 |
|
T6 |
1 |
|
T29 |
3 |
|
T30 |
2 |
all_pins[11] |
transitions[0x0=>0x1] |
37 |
1 |
|
T6 |
1 |
|
T29 |
2 |
|
T30 |
2 |
all_pins[11] |
transitions[0x1=>0x0] |
33 |
1 |
|
T6 |
3 |
|
T32 |
3 |
|
T29 |
1 |
all_pins[12] |
values[0x0] |
230 |
1 |
|
T6 |
5 |
|
T7 |
2 |
|
T9 |
2 |
all_pins[12] |
values[0x1] |
46 |
1 |
|
T6 |
3 |
|
T32 |
3 |
|
T29 |
2 |
all_pins[12] |
transitions[0x0=>0x1] |
32 |
1 |
|
T6 |
2 |
|
T32 |
2 |
|
T31 |
2 |
all_pins[12] |
transitions[0x1=>0x0] |
40 |
1 |
|
T29 |
1 |
|
T30 |
1 |
|
T33 |
3 |
all_pins[13] |
values[0x0] |
222 |
1 |
|
T6 |
7 |
|
T7 |
2 |
|
T9 |
2 |
all_pins[13] |
values[0x1] |
54 |
1 |
|
T6 |
1 |
|
T32 |
1 |
|
T29 |
3 |
all_pins[13] |
transitions[0x0=>0x1] |
45 |
1 |
|
T32 |
1 |
|
T29 |
2 |
|
T31 |
1 |
all_pins[13] |
transitions[0x1=>0x0] |
39 |
1 |
|
T6 |
4 |
|
T30 |
1 |
|
T31 |
2 |
all_pins[14] |
values[0x0] |
228 |
1 |
|
T6 |
3 |
|
T7 |
2 |
|
T9 |
2 |
all_pins[14] |
values[0x1] |
48 |
1 |
|
T6 |
5 |
|
T29 |
1 |
|
T30 |
2 |
all_pins[14] |
transitions[0x0=>0x1] |
31 |
1 |
|
T6 |
5 |
|
T29 |
1 |
|
T31 |
2 |
all_pins[14] |
transitions[0x1=>0x0] |
24 |
1 |
|
T32 |
1 |
|
T33 |
1 |
|
T70 |
1 |
all_pins[15] |
values[0x0] |
235 |
1 |
|
T6 |
8 |
|
T7 |
2 |
|
T9 |
2 |
all_pins[15] |
values[0x1] |
41 |
1 |
|
T32 |
1 |
|
T30 |
2 |
|
T33 |
1 |
all_pins[15] |
transitions[0x0=>0x1] |
33 |
1 |
|
T32 |
1 |
|
T30 |
1 |
|
T33 |
1 |
all_pins[15] |
transitions[0x1=>0x0] |
41 |
1 |
|
T6 |
2 |
|
T29 |
2 |
|
T31 |
2 |
all_pins[16] |
values[0x0] |
227 |
1 |
|
T6 |
6 |
|
T7 |
2 |
|
T9 |
2 |
all_pins[16] |
values[0x1] |
49 |
1 |
|
T6 |
2 |
|
T29 |
2 |
|
T30 |
1 |
all_pins[16] |
transitions[0x0=>0x1] |
31 |
1 |
|
T29 |
1 |
|
T31 |
2 |
|
T70 |
2 |
all_pins[16] |
transitions[0x1=>0x0] |
26 |
1 |
|
T29 |
1 |
|
T30 |
3 |
|
T72 |
1 |