Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=16}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=16}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=16}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	23	0	23	100.00
Crosses	102	0	102	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=16}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	17	0	17	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=16}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	102	0	102	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	199	1		T6	7		T32	4		T29	7
all_values[1]	199	1		T6	7		T32	4		T29	7
all_values[2]	199	1		T6	7		T32	4		T29	7
all_values[3]	199	1		T6	7		T32	4		T29	7
all_values[4]	199	1		T6	7		T32	4		T29	7
all_values[5]	199	1		T6	7		T32	4		T29	7
all_values[6]	199	1		T6	7		T32	4		T29	7
all_values[7]	199	1		T6	7		T32	4		T29	7
all_values[8]	199	1		T6	7		T32	4		T29	7
all_values[9]	199	1		T6	7		T32	4		T29	7
all_values[10]	199	1		T6	7		T32	4		T29	7
all_values[11]	199	1		T6	7		T32	4		T29	7
all_values[12]	199	1		T6	7		T32	4		T29	7
all_values[13]	199	1		T6	7		T32	4		T29	7
all_values[14]	199	1		T6	7		T32	4		T29	7
all_values[15]	199	1		T6	7		T32	4		T29	7
all_values[16]	199	1		T6	7		T32	4		T29	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1890	1		T6	75		T32	32		T29	70
auto[1]	1493	1		T6	44		T32	36		T29	49

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	626	1		T6	23		T32	21		T29	20
auto[1]	2757	1		T6	96		T32	47		T29	99

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2026	1		T6	73		T32	43		T29	74
auto[1]	1357	1		T6	46		T32	25		T29	45

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	102	0	102	100.00
Automatically Generated Cross Bins	102	0	102	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	20	1		T6	2		T30	1		T31	1
all_values[0]	auto[0]	auto[0]	auto[1]	47	1		T6	1		T29	3		T33	1
all_values[0]	auto[0]	auto[1]	auto[0]	14	1		T32	4		T70	3		T77	3
all_values[0]	auto[0]	auto[1]	auto[1]	37	1		T6	3		T30	1		T31	2
all_values[0]	auto[1]	auto[0]	auto[1]	54	1		T29	4		T30	1		T31	1
all_values[0]	auto[1]	auto[1]	auto[1]	27	1		T6	1		T30	1		T33	1
all_values[1]	auto[0]	auto[0]	auto[0]	30	1		T6	2		T32	2		T30	1
all_values[1]	auto[0]	auto[0]	auto[1]	36	1		T6	1		T32	1		T29	2
all_values[1]	auto[0]	auto[1]	auto[0]	10	1		T6	1		T30	1		T33	2
all_values[1]	auto[0]	auto[1]	auto[1]	32	1		T6	2		T33	1		T73	2
all_values[1]	auto[1]	auto[0]	auto[1]	51	1		T32	1		T29	5		T31	1
all_values[1]	auto[1]	auto[1]	auto[1]	40	1		T6	1		T30	1		T31	1
all_values[2]	auto[0]	auto[0]	auto[0]	15	1		T6	4		T31	1		T33	1
all_values[2]	auto[0]	auto[0]	auto[1]	47	1		T32	3		T29	4		T30	3
all_values[2]	auto[0]	auto[1]	auto[0]	9	1		T77	1		T75	1		T78	2
all_values[2]	auto[0]	auto[1]	auto[1]	43	1		T6	1		T33	2		T73	1
all_values[2]	auto[1]	auto[0]	auto[1]	42	1		T29	3		T30	1		T31	1
all_values[2]	auto[1]	auto[1]	auto[1]	43	1		T6	2		T32	1		T31	1
all_values[3]	auto[0]	auto[0]	auto[0]	24	1		T6	1		T32	3		T30	1
all_values[3]	auto[0]	auto[0]	auto[1]	33	1		T29	3		T30	1		T31	1
all_values[3]	auto[0]	auto[1]	auto[0]	13	1		T32	1		T71	2		T74	1
all_values[3]	auto[0]	auto[1]	auto[1]	49	1		T6	4		T29	2		T30	1
all_values[3]	auto[1]	auto[0]	auto[1]	42	1		T6	2		T31	3		T33	2
all_values[3]	auto[1]	auto[1]	auto[1]	38	1		T29	2		T30	1		T33	2
all_values[4]	auto[0]	auto[0]	auto[0]	23	1		T29	1		T30	1		T31	2
all_values[4]	auto[0]	auto[0]	auto[1]	36	1		T6	3		T29	2		T30	1
all_values[4]	auto[0]	auto[1]	auto[0]	11	1		T70	1		T62	1		T75	2
all_values[4]	auto[0]	auto[1]	auto[1]	41	1		T32	2		T30	1		T31	1
all_values[4]	auto[1]	auto[0]	auto[1]	49	1		T6	4		T32	1		T29	2
all_values[4]	auto[1]	auto[1]	auto[1]	39	1		T32	1		T29	2		T30	1
all_values[5]	auto[0]	auto[0]	auto[0]	31	1		T29	4		T30	2		T31	2
all_values[5]	auto[0]	auto[0]	auto[1]	35	1		T6	1		T32	1		T31	1
all_values[5]	auto[0]	auto[1]	auto[0]	19	1		T29	3		T30	2		T76	2
all_values[5]	auto[0]	auto[1]	auto[1]	46	1		T6	1		T32	1		T33	3
all_values[5]	auto[1]	auto[0]	auto[1]	43	1		T6	3		T31	1		T33	1
all_values[5]	auto[1]	auto[1]	auto[1]	25	1		T6	2		T32	2		T33	2
all_values[6]	auto[0]	auto[0]	auto[0]	22	1		T6	1		T30	1		T31	1
all_values[6]	auto[0]	auto[0]	auto[1]	38	1		T6	1		T32	1		T29	2
all_values[6]	auto[0]	auto[1]	auto[0]	12	1		T29	1		T73	2		T74	2
all_values[6]	auto[0]	auto[1]	auto[1]	43	1		T6	3		T32	1		T29	3
all_values[6]	auto[1]	auto[0]	auto[1]	53	1		T6	2		T31	1		T33	2
all_values[6]	auto[1]	auto[1]	auto[1]	31	1		T32	2		T29	1		T30	1
all_values[7]	auto[0]	auto[0]	auto[0]	24	1		T29	1		T30	1		T31	3
all_values[7]	auto[0]	auto[0]	auto[1]	47	1		T6	4		T32	1		T29	2
all_values[7]	auto[0]	auto[1]	auto[0]	15	1		T29	3		T30	1		T31	1
all_values[7]	auto[0]	auto[1]	auto[1]	37	1		T33	1		T73	1		T70	2
all_values[7]	auto[1]	auto[0]	auto[1]	43	1		T6	2		T32	2		T29	1
all_values[7]	auto[1]	auto[1]	auto[1]	33	1		T6	1		T32	1		T30	1
all_values[8]	auto[0]	auto[0]	auto[0]	30	1		T6	2		T30	2		T72	1
all_values[8]	auto[0]	auto[0]	auto[1]	32	1		T32	1		T29	1		T33	2
all_values[8]	auto[0]	auto[1]	auto[0]	13	1		T6	1		T32	1		T73	1
all_values[8]	auto[0]	auto[1]	auto[1]	46	1		T6	1		T29	2		T30	1
all_values[8]	auto[1]	auto[0]	auto[1]	43	1		T6	2		T32	1		T29	4
all_values[8]	auto[1]	auto[1]	auto[1]	35	1		T6	1		T32	1		T33	2
all_values[9]	auto[0]	auto[0]	auto[0]	20	1		T29	1		T31	3		T33	1
all_values[9]	auto[0]	auto[0]	auto[1]	46	1		T6	3		T29	1		T30	1
all_values[9]	auto[0]	auto[1]	auto[0]	19	1		T31	1		T73	1		T71	1
all_values[9]	auto[0]	auto[1]	auto[1]	42	1		T6	1		T32	2		T29	2
all_values[9]	auto[1]	auto[0]	auto[1]	42	1		T6	2		T32	1		T29	2
all_values[9]	auto[1]	auto[1]	auto[1]	30	1		T6	1		T32	1		T29	1
all_values[10]	auto[0]	auto[0]	auto[0]	31	1		T29	2		T30	2		T31	1
all_values[10]	auto[0]	auto[0]	auto[1]	36	1		T6	1		T32	1		T33	1
all_values[10]	auto[0]	auto[1]	auto[0]	16	1		T30	2		T33	1		T73	2
all_values[10]	auto[0]	auto[1]	auto[1]	37	1		T6	2		T29	4		T31	2
all_values[10]	auto[1]	auto[0]	auto[1]	47	1		T6	4		T32	1		T31	1
all_values[10]	auto[1]	auto[1]	auto[1]	32	1		T32	2		T29	1		T33	1
all_values[11]	auto[0]	auto[0]	auto[0]	15	1		T6	1		T29	1		T72	1
all_values[11]	auto[0]	auto[0]	auto[1]	46	1		T6	1		T32	2		T30	1
all_values[11]	auto[0]	auto[1]	auto[0]	7	1		T74	1		T75	2		T79	1
all_values[11]	auto[0]	auto[1]	auto[1]	48	1		T6	2		T32	1		T29	3
all_values[11]	auto[1]	auto[0]	auto[1]	47	1		T6	3		T32	1		T29	1
all_values[11]	auto[1]	auto[1]	auto[1]	36	1		T29	2		T33	3		T73	1
all_values[12]	auto[0]	auto[0]	auto[0]	24	1		T6	2		T32	1		T30	1
all_values[12]	auto[0]	auto[0]	auto[1]	48	1		T29	2		T30	1		T33	3
all_values[12]	auto[0]	auto[1]	auto[0]	7	1		T30	1		T72	1		T77	1
all_values[12]	auto[0]	auto[1]	auto[1]	40	1		T6	3		T32	1		T31	2
all_values[12]	auto[1]	auto[0]	auto[1]	47	1		T6	2		T29	2		T30	1
all_values[12]	auto[1]	auto[1]	auto[1]	33	1		T32	2		T29	3		T31	1
all_values[13]	auto[0]	auto[0]	auto[0]	17	1		T31	1		T70	1		T62	2
all_values[13]	auto[0]	auto[0]	auto[1]	39	1		T6	2		T32	2		T30	1
all_values[13]	auto[0]	auto[1]	auto[0]	12	1		T32	1		T29	2		T33	2
all_values[13]	auto[0]	auto[1]	auto[1]	46	1		T6	2		T29	4		T30	2
all_values[13]	auto[1]	auto[0]	auto[1]	41	1		T6	2		T30	1		T31	1
all_values[13]	auto[1]	auto[1]	auto[1]	44	1		T6	1		T32	1		T29	1
all_values[14]	auto[0]	auto[0]	auto[0]	29	1		T32	1		T31	1		T33	1
all_values[14]	auto[0]	auto[0]	auto[1]	38	1		T6	1		T29	2		T33	2
all_values[14]	auto[0]	auto[1]	auto[0]	24	1		T32	3		T29	1		T31	1
all_values[14]	auto[0]	auto[1]	auto[1]	34	1		T6	2		T29	1		T30	2
all_values[14]	auto[1]	auto[0]	auto[1]	38	1		T6	3		T29	1		T30	1
all_values[14]	auto[1]	auto[1]	auto[1]	36	1		T6	1		T29	2		T30	1
all_values[15]	auto[0]	auto[0]	auto[0]	13	1		T6	3		T71	1		T76	1
all_values[15]	auto[0]	auto[0]	auto[1]	61	1		T6	1		T32	1		T29	5
all_values[15]	auto[0]	auto[1]	auto[0]	12	1		T6	2		T76	1		T80	1
all_values[15]	auto[0]	auto[1]	auto[1]	32	1		T30	2		T73	2		T70	3
all_values[15]	auto[1]	auto[0]	auto[1]	57	1		T6	1		T32	2		T29	2
all_values[15]	auto[1]	auto[1]	auto[1]	24	1		T32	1		T30	1		T33	1
all_values[16]	auto[0]	auto[0]	auto[0]	28	1		T6	1		T32	1		T70	3
all_values[16]	auto[0]	auto[0]	auto[1]	51	1		T6	2		T29	2		T30	2
all_values[16]	auto[0]	auto[1]	auto[0]	17	1		T32	3		T72	2		T62	1
all_values[16]	auto[0]	auto[1]	auto[1]	31	1		T6	1		T29	2		T31	2
all_values[16]	auto[1]	auto[0]	auto[1]	39	1		T6	2		T29	2		T30	1
all_values[16]	auto[1]	auto[1]	auto[1]	33	1		T6	1		T29	1		T30	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal