Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	37201	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	47507	1		T1	3		T2	2		T3	1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	50540	1		T1	2		T2	2		T3	2
values[0x0]	16749	1		T1	1		T4	145		T5	492
values[0x1]	17419	1		T2	1		T3	1		T4	149

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	25653	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	59055	1		T1	3		T2	2		T3	1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	334	1		T4	3		T6	1		T9	4
valid_sources[0x01]	286	1		T6	6		T9	4		T10	2
valid_sources[0x02]	341	1		T4	1		T6	4		T8	1
valid_sources[0x03]	181	1		T4	4		T6	4		T9	1
valid_sources[0x04]	301	1		T6	3		T8	1		T12	1
valid_sources[0x05]	345	1		T6	8		T27	14		T21	3
valid_sources[0x06]	237	1		T4	3		T6	1		T9	8
valid_sources[0x07]	248	1		T4	1		T6	6		T9	1
valid_sources[0x08]	263	1		T4	3		T6	2		T21	7
valid_sources[0x09]	232	1		T4	1		T6	2		T21	1
valid_sources[0x0a]	241	1		T4	4		T6	1		T9	3
valid_sources[0x0b]	235	1		T4	5		T6	5		T8	1
valid_sources[0x0c]	215	1		T6	4		T9	2		T11	1
valid_sources[0x0d]	586	1		T4	4		T6	5		T21	9
valid_sources[0x0e]	272	1		T6	3		T9	7		T22	5
valid_sources[0x0f]	479	1		T4	2		T6	7		T20	1
valid_sources[0x10]	367	1		T4	4		T6	3		T20	2
valid_sources[0x11]	169	1		T4	2		T6	5		T8	1
valid_sources[0x12]	208	1		T4	1		T6	4		T8	1
valid_sources[0x13]	218	1		T6	2		T21	9		T22	4
valid_sources[0x14]	446	1		T4	1		T6	3		T19	78
valid_sources[0x15]	240	1		T4	3		T9	1		T21	2
valid_sources[0x16]	265	1		T4	1		T6	7		T7	1
valid_sources[0x17]	293	1		T4	4		T6	4		T9	5
valid_sources[0x18]	278	1		T6	2		T20	6		T21	4
valid_sources[0x19]	387	1		T6	5		T9	6		T20	5
valid_sources[0x1a]	255	1		T6	4		T8	1		T9	7
valid_sources[0x1b]	271	1		T4	1		T6	7		T9	5
valid_sources[0x1c]	261	1		T6	5		T9	1		T10	7
valid_sources[0x1d]	426	1		T4	2		T6	6		T9	1
valid_sources[0x1e]	197	1		T4	1		T6	5		T10	1
valid_sources[0x1f]	482	1		T6	4		T9	1		T10	16
valid_sources[0x20]	259	1		T4	3		T6	4		T11	1
valid_sources[0x21]	229	1		T4	7		T6	6		T7	1
valid_sources[0x22]	361	1		T4	3		T6	3		T9	2
valid_sources[0x23]	218	1		T6	6		T9	1		T21	6
valid_sources[0x24]	233	1		T6	5		T9	1		T20	1
valid_sources[0x25]	159	1		T6	6		T8	1		T9	2
valid_sources[0x26]	275	1		T4	2		T6	1		T9	1
valid_sources[0x27]	570	1		T4	2		T6	3		T9	1
valid_sources[0x28]	283	1		T4	3		T6	1		T9	2
valid_sources[0x29]	211	1		T4	1		T6	3		T10	2
valid_sources[0x2a]	195	1		T4	1		T6	5		T9	1
valid_sources[0x2b]	456	1		T6	5		T9	1		T10	6
valid_sources[0x2c]	219	1		T4	1		T6	3		T9	7
valid_sources[0x2d]	302	1		T6	8		T9	2		T21	5
valid_sources[0x2e]	504	1		T4	1		T6	4		T20	1
valid_sources[0x2f]	422	1		T6	7		T8	1		T21	6
valid_sources[0x30]	167	1		T4	3		T9	1		T10	9
valid_sources[0x31]	332	1		T6	6		T9	2		T19	53
valid_sources[0x32]	238	1		T4	2		T6	3		T9	2
valid_sources[0x33]	400	1		T4	3		T6	4		T9	5
valid_sources[0x34]	233	1		T4	4		T6	4		T9	1
valid_sources[0x35]	323	1		T4	6		T6	2		T9	2
valid_sources[0x36]	258	1		T6	3		T20	5		T21	4
valid_sources[0x37]	135	1		T6	2		T9	3		T21	1
valid_sources[0x38]	208	1		T4	4		T6	7		T9	2
valid_sources[0x39]	211	1		T4	2		T6	4		T9	2
valid_sources[0x3a]	522	1		T4	1		T6	8		T9	3
valid_sources[0x3b]	206	1		T4	2		T6	4		T9	1
valid_sources[0x3c]	183	1		T6	3		T20	7		T11	1
valid_sources[0x3d]	410	1		T4	1		T6	5		T9	1
valid_sources[0x3e]	1790	1		T4	3		T5	1538		T6	6
valid_sources[0x3f]	373	1		T4	1		T6	7		T9	2
valid_sources[0x40]	367	1		T4	1		T8	1		T9	3
valid_sources[0x41]	240	1		T6	2		T9	2		T10	4
valid_sources[0x42]	359	1		T6	6		T7	2		T9	2
valid_sources[0x43]	289	1		T4	2		T6	5		T20	1
valid_sources[0x44]	290	1		T4	5		T6	6		T10	6
valid_sources[0x45]	219	1		T4	2		T6	4		T9	1
valid_sources[0x46]	337	1		T4	3		T6	3		T21	4
valid_sources[0x47]	207	1		T4	4		T6	10		T9	7
valid_sources[0x48]	220	1		T4	1		T6	3		T21	7
valid_sources[0x49]	210	1		T4	2		T6	2		T9	3
valid_sources[0x4a]	215	1		T6	7		T9	1		T21	3
valid_sources[0x4b]	341	1		T4	2		T6	9		T20	1
valid_sources[0x4c]	251	1		T6	1		T9	4		T22	1
valid_sources[0x4d]	609	1		T4	6		T6	9		T10	13
valid_sources[0x4e]	354	1		T3	1		T4	5		T6	3
valid_sources[0x4f]	273	1		T6	9		T9	3		T11	1
valid_sources[0x50]	199	1		T6	3		T9	2		T21	2
valid_sources[0x51]	179	1		T4	3		T6	2		T9	4
valid_sources[0x52]	345	1		T4	5		T6	1		T9	2
valid_sources[0x53]	142	1		T3	1		T4	2		T6	3
valid_sources[0x54]	331	1		T4	2		T6	8		T10	2
valid_sources[0x55]	237	1		T4	2		T6	6		T9	4
valid_sources[0x56]	243	1		T4	5		T6	3		T21	2
valid_sources[0x57]	346	1		T4	2		T6	4		T9	2
valid_sources[0x58]	275	1		T4	2		T6	7		T22	15
valid_sources[0x59]	213	1		T6	4		T7	3		T20	10
valid_sources[0x5a]	326	1		T4	3		T6	7		T9	4
valid_sources[0x5b]	290	1		T6	3		T9	2		T10	24
valid_sources[0x5c]	251	1		T4	2		T6	3		T11	2
valid_sources[0x5d]	322	1		T4	3		T6	3		T22	8
valid_sources[0x5e]	312	1		T4	3		T6	6		T9	2
valid_sources[0x5f]	528	1		T6	4		T9	2		T21	1
valid_sources[0x60]	298	1		T4	9		T6	3		T9	1
valid_sources[0x61]	258	1		T4	1		T6	6		T9	3
valid_sources[0x62]	352	1		T4	3		T6	3		T20	1
valid_sources[0x63]	228	1		T6	4		T20	1		T27	8
valid_sources[0x64]	300	1		T6	4		T8	1		T9	1
valid_sources[0x65]	313	1		T4	1		T6	3		T10	2
valid_sources[0x66]	301	1		T6	3		T20	1		T11	1
valid_sources[0x67]	458	1		T6	3		T9	1		T20	1
valid_sources[0x68]	302	1		T6	5		T8	1		T9	1
valid_sources[0x69]	289	1		T4	4		T6	3		T9	2
valid_sources[0x6a]	219	1		T4	2		T6	4		T8	1
valid_sources[0x6b]	401	1		T6	7		T20	3		T21	6
valid_sources[0x6c]	185	1		T4	1		T6	5		T10	2
valid_sources[0x6d]	371	1		T3	1		T4	1		T6	5
valid_sources[0x6e]	393	1		T4	5		T6	6		T9	6
valid_sources[0x6f]	227	1		T4	2		T6	2		T9	1
valid_sources[0x70]	538	1		T4	1		T6	6		T9	2
valid_sources[0x71]	314	1		T4	7		T6	4		T8	1
valid_sources[0x72]	199	1		T4	1		T6	4		T8	1
valid_sources[0x73]	268	1		T4	1		T6	9		T9	1
valid_sources[0x74]	355	1		T6	2		T9	3		T11	1
valid_sources[0x75]	303	1		T6	5		T9	1		T20	1
valid_sources[0x76]	234	1		T6	1		T10	21		T20	1
valid_sources[0x77]	233	1		T4	2		T6	6		T20	2
valid_sources[0x78]	194	1		T4	2		T6	3		T20	5
valid_sources[0x79]	260	1		T4	6		T6	6		T10	43
valid_sources[0x7a]	513	1		T6	3		T10	3		T21	5
valid_sources[0x7b]	389	1		T4	3		T6	12		T9	3
valid_sources[0x7c]	265	1		T4	2		T6	5		T9	2
valid_sources[0x7d]	644	1		T6	5		T9	1		T21	3
valid_sources[0x7e]	332	1		T4	4		T6	2		T9	2
valid_sources[0x7f]	181	1		T6	4		T9	1		T21	1
valid_sources[0x80]	390	1		T6	3		T9	3		T21	14

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

18050

1

T1

2

T2

1

T4

47

values[0x0]

all_enables

biggest_size

15269

1

T1

1

T4

143

T5

492

values[0x1]

all_enables

biggest_size

14188

1

T2

1

T3

1

T4

141