SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[usbdev_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 77912 | 1 | T1 | 3 | T2 | 3 | T3 | 3 | |||
auto[1] | 20964 | 1 | T4 | 339 | T5 | 1535 | T9 | 380 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 98758 | 1 | T1 | 3 | T2 | 3 | T3 | 3 | |||
values[1] | 14 | 1 | T42 | 1 | T56 | 1 | T71 | 3 | |||
values[2] | 2 | 1 | T26 | 1 | T54 | 1 | - | - | |||
values[3] | 58 | 1 | T26 | 2 | T42 | 2 | T56 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 98755 | 1 | T1 | 3 | T2 | 3 | T3 | 3 | |||
values[1] | 11 | 1 | T56 | 1 | T54 | 1 | T58 | 1 | |||
values[2] | 8 | 1 | T26 | 1 | T42 | 1 | T56 | 2 | |||
values[3] | 57 | 1 | T26 | 4 | T42 | 6 | T56 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 98696 | 1 | T1 | 3 | T2 | 3 | T3 | 3 | |||
auto[TlIntgErrCmd] | 59 | 1 | T26 | 2 | T42 | 3 | T56 | 2 | |||
auto[TlIntgErrData] | 62 | 1 | T26 | 6 | T42 | 4 | T56 | 3 | |||
auto[TlIntgErrBoth] | 59 | 1 | T26 | 2 | T42 | 3 | T56 | 5 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |