Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	50406	1		T2	1		T3	2		T4	170
full_word	48470	1		T1	3		T2	2		T3	1

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	98696	1		T1	3		T2	3		T3	3
auto[TlIntgErrCmd]	59	1		T26	2		T42	3		T56	2
auto[TlIntgErrData]	62	1		T26	6		T42	4		T56	3
auto[TlIntgErrBoth]	59	1		T26	2		T42	3		T56	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	52332	1		T1	2		T2	2		T3	2
auto[1]	46544	1		T1	1		T2	1		T3	1

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	34043	1		T2	1		T3	2		T4	160
auto[TlIntgErrNone]	partial	auto[1]	16202	1		T4	10		T6	9		T7	2
auto[TlIntgErrNone]	full_word	auto[0]	18211	1		T1	2		T2	1		T4	47
auto[TlIntgErrNone]	full_word	auto[1]	30240	1		T1	1		T2	1		T3	1
auto[TlIntgErrCmd]	partial	auto[0]	20	1		T26	1		T42	2		T54	2
auto[TlIntgErrCmd]	partial	auto[1]	35	1		T26	1		T42	1		T56	2
auto[TlIntgErrCmd]	full_word	auto[0]	1	1		T72	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1		T58	1		T73	1		T74	1
auto[TlIntgErrData]	partial	auto[0]	25	1		T26	4		T42	4		T54	2
auto[TlIntgErrData]	partial	auto[1]	24	1		T26	2		T56	3		T54	4
auto[TlIntgErrData]	full_word	auto[0]	5	1		T54	1		T58	1		T75	1
auto[TlIntgErrData]	full_word	auto[1]	8	1		T54	1		T71	1		T75	2
auto[TlIntgErrBoth]	partial	auto[0]	26	1		T26	1		T42	1		T56	3
auto[TlIntgErrBoth]	partial	auto[1]	31	1		T26	1		T42	2		T56	2
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T72	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	1	1		T76	1		-	-		-	-