Unified Coverage Report :: Module :: prim_fifo_sync_cnt

Module : prim_fifo_sync_cnt

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
63.89	77.78				50.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_avfifo.gen_normal_fifo.u_fifo_cnt	63.89	77.78				50.00
tb.dut.usbdev_rxfifo.gen_normal_fifo.u_fifo_cnt	63.89	77.78				50.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo.gen_normal_fifo.u_fifo_cnt	63.89	77.78				50.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt	63.89	77.78				50.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo.gen_normal_fifo.u_fifo_cnt	63.89	77.78				50.00

---

Module Instance : tb.dut.usbdev_avfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
63.89	77.78				50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
63.89	77.78				50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
62.63	86.36	41.67			62.50	60.00	usbdev_avfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.usbdev_rxfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
63.89	77.78				50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
63.89	77.78				50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
63.30	90.91	42.31			60.00	60.00	usbdev_rxfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
63.89	77.78				50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
63.89	77.78				50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
62.17	86.36	42.31			60.00	60.00	u_reqfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
63.89	77.78				50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
63.89	77.78				50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
62.17	86.36	42.31			60.00	60.00	u_sramreqfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
63.89	77.78				50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
63.89	77.78				50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
62.60	90.91	41.18			58.33	60.00	u_rspfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=8,Width=4,Secure=0 )
Line Coverage for Module self-instances :

SCORE	LINE
63.89	77.78

tb.dut.usbdev_avfifo.gen_normal_fifo.u_fifo_cnt

SCORE	LINE
63.89	77.78

tb.dut.usbdev_rxfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	14	77.78
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	7	5	71.43
ALWAYS	86	7	5	71.43

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77		unreachable
78	1	1
79	0	1
80	1	1
81	0	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89		unreachable
90	1	1
91	0	1
92	1	1
93	0	1
			MISSING_ELSE

---

Line Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=1,Width=2,Secure=0 )
Line Coverage for Module self-instances :

SCORE	LINE
63.89	77.78

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo.gen_normal_fifo.u_fifo_cnt

SCORE	LINE
63.89	77.78

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

SCORE	LINE
63.89	77.78

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	14	77.78
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	7	5	71.43
ALWAYS	86	7	5	71.43

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77		unreachable
78	1	1
79	0	1
80	1	1
81	0	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89		unreachable
90	1	1
91	0	1
92	1	1
93	0	1
			MISSING_ELSE

---

Branch Coverage for Module : prim_fifo_sync_cnt

	Line No.	Total	Covered	Percent
Branches		8	4	50.00
IF	74	4	2	50.00
IF	86	4	2	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Not Covered
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Not Covered
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.usbdev_avfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	14	77.78
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	7	5	71.43
ALWAYS	86	7	5	71.43

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77		unreachable
78	1	1
79	0	1
80	1	1
81	0	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89		unreachable
90	1	1
91	0	1
92	1	1
93	0	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.usbdev_avfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	4	50.00
IF	74	4	2	50.00
IF	86	4	2	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Not Covered
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Not Covered
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.usbdev_rxfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	14	77.78
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	7	5	71.43
ALWAYS	86	7	5	71.43

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77		unreachable
78	1	1
79	0	1
80	1	1
81	0	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89		unreachable
90	1	1
91	0	1
92	1	1
93	0	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.usbdev_rxfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	4	50.00
IF	74	4	2	50.00
IF	86	4	2	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Not Covered
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Not Covered
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	14	77.78
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	7	5	71.43
ALWAYS	86	7	5	71.43

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77		unreachable
78	1	1
79	0	1
80	1	1
81	0	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89		unreachable
90	1	1
91	0	1
92	1	1
93	0	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	4	50.00
IF	74	4	2	50.00
IF	86	4	2	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Not Covered
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Not Covered
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	14	77.78
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	7	5	71.43
ALWAYS	86	7	5	71.43

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77		unreachable
78	1	1
79	0	1
80	1	1
81	0	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89		unreachable
90	1	1
91	0	1
92	1	1
93	0	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	4	50.00
IF	74	4	2	50.00
IF	86	4	2	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Not Covered
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Not Covered
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	14	77.78
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	7	5	71.43
ALWAYS	86	7	5	71.43

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77		unreachable
78	1	1
79	0	1
80	1	1
81	0	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89		unreachable
90	1	1
91	0	1
92	1	1
93	0	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	4	50.00
IF	74	4	2	50.00
IF	86	4	2	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Not Covered
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Not Covered
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3