Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
72.77	83.19	35.82	89.69		55.17	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	776613	11689	0	0
ep_in_enable_rd_A	776613	1237	0	0
ep_out_enable_rd_A	776613	1372	0	0
in_iso_rd_A	776613	1162	0	0
intr_enable_rd_A	776613	1996	0	0
out_iso_rd_A	776613	1488	0	0
phy_config_rd_A	776613	858	0	0
phy_pins_drive_rd_A	776613	1044	0	0
rxenable_setup_rd_A	776613	1272	0	0
set_nak_out_rd_A	776613	1597	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	776613	11689	0	0
T4	4716	5	0	0
T9	14542	1056	0	0
T10	4876	549	0	0
T11	1742	4	0	0
T12	14505	743	0	0
T13	1994	1	0	0
T14	12189	0	0	0
T15	0	1	0	0
T16	0	330	0	0
T17	1194	0	0	0
T18	2660	0	0	0
T26	0	1	0	0
T32	0	806	0	0
T43	1674	0	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	776613	1237	0	0
T6	9974	151	0	0
T11	1742	2	0	0
T13	1994	6	0	0
T14	12189	0	0	0
T15	0	8	0	0
T17	1194	0	0	0
T18	2660	0	0	0
T21	8093	12	0	0
T22	7000	26	0	0
T30	3705	103	0	0
T40	0	3	0	0
T43	1674	0	0	0
T46	0	60	0	0
T57	0	14	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	776613	1372	0	0
T6	9974	128	0	0
T11	1742	4	0	0
T13	1994	1	0	0
T14	12189	0	0	0
T17	1194	0	0	0
T18	2660	0	0	0
T21	8093	40	0	0
T22	7000	22	0	0
T30	3705	59	0	0
T34	0	6	0	0
T43	1674	0	0	0
T46	0	91	0	0
T56	0	218	0	0
T57	0	4	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	776613	1162	0	0
T6	9974	116	0	0
T13	1994	5	0	0
T14	12189	0	0	0
T15	2004	0	0	0
T17	1194	0	0	0
T18	2660	0	0	0
T21	8093	40	0	0
T22	7000	20	0	0
T30	3705	76	0	0
T43	1674	0	0	0
T46	0	49	0	0
T47	0	2	0	0
T56	0	230	0	0
T57	0	7	0	0
T58	0	86	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	776613	1996	0	0
T6	9974	144	0	0
T7	1256	13	0	0
T13	1994	8	0	0
T14	12189	0	0	0
T15	0	3	0	0
T17	1194	0	0	0
T18	2660	0	0	0
T21	8093	59	0	0
T22	7000	29	0	0
T30	3705	89	0	0
T37	0	16	0	0
T40	0	8	0	0
T43	1674	0	0	0
T57	0	1	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	776613	1488	0	0
T6	9974	137	0	0
T11	1742	7	0	0
T15	2004	8	0	0
T16	7187	0	0	0
T21	8093	9	0	0
T22	7000	14	0	0
T26	13897	0	0	0
T30	3705	56	0	0
T37	1282	0	0	0
T38	1950	0	0	0
T40	0	6	0	0
T46	0	57	0	0
T56	0	277	0	0
T57	0	4	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	776613	858	0	0
T6	9974	132	0	0
T11	1742	10	0	0
T13	1994	4	0	0
T14	12189	0	0	0
T15	0	9	0	0
T17	1194	0	0	0
T18	2660	0	0	0
T21	8093	24	0	0
T22	7000	42	0	0
T30	3705	24	0	0
T43	1674	0	0	0
T46	0	46	0	0
T56	0	132	0	0
T57	0	8	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	776613	1044	0	0
T6	9974	132	0	0
T11	1742	6	0	0
T15	2004	3	0	0
T16	7187	0	0	0
T21	8093	48	0	0
T22	7000	13	0	0
T26	13897	0	0	0
T30	3705	45	0	0
T37	1282	0	0	0
T38	1950	0	0	0
T46	0	8	0	0
T47	0	5	0	0
T56	0	164	0	0
T57	0	4	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	776613	1272	0	0
T6	9974	152	0	0
T13	1994	7	0	0
T14	12189	0	0	0
T15	2004	0	0	0
T17	1194	0	0	0
T18	2660	0	0	0
T21	8093	16	0	0
T22	7000	40	0	0
T30	3705	115	0	0
T40	0	6	0	0
T43	1674	0	0	0
T46	0	49	0	0
T56	0	161	0	0
T57	0	7	0	0
T59	0	15	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	776613	1597	0	0
T6	9974	131	0	0
T13	1994	6	0	0
T14	12189	0	0	0
T15	2004	1	0	0
T17	1194	0	0	0
T18	2660	0	0	0
T21	8093	48	0	0
T22	7000	25	0	0
T30	3705	120	0	0
T34	0	16	0	0
T40	0	4	0	0
T43	1674	0	0	0
T46	0	2	0	0
T57	0	5	0	0