Toggle Coverage for Module :
prim_secded_inv_64_57_dec
| Total | Covered | Percent |
Totals |
4 |
4 |
100.00 |
Total Bits |
232 |
232 |
100.00 |
Total Bits 0->1 |
116 |
116 |
100.00 |
Total Bits 1->0 |
116 |
116 |
100.00 |
| | | |
Ports |
4 |
4 |
100.00 |
Port Bits |
232 |
232 |
100.00 |
Port Bits 0->1 |
116 |
116 |
100.00 |
Port Bits 1->0 |
116 |
116 |
100.00 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[42:0] |
Yes |
Yes |
*T2,*T3,*T4 |
Yes |
T3,T4,T5 |
INPUT |
data_i[56:43] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
data_i[63:57] |
Yes |
Yes |
T1,T2,T4 |
Yes |
T1,T3,T4 |
INPUT |
data_o[56:0] |
Yes |
Yes |
T2,T3,T4 |
Yes |
T3,T4,T5 |
OUTPUT |
syndrome_o[6:0] |
Yes |
Yes |
T8,T9,T11 |
Yes |
T8,T9,T11 |
OUTPUT |
err_o[1:0] |
Yes |
Yes |
T8,T9,T11 |
Yes |
T8,T9,T11 |
OUTPUT |
*Tests covering at least one bit in the range