Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=16}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=16}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=16}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	68	0	68	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=16}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	17	0	17	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=16}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	68	0	68	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	288	1		T4	5		T6	2		T8	5
all_values[1]	288	1		T4	5		T6	2		T8	5
all_values[2]	288	1		T4	5		T6	2		T8	5
all_values[3]	288	1		T4	5		T6	2		T8	5
all_values[4]	288	1		T4	5		T6	2		T8	5
all_values[5]	288	1		T4	5		T6	2		T8	5
all_values[6]	288	1		T4	5		T6	2		T8	5
all_values[7]	288	1		T4	5		T6	2		T8	5
all_values[8]	288	1		T4	5		T6	2		T8	5
all_values[9]	288	1		T4	5		T6	2		T8	5
all_values[10]	288	1		T4	5		T6	2		T8	5
all_values[11]	288	1		T4	5		T6	2		T8	5
all_values[12]	288	1		T4	5		T6	2		T8	5
all_values[13]	288	1		T4	5		T6	2		T8	5
all_values[14]	288	1		T4	5		T6	2		T8	5
all_values[15]	288	1		T4	5		T6	2		T8	5
all_values[16]	288	1		T4	5		T6	2		T8	5

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2752	1		T4	37		T6	34		T8	37
auto[1]	2144	1		T4	48		T8	48		T9	48

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1304	1		T4	11		T6	34		T8	14
auto[1]	3592	1		T4	74		T8	71		T9	71

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	68	0	68	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	59	1		T6	2		T9	1		T28	1
all_values[0]	auto[0]	auto[1]	97	1		T4	1		T29	2		T47	6
all_values[0]	auto[1]	auto[0]	11	1		T8	2		T28	2		T64	2
all_values[0]	auto[1]	auto[1]	121	1		T4	4		T8	3		T9	4
all_values[1]	auto[0]	auto[0]	57	1		T4	4		T6	2		T19	1
all_values[1]	auto[0]	auto[1]	103	1		T28	6		T29	2		T47	5
all_values[1]	auto[1]	auto[0]	28	1		T4	1		T9	1		T29	2
all_values[1]	auto[1]	auto[1]	100	1		T8	5		T9	4		T28	2
all_values[2]	auto[0]	auto[0]	59	1		T4	1		T6	2		T9	2
all_values[2]	auto[0]	auto[1]	108	1		T8	3		T28	5		T19	2
all_values[2]	auto[1]	auto[0]	20	1		T4	1		T28	1		T29	3
all_values[2]	auto[1]	auto[1]	101	1		T4	3		T8	2		T9	3
all_values[3]	auto[0]	auto[0]	53	1		T6	2		T8	1		T28	1
all_values[3]	auto[0]	auto[1]	123	1		T4	1		T8	3		T9	4
all_values[3]	auto[1]	auto[0]	19	1		T28	1		T41	1		T65	1
all_values[3]	auto[1]	auto[1]	93	1		T4	4		T8	1		T9	1
all_values[4]	auto[0]	auto[0]	68	1		T6	2		T8	1		T28	2
all_values[4]	auto[0]	auto[1]	93	1		T4	5		T29	1		T48	2
all_values[4]	auto[1]	auto[0]	24	1		T8	1		T28	3		T29	1
all_values[4]	auto[1]	auto[1]	103	1		T8	3		T9	5		T28	3
all_values[5]	auto[0]	auto[0]	53	1		T6	2		T28	1		T19	1
all_values[5]	auto[0]	auto[1]	90	1		T4	3		T8	1		T9	1
all_values[5]	auto[1]	auto[0]	13	1		T19	4		T48	1		T41	1
all_values[5]	auto[1]	auto[1]	132	1		T4	2		T8	4		T9	4
all_values[6]	auto[0]	auto[0]	59	1		T4	1		T6	2		T47	1
all_values[6]	auto[0]	auto[1]	101	1		T8	1		T9	1		T28	3
all_values[6]	auto[1]	auto[0]	23	1		T4	1		T28	4		T29	3
all_values[6]	auto[1]	auto[1]	105	1		T4	3		T8	4		T9	4
all_values[7]	auto[0]	auto[0]	54	1		T6	2		T9	1		T16	2
all_values[7]	auto[0]	auto[1]	113	1		T4	1		T8	5		T9	3
all_values[7]	auto[1]	auto[0]	21	1		T28	1		T48	1		T40	2
all_values[7]	auto[1]	auto[1]	100	1		T4	4		T9	1		T28	5
all_values[8]	auto[0]	auto[0]	59	1		T6	2		T8	1		T28	1
all_values[8]	auto[0]	auto[1]	110	1		T4	4		T8	1		T9	5
all_values[8]	auto[1]	auto[0]	31	1		T28	3		T19	1		T40	1
all_values[8]	auto[1]	auto[1]	88	1		T4	1		T8	3		T28	1
all_values[9]	auto[0]	auto[0]	58	1		T6	2		T48	1		T16	2
all_values[9]	auto[0]	auto[1]	111	1		T4	2		T8	1		T9	2
all_values[9]	auto[1]	auto[0]	19	1		T8	1		T29	1		T48	4
all_values[9]	auto[1]	auto[1]	100	1		T4	3		T8	3		T9	3
all_values[10]	auto[0]	auto[0]	58	1		T6	2		T16	2		T17	2
all_values[10]	auto[0]	auto[1]	95	1		T4	3		T9	1		T28	2
all_values[10]	auto[1]	auto[0]	14	1		T28	1		T29	2		T66	1
all_values[10]	auto[1]	auto[1]	121	1		T4	2		T8	5		T9	4
all_values[11]	auto[0]	auto[0]	54	1		T6	2		T8	1		T9	2
all_values[11]	auto[0]	auto[1]	92	1		T4	1		T8	4		T28	1
all_values[11]	auto[1]	auto[0]	22	1		T47	2		T40	1		T42	1
all_values[11]	auto[1]	auto[1]	120	1		T4	4		T9	3		T28	7
all_values[12]	auto[0]	auto[0]	57	1		T6	2		T8	1		T28	1
all_values[12]	auto[0]	auto[1]	95	1		T4	1		T8	3		T9	5
all_values[12]	auto[1]	auto[0]	18	1		T28	2		T65	1		T67	1
all_values[12]	auto[1]	auto[1]	118	1		T4	4		T8	1		T28	4
all_values[13]	auto[0]	auto[0]	62	1		T4	1		T6	2		T29	2
all_values[13]	auto[0]	auto[1]	104	1		T4	3		T8	3		T9	1
all_values[13]	auto[1]	auto[0]	16	1		T9	1		T28	1		T29	3
all_values[13]	auto[1]	auto[1]	106	1		T4	1		T8	2		T9	3
all_values[14]	auto[0]	auto[0]	65	1		T6	2		T8	5		T9	2
all_values[14]	auto[0]	auto[1]	108	1		T4	1		T28	1		T29	7
all_values[14]	auto[1]	auto[0]	14	1		T9	3		T28	2		T48	1
all_values[14]	auto[1]	auto[1]	101	1		T4	4		T28	4		T29	1
all_values[15]	auto[0]	auto[0]	48	1		T6	2		T29	2		T16	2
all_values[15]	auto[0]	auto[1]	122	1		T8	1		T9	2		T28	5
all_values[15]	auto[1]	auto[0]	11	1		T29	1		T19	1		T47	1
all_values[15]	auto[1]	auto[1]	107	1		T4	5		T8	4		T9	3
all_values[16]	auto[0]	auto[0]	60	1		T4	1		T6	2		T19	1
all_values[16]	auto[0]	auto[1]	104	1		T4	3		T8	1		T9	4
all_values[16]	auto[1]	auto[0]	17	1		T9	1		T28	1		T19	1
all_values[16]	auto[1]	auto[1]	107	1		T4	1		T8	4		T28	6