---

Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.gen_no_stubbed_memory.u_memory_2p.i_prim_ram_2p_async_adv.u_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheckPortA_A	0	0	17813	0	0	0
tb.dut.gen_no_stubbed_memory.u_memory_2p.i_prim_ram_2p_async_adv.u_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheckPortB_A	0	0	17813	0	0	0
tb.dut.gen_no_stubbed_memory.u_memory_2p.i_prim_ram_2p_async_adv.u_mem.gen_generic.u_impl_generic.gen_wmask[1].MaskCheckPortA_A	0	0	17813	0	0	0
tb.dut.gen_no_stubbed_memory.u_memory_2p.i_prim_ram_2p_async_adv.u_mem.gen_generic.u_impl_generic.gen_wmask[1].MaskCheckPortB_A	0	0	17813	0	0	0
tb.dut.gen_no_stubbed_memory.u_memory_2p.i_prim_ram_2p_async_adv.u_mem.gen_generic.u_impl_generic.gen_wmask[2].MaskCheckPortA_A	0	0	17813	0	0	0
tb.dut.gen_no_stubbed_memory.u_memory_2p.i_prim_ram_2p_async_adv.u_mem.gen_generic.u_impl_generic.gen_wmask[2].MaskCheckPortB_A	0	0	17813	0	0	0
tb.dut.gen_no_stubbed_memory.u_memory_2p.i_prim_ram_2p_async_adv.u_mem.gen_generic.u_impl_generic.gen_wmask[3].MaskCheckPortA_A	0	0	17813	0	0	0
tb.dut.gen_no_stubbed_memory.u_memory_2p.i_prim_ram_2p_async_adv.u_mem.gen_generic.u_impl_generic.gen_wmask[3].MaskCheckPortB_A	0	0	17813	0	0	0
tb.dut.gen_no_stubbed_memory.u_tlul2sram.TlOutPayloadKnown_A	0	0	17813	0	0	0
tb.dut.gen_no_stubbed_memory.u_tlul2sram.rvalidHighReqFifoEmpty	0	0	17813	0	0	0
tb.dut.gen_no_stubbed_memory.u_tlul2sram.rvalidHighWhenRspFifoFull	0	0	17813	0	0	0
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo.DataKnown_A	0	0	17813	0	0	0
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	17813	0	0	0
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo.DataKnown_A	0	0	17813	0	0	0
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	17813	0	0	0
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo.DataKnown_A	0	0	17813	0	0	0
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	17813	0	0	0
tb.dut.i_usbdev_iomux.i_mux_tx_d.gen_generic.u_impl_generic.selKnown0	0	0	3	0	0	0
tb.dut.i_usbdev_iomux.i_mux_tx_d.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.i_usbdev_iomux.i_mux_tx_dn.gen_generic.u_impl_generic.selKnown0	0	0	0	0	0	0
tb.dut.i_usbdev_iomux.i_mux_tx_dn.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.i_usbdev_iomux.i_mux_tx_dp.gen_generic.u_impl_generic.selKnown0	0	0	3	0	0	0
tb.dut.i_usbdev_iomux.i_mux_tx_dp.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.i_usbdev_iomux.i_mux_tx_oe.gen_generic.u_impl_generic.selKnown0	0	0	0	0	0	0
tb.dut.i_usbdev_iomux.i_mux_tx_oe.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.i_usbdev_iomux.i_mux_tx_se0.gen_generic.u_impl_generic.selKnown0	0	0	0	0	0	0
tb.dut.i_usbdev_iomux.i_mux_tx_se0.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_reg.u_wake_events_cdc.BusySrcReqChk_A	0	0	759040	0	0	0
tb.dut.u_reg.u_wake_events_cdc.SrcAckBusyChk_A	0	0	759040	0	0	0
tb.dut.u_reg.u_wake_events_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	199608	0	0	152
tb.dut.u_reg.u_wake_events_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	199608	0	0	0
tb.dut.u_reg.u_wake_events_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	759040	0	0	0
tb.dut.u_reg.u_wake_events_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	199608	0	0	0
tb.dut.u_reg.u_wake_events_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	199608	0	0	0
tb.dut.u_reg.u_wake_events_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	759040	0	0	0
tb.dut.usbdev_avfifo.DataKnown_A	0	0	17813	0	0	0
tb.dut.usbdev_avfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	17813	0	0	0
tb.dut.usbdev_rxfifo.DataKnown_A	0	0	17813	0	0	0
tb.dut.usbdev_rxfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	17813	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AlertsKnown_A	0	0	17813	15288	0	0
tb.dut.CIODnEnKnown_A	0	0	17813	15288	0	0
tb.dut.CIODnKnown_A	0	0	17813	15288	0	0
tb.dut.CIODpEnKnown_A	0	0	17813	15288	0	0
tb.dut.CIODpKnown_A	0	0	17813	15288	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	17813	30	0	0
tb.dut.TlOAReadyKnown_A	0	0	17813	15288	0	0
tb.dut.TlODValidKnown_A	0	0	17813	15288	0	0
tb.dut.USBAonSuspendReqKnown_A	0	0	17813	15288	0	0
tb.dut.USBAonWakeAckKnown_A	0	0	17813	15288	0	0
tb.dut.USBDnPUKnown_A	0	0	17813	15288	0	0
tb.dut.USBDpPUKnown_A	0	0	17813	15288	0	0
tb.dut.USBIntrAvEmptyKnown_A	0	0	17813	15288	0	0
tb.dut.USBIntrAvOverKnown_A	0	0	17813	15288	0	0
tb.dut.USBIntrDisConKnown_A	0	0	17813	15288	0	0
tb.dut.USBIntrFrameKnown_A	0	0	17813	15288	0	0
tb.dut.USBIntrHostLostKnown_A	0	0	17813	15288	0	0
tb.dut.USBIntrLinkInErrKnown_A	0	0	17813	15288	0	0
tb.dut.USBIntrLinkOutErrKnown_A	0	0	17813	15288	0	0
tb.dut.USBIntrLinkResKnown_A	0	0	17813	15288	0	0
tb.dut.USBIntrLinkRstKnown_A	0	0	17813	15288	0	0
tb.dut.USBIntrLinkSusKnown_A	0	0	17813	15288	0	0
tb.dut.USBIntrPktRcvdKnown_A	0	0	17813	15288	0	0
tb.dut.USBIntrPktSentKnown_A	0	0	17813	15288	0	0
tb.dut.USBIntrPwrdKnown_A	0	0	17813	15288	0	0
tb.dut.USBIntrRxBitstuffErrKnown_A	0	0	17813	15288	0	0
tb.dut.USBIntrRxCrCErrKnown_A	0	0	17813	15288	0	0
tb.dut.USBIntrRxFullKnown_A	0	0	17813	15288	0	0
tb.dut.USBIntrRxPidErrKnown_A	0	0	17813	15288	0	0
tb.dut.USBRefPulseKnown_A	0	0	17813	15288	0	0
tb.dut.USBRefValKnown_A	0	0	17813	15288	0	0
tb.dut.USBRxEnableKnown_A	0	0	17813	15288	0	0
tb.dut.USBTxDKnown_A	0	0	17813	15288	0	0
tb.dut.USBTxSe0Known_A	0	0	17813	15288	0	0
tb.dut.gen_no_stubbed_memory.u_memory_2p.i_prim_ram_2p_async_adv.CannotHaveEccAndParity_A	0	0	3	3	0	0
tb.dut.gen_no_stubbed_memory.u_tlul2sram.AddrOutKnown_A	0	0	17813	15288	0	0
tb.dut.gen_no_stubbed_memory.u_tlul2sram.DataIntgOptions_A	0	0	3	3	0	0
tb.dut.gen_no_stubbed_memory.u_tlul2sram.ReqOutKnown_A	0	0	17813	15288	0	0
tb.dut.gen_no_stubbed_memory.u_tlul2sram.SramDwHasByteGranularity_A	0	0	3	3	0	0
tb.dut.gen_no_stubbed_memory.u_tlul2sram.SramDwIsMultipleOfTlulWidth_A	0	0	3	3	0	0
tb.dut.gen_no_stubbed_memory.u_tlul2sram.TlOutKnown_A	0	0	17813	15288	0	0
tb.dut.gen_no_stubbed_memory.u_tlul2sram.TlOutPayloadKnown_AKnownEnable	0	0	17813	15288	0	0
tb.dut.gen_no_stubbed_memory.u_tlul2sram.WdataOutKnown_A	0	0	17813	15288	0	0
tb.dut.gen_no_stubbed_memory.u_tlul2sram.WeOutKnown_A	0	0	17813	15288	0	0
tb.dut.gen_no_stubbed_memory.u_tlul2sram.WmaskOutKnown_A	0	0	17813	15288	0	0
tb.dut.gen_no_stubbed_memory.u_tlul2sram.adapterNoReadOrWrite	0	0	3	3	0	0
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_err.dataWidthOnly32_A	0	0	3	3	0	0
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo.DepthKnown_A	0	0	17813	15288	0	0
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo.RvalidKnown_A	0	0	17813	15288	0	0
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo.WreadyKnown_A	0	0	17813	15288	0	0
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rsp_gen.DataWidthCheck_A	0	0	3	3	0	0
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rsp_gen.PayLoadWidthCheck	0	0	3	3	0	0
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo.DepthKnown_A	0	0	17813	15288	0	0
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo.RvalidKnown_A	0	0	17813	15288	0	0
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo.WreadyKnown_A	0	0	17813	15288	0	0
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo.DepthKnown_A	0	0	17813	15288	0	0
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo.RvalidKnown_A	0	0	17813	15288	0	0
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo.WreadyKnown_A	0	0	17813	15288	0	0
tb.dut.intr_av_empty.IntrTKind_A	0	0	3	3	0	0
tb.dut.intr_av_overflow.IntrTKind_A	0	0	3	3	0	0
tb.dut.intr_disconnected.IntrTKind_A	0	0	3	3	0	0
tb.dut.intr_frame.IntrTKind_A	0	0	3	3	0	0
tb.dut.intr_host_lost.IntrTKind_A	0	0	3	3	0	0
tb.dut.intr_hw_pkt_received.IntrTKind_A	0	0	3	3	0	0
tb.dut.intr_hw_pkt_sent.IntrTKind_A	0	0	3	3	0	0
tb.dut.intr_link_in_err.IntrTKind_A	0	0	3	3	0	0
tb.dut.intr_link_out_err.IntrTKind_A	0	0	3	3	0	0
tb.dut.intr_link_reset.IntrTKind_A	0	0	3	3	0	0
tb.dut.intr_link_resume.IntrTKind_A	0	0	3	3	0	0
tb.dut.intr_link_suspend.IntrTKind_A	0	0	3	3	0	0
tb.dut.intr_powered.IntrTKind_A	0	0	3	3	0	0
tb.dut.intr_rx_bitstuff_err.IntrTKind_A	0	0	3	3	0	0
tb.dut.intr_rx_crc_err.IntrTKind_A	0	0	3	3	0	0
tb.dut.intr_rx_full.IntrTKind_A	0	0	3	3	0	0
tb.dut.intr_rx_pid_err.IntrTKind_A	0	0	3	3	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	759040	175896	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	759040	731465	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	759040	731465	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	759040	163326	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	759040	731465	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	759040	731465	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[153].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[154].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[155].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[156].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[157].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[158].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[159].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[15].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[160].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[161].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
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tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A	0	0	152	152	0	0
tb.dut.tlul_assert_device.gen_device.aDataKnown_M	0	0	759040	76878	0	0
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A	0	0	759040	5570	0	0
tb.dut.tlul_assert_device.gen_device.contigMask_M	0	0	759040	67940	0	0
tb.dut.tlul_assert_device.gen_device.dDataKnown_A	0	0	759040	51359	0	0
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A	0	0	759040	5932	0	0
tb.dut.tlul_assert_device.gen_device.legalAParam_M	0	0	759040	175903	0	0
tb.dut.tlul_assert_device.gen_device.legalDParam_A	0	0	759040	163331	0	0
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M	0	0	759040	175903	0	0
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A	0	0	759040	163331	0	0
tb.dut.tlul_assert_device.gen_device.respOpcode_A	0	0	759040	163331	0	0
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A	0	0	759040	163331	0	0
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A	0	0	759040	3376	0	0
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A	0	0	759040	2722	0	0
tb.dut.tlul_assert_device.p_dbw.TlDbw_A	0	0	152	152	0	0
tb.dut.u_reg.en2addrHit	0	0	759040	66840	0	0
tb.dut.u_reg.reAfterRv	0	0	759040	66838	0	0
tb.dut.u_reg.rePulse	0	0	759040	46999	0	0
tb.dut.u_reg.u_chk.PayLoadWidthCheck	0	0	152	152	0	0
tb.dut.u_reg.u_reg_if.AllowedLatency_A	0	0	152	152	0	0
tb.dut.u_reg.u_reg_if.MatchedWidthAssert	0	0	152	152	0	0
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A	0	0	152	152	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	152	152	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	152	152	0	0
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A	0	0	152	152	0	0
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck	0	0	152	152	0	0
tb.dut.u_reg.u_socket.NotOverflowed_A	0	0	759040	731465	0	0
tb.dut.u_reg.u_socket.fifo_h.reqfifo.DataKnown_A	0	0	759040	175896	0	0
tb.dut.u_reg.u_socket.fifo_h.reqfifo.DepthKnown_A	0	0	759040	731465	0	0
tb.dut.u_reg.u_socket.fifo_h.reqfifo.RvalidKnown_A	0	0	759040	731465	0	0
tb.dut.u_reg.u_socket.fifo_h.reqfifo.WreadyKnown_A	0	0	759040	731465	0	0
tb.dut.u_reg.u_socket.fifo_h.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	152	152	0	0
tb.dut.u_reg.u_socket.fifo_h.rspfifo.DataKnown_A	0	0	759040	163326	0	0
tb.dut.u_reg.u_socket.fifo_h.rspfifo.DepthKnown_A	0	0	759040	731465	0	0
tb.dut.u_reg.u_socket.fifo_h.rspfifo.RvalidKnown_A	0	0	759040	731465	0	0
tb.dut.u_reg.u_socket.fifo_h.rspfifo.WreadyKnown_A	0	0	759040	731465	0	0
tb.dut.u_reg.u_socket.fifo_h.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	152	152	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.DataKnown_A	0	0	759040	30901	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.DepthKnown_A	0	0	759040	731465	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.RvalidKnown_A	0	0	759040	731465	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.WreadyKnown_A	0	0	759040	731465	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	152	152	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.DataKnown_A	0	0	759040	36774	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.DepthKnown_A	0	0	759040	731465	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.RvalidKnown_A	0	0	759040	731465	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.WreadyKnown_A	0	0	759040	731465	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	152	152	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.DataKnown_A	0	0	759040	139202	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.DepthKnown_A	0	0	759040	731465	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.RvalidKnown_A	0	0	759040	731465	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.WreadyKnown_A	0	0	759040	731465	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	152	152	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.DataKnown_A	0	0	759040	126552	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.DepthKnown_A	0	0	759040	731465	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.RvalidKnown_A	0	0	759040	731465	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.WreadyKnown_A	0	0	759040	731465	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	152	152	0	0
tb.dut.u_reg.u_socket.maxN	0	0	152	152	0	0
tb.dut.u_reg.u_wake_control_cdc.BusySrcReqChk_A	0	0	759040	12213	0	0
tb.dut.u_reg.u_wake_control_cdc.DstReqKnown_A	0	0	199608	172780	0	0
tb.dut.u_reg.u_wake_control_cdc.SrcAckBusyChk_A	0	0	759040	513	0	0
tb.dut.u_reg.u_wake_control_cdc.SrcBusyKnown_A	0	0	759040	731465	0	0
tb.dut.u_reg.u_wake_control_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	759040	513	0	0
tb.dut.u_reg.u_wake_control_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	199608	514	0	0
tb.dut.u_reg.u_wake_control_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	199608	513	0	0
tb.dut.u_reg.u_wake_control_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	759040	515	0	0
tb.dut.u_reg.u_wake_events_cdc.DstReqKnown_A	0	0	199608	172780	0	0
tb.dut.u_reg.u_wake_events_cdc.SrcBusyKnown_A	0	0	759040	731465	0	0
tb.dut.u_reg.wePulse	0	0	759040	19839	0	0
tb.dut.usbdev_avfifo.DepthKnown_A	0	0	17813	15288	0	0
tb.dut.usbdev_avfifo.RvalidKnown_A	0	0	17813	15288	0	0
tb.dut.usbdev_avfifo.WreadyKnown_A	0	0	17813	15288	0	0
tb.dut.usbdev_csr_assert.TlulOOBAddrErr_A	0	0	759040	11664	0	0
tb.dut.usbdev_csr_assert.ep_in_enable_rd_A	0	0	759040	798	0	0
tb.dut.usbdev_csr_assert.ep_out_enable_rd_A	0	0	759040	848	0	0
tb.dut.usbdev_csr_assert.in_iso_rd_A	0	0	759040	991	0	0
tb.dut.usbdev_csr_assert.intr_enable_rd_A	0	0	759040	1345	0	0
tb.dut.usbdev_csr_assert.out_iso_rd_A	0	0	759040	931	0	0
tb.dut.usbdev_csr_assert.phy_config_rd_A	0	0	759040	745	0	0
tb.dut.usbdev_csr_assert.phy_pins_drive_rd_A	0	0	759040	741	0	0
tb.dut.usbdev_csr_assert.rxenable_setup_rd_A	0	0	759040	992	0	0
tb.dut.usbdev_csr_assert.set_nak_out_rd_A	0	0	759040	889	0	0
tb.dut.usbdev_impl.ParamAVFifoWidthValid	0	0	3	3	0	0
tb.dut.usbdev_impl.ParamMaxPktSizeByteValid	0	0	3	3	0	0
tb.dut.usbdev_impl.ParamNBufValid	0	0	3	3	0	0
tb.dut.usbdev_impl.ParamNEndpointsValid	0	0	3	3	0	0
tb.dut.usbdev_impl.ParamRXFifoWidthValid	0	0	3	3	0	0
tb.dut.usbdev_impl.ParamSramAwValid	0	0	3	3	0	0
tb.dut.usbdev_impl.u_usb_fs_nb_pe.NumOutEpsEqualsNumInEps_A	0	0	3	3	0	0
tb.dut.usbdev_impl.u_usb_fs_nb_pe.ParamMaxPktSizeByteValid	0	0	3	3	0	0
tb.dut.usbdev_impl.u_usb_fs_nb_pe.ParamNumEpsOutAndInEqual	0	0	3	3	0	0
tb.dut.usbdev_impl.u_usb_fs_nb_pe.ParamNumInEpsValid	0	0	3	3	0	0
tb.dut.usbdev_impl.u_usb_fs_nb_pe.ParamNumOutEpsValid	0	0	3	3	0	0
tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_nb_in_pe.InXactStateValid_A	0	0	17813	15288	0	0
tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_nb_out_pe.OutXactStateValid_A	0	0	17813	15288	0	0
tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_tx.OutStateValid_A	0	0	17813	15288	0	0
tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_tx.StateValid_A	0	0	17813	15288	0	0
tb.dut.usbdev_impl.u_usbdev_linkstate.LincInacStateValid_A	0	0	17813	15288	0	0
tb.dut.usbdev_impl.u_usbdev_linkstate.LinkRstStateValid_A	0	0	17813	15288	0	0
tb.dut.usbdev_impl.u_usbdev_linkstate.LinkStateValid_A	0	0	17813	15288	0	0
tb.dut.usbdev_rxfifo.DepthKnown_A	0	0	17813	15288	0	0
tb.dut.usbdev_rxfifo.RvalidKnown_A	0	0	17813	15288	0	0
tb.dut.usbdev_rxfifo.WreadyKnown_A	0	0	17813	15288	0	0

Assertions Incomplete:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_reg.u_wake_events_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	199608	0	0	152

Assertions Without Attempts:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.i_usbdev_iomux.i_mux_tx_d.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.i_usbdev_iomux.i_mux_tx_dn.gen_generic.u_impl_generic.selKnown0	0	0	0	0	0	0
tb.dut.i_usbdev_iomux.i_mux_tx_dn.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.i_usbdev_iomux.i_mux_tx_dp.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.i_usbdev_iomux.i_mux_tx_oe.gen_generic.u_impl_generic.selKnown0	0	0	0	0	0	0
tb.dut.i_usbdev_iomux.i_mux_tx_oe.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.i_usbdev_iomux.i_mux_tx_se0.gen_generic.u_impl_generic.selKnown0	0	0	0	0	0	0
tb.dut.i_usbdev_iomux.i_mux_tx_se0.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0

---

Detail Report for Cover Sequences

Cover Sequences All Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	759040	1434	1434	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	759040	452	452	1
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	759040	563	563	1
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	759040	392	392	1
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	759040	274	274	1
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	759040	287	287	1
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	759040	319	319	1
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	759040	5828	5828	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	759040	10075	10075	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	759040	16496	16496	131

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	759040	1434	1434	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	759040	452	452	1
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	759040	563	563	1
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	759040	392	392	1
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	759040	274	274	1
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	759040	287	287	1
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	759040	319	319	1
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	759040	5828	5828	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	759040	10075	10075	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	759040	16496	16496	131