Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
77.03	90.03	75.63	94.84	3.12	87.11	92.01	96.47

Total tests in report: 152

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
49.78	49.78	66.05	66.05	58.58	58.58	75.91	75.91	0.00	0.00	72.24	72.24	68.03	68.03	7.62	7.62	/workspace/coverage/cover_reg_top/4.usbdev_csr_rw.2554440178
61.81	12.03	88.45	22.40	71.02	12.44	86.13	10.22	3.12	3.12	86.68	14.44	88.52	20.49	8.74	1.12	/workspace/coverage/default/3.usbdev_sec_cm.1241949950
69.33	7.52	89.54	1.09	72.71	1.69	89.68	3.55	3.12	0.00	86.72	0.04	88.52	0.00	55.02	46.28	/workspace/coverage/cover_reg_top/18.usbdev_intr_test.2164357927
73.82	4.49	89.63	0.08	74.30	1.59	92.04	2.37	3.12	0.00	86.85	0.13	89.96	1.43	80.86	25.84	/workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1632770009
74.73	0.90	89.65	0.02	74.40	0.10	93.55	1.51	3.12	0.00	86.90	0.04	89.96	0.00	85.50	4.65	/workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.3804147650
75.58	0.85	89.65	0.00	74.40	0.00	93.76	0.22	3.12	0.00	86.90	0.00	89.96	0.00	91.26	5.76	/workspace/coverage/cover_reg_top/3.usbdev_intr_test.3718817281
75.90	0.32	90.03	0.38	74.42	0.03	93.76	0.00	3.12	0.00	86.90	0.00	91.80	1.84	91.26	0.00	/workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.3316547520
76.22	0.32	90.03	0.00	74.42	0.00	93.76	0.00	3.12	0.00	86.90	0.00	91.80	0.00	93.49	2.23	/workspace/coverage/cover_reg_top/46.usbdev_intr_test.3285523335
76.53	0.31	90.05	0.02	75.52	1.10	94.41	0.65	3.12	0.00	87.11	0.22	92.01	0.20	93.49	0.00	/workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.2494140232
76.67	0.14	90.05	0.00	75.52	0.00	94.62	0.22	3.12	0.00	87.11	0.00	92.01	0.00	94.24	0.74	/workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.902072230
76.77	0.11	90.05	0.00	75.52	0.00	94.62	0.00	3.12	0.00	87.11	0.00	92.01	0.00	94.98	0.74	/workspace/coverage/cover_reg_top/6.usbdev_intr_test.4047625383
76.85	0.08	90.05	0.00	75.52	0.00	94.62	0.00	3.12	0.00	87.11	0.00	92.01	0.00	95.54	0.56	/workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.3991506894
76.91	0.05	90.05	0.00	75.52	0.00	94.62	0.00	3.12	0.00	87.11	0.00	92.01	0.00	95.91	0.37	/workspace/coverage/cover_reg_top/34.usbdev_intr_test.1706980764
76.95	0.04	90.24	0.19	75.60	0.08	94.62	0.00	3.12	0.00	87.11	0.00	92.01	0.00	95.91	0.00	/workspace/coverage/cover_reg_top/9.usbdev_tl_errors.2483789694
76.98	0.03	90.24	0.00	75.60	0.00	94.84	0.22	3.12	0.00	87.11	0.00	92.01	0.00	95.91	0.00	/workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.1174156961
77.00	0.03	90.24	0.00	75.60	0.00	94.84	0.00	3.12	0.00	87.11	0.00	92.01	0.00	96.10	0.19	/workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.3811486313
77.03	0.03	90.24	0.00	75.60	0.00	94.84	0.00	3.12	0.00	87.11	0.00	92.01	0.00	96.28	0.19	/workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.2973269011
77.06	0.03	90.24	0.00	75.60	0.00	94.84	0.00	3.12	0.00	87.11	0.00	92.01	0.00	96.47	0.19	/workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.283094109
77.08	0.02	90.41	0.17	75.60	0.00	94.84	0.00	3.12	0.00	87.11	0.00	92.01	0.00	96.47	0.00	/workspace/coverage/default/1.usbdev_sec_cm.3995530938
77.08	0.01	90.41	0.00	75.63	0.03	94.84	0.00	3.12	0.00	87.11	0.00	92.01	0.00	96.47	0.00	/workspace/coverage/cover_reg_top/1.usbdev_tl_errors.13587668

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1425510421
/workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.2325138634
/workspace/coverage/cover_reg_top/0.usbdev_csr_rw.2192239634
/workspace/coverage/cover_reg_top/0.usbdev_intr_test.4059415097
/workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.1573533561
/workspace/coverage/cover_reg_top/0.usbdev_mem_walk.2322055849
/workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.1908364518
/workspace/coverage/cover_reg_top/0.usbdev_tl_errors.2192080197
/workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.374486467
/workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.3237234628
/workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.3112146082
/workspace/coverage/cover_reg_top/1.usbdev_csr_rw.2365153106
/workspace/coverage/cover_reg_top/1.usbdev_intr_test.2253932708
/workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.1792579914
/workspace/coverage/cover_reg_top/1.usbdev_mem_walk.1279441170
/workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.917111883
/workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.1964596038
/workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.3946142393
/workspace/coverage/cover_reg_top/10.usbdev_csr_rw.2446914053
/workspace/coverage/cover_reg_top/10.usbdev_intr_test.1473295795
/workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2051263328
/workspace/coverage/cover_reg_top/10.usbdev_tl_errors.401333355
/workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3228956243
/workspace/coverage/cover_reg_top/11.usbdev_csr_rw.962007707
/workspace/coverage/cover_reg_top/11.usbdev_intr_test.3234307368
/workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.1504824653
/workspace/coverage/cover_reg_top/11.usbdev_tl_errors.235138325
/workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.4276526756
/workspace/coverage/cover_reg_top/12.usbdev_csr_rw.2627732347
/workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3355990109
/workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2520729608
/workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.2064529866
/workspace/coverage/cover_reg_top/13.usbdev_csr_rw.2257682933
/workspace/coverage/cover_reg_top/13.usbdev_intr_test.3579925809
/workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.896087170
/workspace/coverage/cover_reg_top/13.usbdev_tl_errors.2274358715
/workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.1800115614
/workspace/coverage/cover_reg_top/14.usbdev_csr_rw.2601025518
/workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.844308586
/workspace/coverage/cover_reg_top/14.usbdev_tl_errors.4077755004
/workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.4193007537
/workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.3350205930
/workspace/coverage/cover_reg_top/15.usbdev_csr_rw.636600188
/workspace/coverage/cover_reg_top/15.usbdev_intr_test.3141150618
/workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3994496358
/workspace/coverage/cover_reg_top/15.usbdev_tl_errors.1569900047
/workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.571982356
/workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.4271823112
/workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3245783100
/workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.2852350129
/workspace/coverage/cover_reg_top/17.usbdev_csr_rw.4100354443
/workspace/coverage/cover_reg_top/17.usbdev_intr_test.878263561
/workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3759000760
/workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.4192088829
/workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1367153204
/workspace/coverage/cover_reg_top/18.usbdev_csr_rw.2335584774
/workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.3580342147
/workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.1715102945
/workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2423797364
/workspace/coverage/cover_reg_top/19.usbdev_csr_rw.518659996
/workspace/coverage/cover_reg_top/19.usbdev_intr_test.1385633069
/workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.2536408877
/workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3586725976
/workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.545554762
/workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.891958338
/workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1295626777
/workspace/coverage/cover_reg_top/2.usbdev_csr_rw.1217510032
/workspace/coverage/cover_reg_top/2.usbdev_intr_test.1664970248
/workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.1555455620
/workspace/coverage/cover_reg_top/2.usbdev_mem_walk.3874052894
/workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2990984752
/workspace/coverage/cover_reg_top/2.usbdev_tl_errors.1695585266
/workspace/coverage/cover_reg_top/22.usbdev_intr_test.3148268445
/workspace/coverage/cover_reg_top/24.usbdev_intr_test.1856916337
/workspace/coverage/cover_reg_top/25.usbdev_intr_test.572315195
/workspace/coverage/cover_reg_top/26.usbdev_intr_test.2982087122
/workspace/coverage/cover_reg_top/27.usbdev_intr_test.3291275219
/workspace/coverage/cover_reg_top/28.usbdev_intr_test.2187005058
/workspace/coverage/cover_reg_top/29.usbdev_intr_test.892499256
/workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.2155454255
/workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3456055926
/workspace/coverage/cover_reg_top/3.usbdev_csr_rw.536740547
/workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.3078606700
/workspace/coverage/cover_reg_top/3.usbdev_mem_walk.328720530
/workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.2225601900
/workspace/coverage/cover_reg_top/3.usbdev_tl_errors.570206436
/workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.2409799252
/workspace/coverage/cover_reg_top/32.usbdev_intr_test.351879099
/workspace/coverage/cover_reg_top/35.usbdev_intr_test.525744889
/workspace/coverage/cover_reg_top/36.usbdev_intr_test.1281541721
/workspace/coverage/cover_reg_top/37.usbdev_intr_test.2237788298
/workspace/coverage/cover_reg_top/38.usbdev_intr_test.2194262103
/workspace/coverage/cover_reg_top/39.usbdev_intr_test.339960176
/workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.3384218772
/workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.586390147
/workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.3998961599
/workspace/coverage/cover_reg_top/4.usbdev_intr_test.3421378746
/workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.3805585887
/workspace/coverage/cover_reg_top/4.usbdev_mem_walk.3434180165
/workspace/coverage/cover_reg_top/4.usbdev_tl_errors.989446806
/workspace/coverage/cover_reg_top/40.usbdev_intr_test.3765291810
/workspace/coverage/cover_reg_top/42.usbdev_intr_test.2535845584
/workspace/coverage/cover_reg_top/43.usbdev_intr_test.884914720
/workspace/coverage/cover_reg_top/44.usbdev_intr_test.2683476449
/workspace/coverage/cover_reg_top/48.usbdev_intr_test.1305416728
/workspace/coverage/cover_reg_top/49.usbdev_intr_test.4292448236
/workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1176601863
/workspace/coverage/cover_reg_top/5.usbdev_csr_rw.617449365
/workspace/coverage/cover_reg_top/5.usbdev_intr_test.1227854242
/workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.2058994566
/workspace/coverage/cover_reg_top/5.usbdev_tl_errors.696395272
/workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.2382282631
/workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.1344946434
/workspace/coverage/cover_reg_top/6.usbdev_csr_rw.2783338420
/workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3437736924
/workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1501427818
/workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.2601229418
/workspace/coverage/cover_reg_top/7.usbdev_csr_rw.2435254635
/workspace/coverage/cover_reg_top/7.usbdev_intr_test.4043776043
/workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.3538452209
/workspace/coverage/cover_reg_top/7.usbdev_tl_errors.1953218929
/workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.4280283151
/workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2548807686
/workspace/coverage/cover_reg_top/8.usbdev_intr_test.4072309085
/workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.762122135
/workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2513392368
/workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.1131982792
/workspace/coverage/cover_reg_top/9.usbdev_csr_rw.3807558206
/workspace/coverage/cover_reg_top/9.usbdev_intr_test.3998760071
/workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.1678287661
/workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.3220262165
/workspace/coverage/default/2.usbdev_sec_cm.3111403636

Total test records in report: 152

tests.html | tests1.html | tests2.html

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/3.usbdev_sec_cm.1241949950	Jan 21 12:27:29 PM PST 24	Jan 21 12:27:32 PM PST 24	86228485 ps
T2	/workspace/coverage/default/1.usbdev_sec_cm.3995530938	Jan 21 12:35:51 PM PST 24	Jan 21 12:35:57 PM PST 24	109875870 ps
T3	/workspace/coverage/default/2.usbdev_sec_cm.3111403636	Jan 21 12:24:18 PM PST 24	Jan 21 12:24:21 PM PST 24	175051871 ps
T4	/workspace/coverage/cover_reg_top/13.usbdev_intr_test.3579925809	Jan 21 07:49:41 PM PST 24	Jan 21 07:49:44 PM PST 24	25873232 ps
T5	/workspace/coverage/cover_reg_top/4.usbdev_csr_rw.2554440178	Jan 21 07:49:09 PM PST 24	Jan 21 07:49:13 PM PST 24	38658921 ps
T6	/workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1632770009	Jan 21 07:49:47 PM PST 24	Jan 21 07:49:53 PM PST 24	93660595 ps
T7	/workspace/coverage/cover_reg_top/0.usbdev_csr_rw.2192239634	Jan 21 07:48:54 PM PST 24	Jan 21 07:48:57 PM PST 24	50438333 ps
T8	/workspace/coverage/cover_reg_top/35.usbdev_intr_test.525744889	Jan 21 07:49:56 PM PST 24	Jan 21 07:49:59 PM PST 24	30677648 ps
T9	/workspace/coverage/cover_reg_top/26.usbdev_intr_test.2982087122	Jan 21 07:50:08 PM PST 24	Jan 21 07:50:12 PM PST 24	27895586 ps
T10	/workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.2601229418	Jan 21 07:49:29 PM PST 24	Jan 21 07:49:36 PM PST 24	29940684 ps
T11	/workspace/coverage/cover_reg_top/2.usbdev_mem_walk.3874052894	Jan 21 07:48:57 PM PST 24	Jan 21 07:49:03 PM PST 24	149326368 ps
T23	/workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.1504824653	Jan 21 07:49:27 PM PST 24	Jan 21 07:49:32 PM PST 24	156280704 ps
T28	/workspace/coverage/cover_reg_top/18.usbdev_intr_test.2164357927	Jan 21 07:49:54 PM PST 24	Jan 21 07:49:58 PM PST 24	53930405 ps
T22	/workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.3804147650	Jan 21 07:49:04 PM PST 24	Jan 21 07:49:08 PM PST 24	408580889 ps
T24	/workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.2325138634	Jan 21 07:48:50 PM PST 24	Jan 21 07:48:52 PM PST 24	48359242 ps
T56	/workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.2058994566	Jan 21 07:49:24 PM PST 24	Jan 21 07:49:32 PM PST 24	57603518 ps
T12	/workspace/coverage/cover_reg_top/0.usbdev_mem_walk.2322055849	Jan 21 07:48:45 PM PST 24	Jan 21 07:48:50 PM PST 24	245601884 ps
T29	/workspace/coverage/cover_reg_top/3.usbdev_intr_test.3718817281	Jan 21 07:49:02 PM PST 24	Jan 21 07:49:04 PM PST 24	24297828 ps
T13	/workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.3811486313	Jan 21 07:48:58 PM PST 24	Jan 21 07:49:02 PM PST 24	66669670 ps
T14	/workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.1555455620	Jan 21 07:48:55 PM PST 24	Jan 21 07:48:58 PM PST 24	46212030 ps
T15	/workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.3078606700	Jan 21 07:49:06 PM PST 24	Jan 21 07:49:10 PM PST 24	99106389 ps
T19	/workspace/coverage/cover_reg_top/48.usbdev_intr_test.1305416728	Jan 21 07:50:05 PM PST 24	Jan 21 07:50:09 PM PST 24	21314843 ps
T20	/workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3994496358	Jan 21 07:49:44 PM PST 24	Jan 21 07:49:52 PM PST 24	80004468 ps
T21	/workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.3316547520	Jan 21 07:49:12 PM PST 24	Jan 21 07:49:16 PM PST 24	157332675 ps
T47	/workspace/coverage/cover_reg_top/39.usbdev_intr_test.339960176	Jan 21 07:50:05 PM PST 24	Jan 21 07:50:08 PM PST 24	22750353 ps
T48	/workspace/coverage/cover_reg_top/37.usbdev_intr_test.2237788298	Jan 21 07:50:02 PM PST 24	Jan 21 07:50:05 PM PST 24	27291292 ps
T16	/workspace/coverage/cover_reg_top/5.usbdev_tl_errors.696395272	Jan 21 07:49:10 PM PST 24	Jan 21 07:49:15 PM PST 24	166810023 ps
T36	/workspace/coverage/cover_reg_top/7.usbdev_csr_rw.2435254635	Jan 21 07:49:30 PM PST 24	Jan 21 07:49:37 PM PST 24	61393769 ps
T37	/workspace/coverage/cover_reg_top/17.usbdev_csr_rw.4100354443	Jan 21 07:49:47 PM PST 24	Jan 21 07:49:52 PM PST 24	34311017 ps
T38	/workspace/coverage/cover_reg_top/2.usbdev_csr_rw.1217510032	Jan 21 07:49:06 PM PST 24	Jan 21 07:49:08 PM PST 24	50342896 ps
T39	/workspace/coverage/cover_reg_top/9.usbdev_csr_rw.3807558206	Jan 21 07:49:24 PM PST 24	Jan 21 07:49:32 PM PST 24	69155640 ps
T40	/workspace/coverage/cover_reg_top/11.usbdev_intr_test.3234307368	Jan 21 07:49:34 PM PST 24	Jan 21 07:49:38 PM PST 24	50523273 ps
T41	/workspace/coverage/cover_reg_top/24.usbdev_intr_test.1856916337	Jan 21 07:57:32 PM PST 24	Jan 21 07:57:34 PM PST 24	31691373 ps
T42	/workspace/coverage/cover_reg_top/28.usbdev_intr_test.2187005058	Jan 21 07:49:55 PM PST 24	Jan 21 07:49:59 PM PST 24	36342194 ps
T44	/workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.2225601900	Jan 21 07:49:06 PM PST 24	Jan 21 07:49:09 PM PST 24	43424102 ps
T49	/workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.2155454255	Jan 21 07:49:07 PM PST 24	Jan 21 07:49:13 PM PST 24	321613079 ps
T50	/workspace/coverage/cover_reg_top/19.usbdev_csr_rw.518659996	Jan 21 07:49:55 PM PST 24	Jan 21 07:49:59 PM PST 24	52651685 ps
T51	/workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.3237234628	Jan 21 07:48:58 PM PST 24	Jan 21 07:49:05 PM PST 24	200719323 ps
T17	/workspace/coverage/cover_reg_top/9.usbdev_tl_errors.2483789694	Jan 21 07:49:24 PM PST 24	Jan 21 07:49:34 PM PST 24	229483594 ps
T75	/workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2990984752	Jan 21 07:49:03 PM PST 24	Jan 21 07:49:06 PM PST 24	55099145 ps
T18	/workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1367153204	Jan 21 08:53:40 PM PST 24	Jan 21 08:53:58 PM PST 24	32064179 ps
T30	/workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.1964596038	Jan 21 07:48:59 PM PST 24	Jan 21 07:49:04 PM PST 24	336693638 ps
T43	/workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.902072230	Jan 21 07:49:13 PM PST 24	Jan 21 07:49:17 PM PST 24	120325616 ps
T31	/workspace/coverage/cover_reg_top/11.usbdev_tl_errors.235138325	Jan 21 07:49:30 PM PST 24	Jan 21 07:49:39 PM PST 24	190567581 ps
T68	/workspace/coverage/cover_reg_top/44.usbdev_intr_test.2683476449	Jan 21 07:50:03 PM PST 24	Jan 21 07:50:06 PM PST 24	27403803 ps
T66	/workspace/coverage/cover_reg_top/9.usbdev_intr_test.3998760071	Jan 21 07:49:24 PM PST 24	Jan 21 07:49:31 PM PST 24	18372505 ps
T32	/workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.4193007537	Jan 21 07:49:41 PM PST 24	Jan 21 07:49:48 PM PST 24	422546485 ps
T57	/workspace/coverage/cover_reg_top/6.usbdev_csr_rw.2783338420	Jan 21 07:49:24 PM PST 24	Jan 21 07:49:31 PM PST 24	55283829 ps
T52	/workspace/coverage/cover_reg_top/1.usbdev_csr_rw.2365153106	Jan 21 07:48:59 PM PST 24	Jan 21 07:49:01 PM PST 24	51804347 ps
T33	/workspace/coverage/cover_reg_top/4.usbdev_tl_errors.989446806	Jan 21 07:49:07 PM PST 24	Jan 21 07:49:12 PM PST 24	98930251 ps
T34	/workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3586725976	Jan 21 08:56:00 PM PST 24	Jan 21 08:56:34 PM PST 24	158502468 ps
T35	/workspace/coverage/cover_reg_top/7.usbdev_tl_errors.1953218929	Jan 21 07:49:12 PM PST 24	Jan 21 07:49:15 PM PST 24	116694893 ps
T65	/workspace/coverage/cover_reg_top/46.usbdev_intr_test.3285523335	Jan 21 07:50:04 PM PST 24	Jan 21 07:50:07 PM PST 24	30462408 ps
T76	/workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1295626777	Jan 21 07:49:07 PM PST 24	Jan 21 07:49:10 PM PST 24	37023577 ps
T45	/workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1501427818	Jan 21 07:49:16 PM PST 24	Jan 21 07:49:19 PM PST 24	104595195 ps
T53	/workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.1792579914	Jan 21 07:48:59 PM PST 24	Jan 21 07:49:02 PM PST 24	84548955 ps
T77	/workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.374486467	Jan 21 07:49:06 PM PST 24	Jan 21 07:49:10 PM PST 24	127768950 ps
T78	/workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.4271823112	Jan 21 07:49:47 PM PST 24	Jan 21 07:49:52 PM PST 24	70539622 ps
T55	/workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.1573533561	Jan 21 07:48:50 PM PST 24	Jan 21 07:48:54 PM PST 24	86703900 ps
T25	/workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.2494140232	Jan 21 07:49:06 PM PST 24	Jan 21 07:49:09 PM PST 24	55592065 ps
T70	/workspace/coverage/cover_reg_top/19.usbdev_intr_test.1385633069	Jan 21 07:49:56 PM PST 24	Jan 21 07:49:59 PM PST 24	24321142 ps
T64	/workspace/coverage/cover_reg_top/25.usbdev_intr_test.572315195	Jan 21 07:49:55 PM PST 24	Jan 21 07:49:59 PM PST 24	25583772 ps
T58	/workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.4192088829	Jan 21 07:49:53 PM PST 24	Jan 21 07:49:59 PM PST 24	185548890 ps
T79	/workspace/coverage/cover_reg_top/14.usbdev_csr_rw.2601025518	Jan 21 07:49:36 PM PST 24	Jan 21 07:49:39 PM PST 24	33524158 ps
T80	/workspace/coverage/cover_reg_top/5.usbdev_csr_rw.617449365	Jan 21 07:49:09 PM PST 24	Jan 21 07:49:11 PM PST 24	31676751 ps
T46	/workspace/coverage/cover_reg_top/3.usbdev_tl_errors.570206436	Jan 21 07:49:02 PM PST 24	Jan 21 07:49:06 PM PST 24	261976508 ps
T81	/workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.3350205930	Jan 21 07:49:53 PM PST 24	Jan 21 07:49:58 PM PST 24	27329581 ps
T82	/workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1176601863	Jan 21 07:49:24 PM PST 24	Jan 21 07:49:32 PM PST 24	73053752 ps
T60	/workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.2409799252	Jan 21 07:49:03 PM PST 24	Jan 21 07:49:08 PM PST 24	136425027 ps
T83	/workspace/coverage/cover_reg_top/1.usbdev_mem_walk.1279441170	Jan 21 07:48:54 PM PST 24	Jan 21 07:49:01 PM PST 24	154710255 ps
T67	/workspace/coverage/cover_reg_top/0.usbdev_intr_test.4059415097	Jan 21 07:48:50 PM PST 24	Jan 21 07:48:53 PM PST 24	26336110 ps
T74	/workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3228956243	Jan 21 07:49:33 PM PST 24	Jan 21 07:49:39 PM PST 24	135418197 ps
T84	/workspace/coverage/cover_reg_top/3.usbdev_csr_rw.536740547	Jan 21 07:49:02 PM PST 24	Jan 21 07:49:04 PM PST 24	43583751 ps
T85	/workspace/coverage/cover_reg_top/22.usbdev_intr_test.3148268445	Jan 21 07:49:55 PM PST 24	Jan 21 07:49:58 PM PST 24	35607028 ps
T86	/workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3355990109	Jan 21 07:49:39 PM PST 24	Jan 21 07:49:43 PM PST 24	168756219 ps
T87	/workspace/coverage/cover_reg_top/13.usbdev_csr_rw.2257682933	Jan 21 07:49:39 PM PST 24	Jan 21 07:49:41 PM PST 24	41434961 ps
T63	/workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.3991506894	Jan 21 07:49:44 PM PST 24	Jan 21 07:49:55 PM PST 24	224944937 ps
T88	/workspace/coverage/cover_reg_top/4.usbdev_mem_walk.3434180165	Jan 21 07:49:02 PM PST 24	Jan 21 07:49:08 PM PST 24	199118779 ps
T72	/workspace/coverage/cover_reg_top/42.usbdev_intr_test.2535845584	Jan 21 07:50:04 PM PST 24	Jan 21 07:50:07 PM PST 24	23264236 ps
T89	/workspace/coverage/cover_reg_top/1.usbdev_intr_test.2253932708	Jan 21 07:49:00 PM PST 24	Jan 21 07:49:01 PM PST 24	26216054 ps
T90	/workspace/coverage/cover_reg_top/1.usbdev_tl_errors.13587668	Jan 21 07:48:56 PM PST 24	Jan 21 07:49:00 PM PST 24	176639911 ps
T73	/workspace/coverage/cover_reg_top/6.usbdev_intr_test.4047625383	Jan 21 07:49:12 PM PST 24	Jan 21 07:49:15 PM PST 24	26080899 ps
T91	/workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1425510421	Jan 21 07:48:57 PM PST 24	Jan 21 07:49:08 PM PST 24	484832896 ps
T92	/workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.1131982792	Jan 21 07:49:24 PM PST 24	Jan 21 07:49:32 PM PST 24	86542208 ps
T93	/workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2051263328	Jan 21 07:49:26 PM PST 24	Jan 21 07:49:32 PM PST 24	167270109 ps
T94	/workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.3538452209	Jan 21 07:49:22 PM PST 24	Jan 21 07:49:29 PM PST 24	60474013 ps
T71	/workspace/coverage/cover_reg_top/49.usbdev_intr_test.4292448236	Jan 21 07:50:04 PM PST 24	Jan 21 07:50:07 PM PST 24	30844923 ps
T95	/workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.762122135	Jan 21 07:49:26 PM PST 24	Jan 21 07:49:32 PM PST 24	72970910 ps
T96	/workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.3946142393	Jan 21 07:49:31 PM PST 24	Jan 21 07:49:38 PM PST 24	51333245 ps
T97	/workspace/coverage/cover_reg_top/8.usbdev_intr_test.4072309085	Jan 21 07:49:24 PM PST 24	Jan 21 07:49:31 PM PST 24	25752837 ps
T69	/workspace/coverage/cover_reg_top/7.usbdev_intr_test.4043776043	Jan 21 07:49:25 PM PST 24	Jan 21 07:49:31 PM PST 24	71252829 ps
T98	/workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.1800115614	Jan 21 07:49:45 PM PST 24	Jan 21 07:49:52 PM PST 24	61351744 ps
T54	/workspace/coverage/cover_reg_top/15.usbdev_csr_rw.636600188	Jan 21 07:49:46 PM PST 24	Jan 21 07:49:52 PM PST 24	26128274 ps
T99	/workspace/coverage/cover_reg_top/36.usbdev_intr_test.1281541721	Jan 21 07:49:56 PM PST 24	Jan 21 07:50:00 PM PST 24	42299241 ps
T100	/workspace/coverage/cover_reg_top/10.usbdev_csr_rw.2446914053	Jan 21 07:49:26 PM PST 24	Jan 21 07:49:31 PM PST 24	66602259 ps
T101	/workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3759000760	Jan 21 07:49:55 PM PST 24	Jan 21 07:49:59 PM PST 24	36851642 ps
T102	/workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3437736924	Jan 21 07:49:12 PM PST 24	Jan 21 07:49:15 PM PST 24	139382469 ps
T103	/workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.2382282631	Jan 21 07:49:09 PM PST 24	Jan 21 07:49:15 PM PST 24	277761061 ps
T104	/workspace/coverage/cover_reg_top/27.usbdev_intr_test.3291275219	Jan 21 08:50:09 PM PST 24	Jan 21 08:50:34 PM PST 24	25795964 ps
T105	/workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.3805585887	Jan 21 07:49:06 PM PST 24	Jan 21 07:49:11 PM PST 24	196359098 ps
T106	/workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2423797364	Jan 21 07:49:55 PM PST 24	Jan 21 07:49:59 PM PST 24	52564667 ps
T61	/workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.3220262165	Jan 21 07:49:27 PM PST 24	Jan 21 07:49:34 PM PST 24	472564055 ps
T107	/workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.545554762	Jan 21 07:49:03 PM PST 24	Jan 21 07:49:08 PM PST 24	313431253 ps
T108	/workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.1174156961	Jan 21 07:48:47 PM PST 24	Jan 21 07:48:51 PM PST 24	345164038 ps
T109	/workspace/coverage/cover_reg_top/29.usbdev_intr_test.892499256	Jan 21 08:09:43 PM PST 24	Jan 21 08:09:45 PM PST 24	21552396 ps
T110	/workspace/coverage/cover_reg_top/0.usbdev_tl_errors.2192080197	Jan 21 07:48:50 PM PST 24	Jan 21 07:48:55 PM PST 24	238451227 ps
T111	/workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.1715102945	Jan 21 07:49:54 PM PST 24	Jan 21 07:50:01 PM PST 24	354035110 ps
T112	/workspace/coverage/cover_reg_top/11.usbdev_csr_rw.962007707	Jan 21 07:49:27 PM PST 24	Jan 21 07:49:32 PM PST 24	32900545 ps
T113	/workspace/coverage/cover_reg_top/5.usbdev_intr_test.1227854242	Jan 21 07:49:24 PM PST 24	Jan 21 07:49:31 PM PST 24	57272287 ps
T26	/workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.891958338	Jan 21 07:48:56 PM PST 24	Jan 21 07:48:58 PM PST 24	43241425 ps
T114	/workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2513392368	Jan 21 07:49:22 PM PST 24	Jan 21 07:49:30 PM PST 24	141482471 ps
T115	/workspace/coverage/cover_reg_top/13.usbdev_tl_errors.2274358715	Jan 21 07:49:42 PM PST 24	Jan 21 07:49:46 PM PST 24	200190633 ps
T116	/workspace/coverage/cover_reg_top/43.usbdev_intr_test.884914720	Jan 21 07:50:05 PM PST 24	Jan 21 07:50:08 PM PST 24	36140233 ps
T117	/workspace/coverage/cover_reg_top/15.usbdev_intr_test.3141150618	Jan 21 07:49:45 PM PST 24	Jan 21 07:49:51 PM PST 24	33087582 ps
T118	/workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.2852350129	Jan 21 07:49:55 PM PST 24	Jan 21 07:49:59 PM PST 24	29571001 ps
T119	/workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3456055926	Jan 21 07:49:02 PM PST 24	Jan 21 07:49:05 PM PST 24	94222046 ps
T120	/workspace/coverage/cover_reg_top/4.usbdev_intr_test.3421378746	Jan 21 07:49:02 PM PST 24	Jan 21 07:49:04 PM PST 24	30720385 ps
T121	/workspace/coverage/cover_reg_top/34.usbdev_intr_test.1706980764	Jan 21 08:53:40 PM PST 24	Jan 21 08:53:58 PM PST 24	26641984 ps
T122	/workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.2064529866	Jan 21 07:49:36 PM PST 24	Jan 21 07:49:39 PM PST 24	44152628 ps
T123	/workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.3384218772	Jan 21 07:49:10 PM PST 24	Jan 21 07:49:16 PM PST 24	307300771 ps
T124	/workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.4280283151	Jan 21 07:49:26 PM PST 24	Jan 21 07:49:32 PM PST 24	62759041 ps
T125	/workspace/coverage/cover_reg_top/38.usbdev_intr_test.2194262103	Jan 21 07:50:08 PM PST 24	Jan 21 07:50:12 PM PST 24	31595479 ps
T126	/workspace/coverage/cover_reg_top/2.usbdev_tl_errors.1695585266	Jan 21 07:48:58 PM PST 24	Jan 21 07:49:01 PM PST 24	162745112 ps
T127	/workspace/coverage/cover_reg_top/10.usbdev_tl_errors.401333355	Jan 21 07:49:24 PM PST 24	Jan 21 07:49:33 PM PST 24	63516961 ps
T128	/workspace/coverage/cover_reg_top/3.usbdev_mem_walk.328720530	Jan 21 07:49:01 PM PST 24	Jan 21 07:49:07 PM PST 24	479372431 ps
T129	/workspace/coverage/cover_reg_top/2.usbdev_intr_test.1664970248	Jan 21 07:49:06 PM PST 24	Jan 21 07:49:09 PM PST 24	29383560 ps
T130	/workspace/coverage/cover_reg_top/12.usbdev_csr_rw.2627732347	Jan 21 07:49:47 PM PST 24	Jan 21 07:49:52 PM PST 24	70205989 ps
T131	/workspace/coverage/cover_reg_top/18.usbdev_csr_rw.2335584774	Jan 21 07:49:55 PM PST 24	Jan 21 07:49:59 PM PST 24	43600059 ps
T132	/workspace/coverage/cover_reg_top/17.usbdev_intr_test.878263561	Jan 21 07:49:53 PM PST 24	Jan 21 07:49:58 PM PST 24	23694329 ps
T133	/workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.844308586	Jan 21 07:49:40 PM PST 24	Jan 21 07:49:43 PM PST 24	70588936 ps
T134	/workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.3998961599	Jan 21 07:49:14 PM PST 24	Jan 21 07:49:16 PM PST 24	30925674 ps
T135	/workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3245783100	Jan 21 07:49:45 PM PST 24	Jan 21 07:49:53 PM PST 24	57592169 ps
T62	/workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.2973269011	Jan 21 07:49:31 PM PST 24	Jan 21 07:49:39 PM PST 24	169244851 ps
T136	/workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.571982356	Jan 21 07:49:47 PM PST 24	Jan 21 07:49:52 PM PST 24	55511385 ps
T137	/workspace/coverage/cover_reg_top/10.usbdev_intr_test.1473295795	Jan 21 07:49:24 PM PST 24	Jan 21 07:49:31 PM PST 24	21455541 ps
T138	/workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.2536408877	Jan 21 07:49:59 PM PST 24	Jan 21 07:50:04 PM PST 24	73989001 ps
T139	/workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2548807686	Jan 21 07:49:26 PM PST 24	Jan 21 07:49:32 PM PST 24	59321325 ps
T140	/workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.3112146082	Jan 21 07:49:06 PM PST 24	Jan 21 07:49:09 PM PST 24	34533384 ps
T141	/workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.917111883	Jan 21 07:49:02 PM PST 24	Jan 21 07:49:04 PM PST 24	109917017 ps
T59	/workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.283094109	Jan 21 07:49:26 PM PST 24	Jan 21 07:49:36 PM PST 24	258998927 ps
T142	/workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.1908364518	Jan 21 07:48:51 PM PST 24	Jan 21 07:48:55 PM PST 24	102835247 ps
T143	/workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.3580342147	Jan 21 07:49:53 PM PST 24	Jan 21 07:49:59 PM PST 24	62147288 ps
T144	/workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.1678287661	Jan 21 07:49:31 PM PST 24	Jan 21 07:49:38 PM PST 24	73393162 ps
T145	/workspace/coverage/cover_reg_top/40.usbdev_intr_test.3765291810	Jan 21 07:50:01 PM PST 24	Jan 21 07:50:05 PM PST 24	25608663 ps
T146	/workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.896087170	Jan 21 07:49:38 PM PST 24	Jan 21 07:49:41 PM PST 24	116810509 ps
T147	/workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2520729608	Jan 21 07:49:30 PM PST 24	Jan 21 07:49:38 PM PST 24	104770306 ps
T148	/workspace/coverage/cover_reg_top/14.usbdev_tl_errors.4077755004	Jan 21 07:49:38 PM PST 24	Jan 21 07:49:42 PM PST 24	196109046 ps
T27	/workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.586390147	Jan 21 07:49:05 PM PST 24	Jan 21 07:49:07 PM PST 24	115106131 ps
T149	/workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.4276526756	Jan 21 07:49:39 PM PST 24	Jan 21 07:49:41 PM PST 24	31471002 ps
T150	/workspace/coverage/cover_reg_top/15.usbdev_tl_errors.1569900047	Jan 21 07:49:40 PM PST 24	Jan 21 07:49:44 PM PST 24	154988204 ps
T151	/workspace/coverage/cover_reg_top/32.usbdev_intr_test.351879099	Jan 21 07:49:55 PM PST 24	Jan 21 07:49:58 PM PST 24	31017367 ps
T152	/workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.1344946434	Jan 21 07:49:21 PM PST 24	Jan 21 07:49:23 PM PST 24	50087061 ps

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_rw.2554440178
Short name	T5
Test name
Test status
Simulation time	38658921 ps
CPU time	1.01 seconds
Started	Jan 21 07:49:09 PM PST 24
Finished	Jan 21 07:49:13 PM PST 24
Peak memory	202008 kb
Host	smart-45f74479-44de-4a65-8601-3f7fc576e946
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554440178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.2554440178
Directory	/workspace/4.usbdev_csr_rw/latest

Test location	/workspace/coverage/default/3.usbdev_sec_cm.1241949950
Short name	T1
Test name
Test status
Simulation time	86228485 ps
CPU time	0.88 seconds
Started	Jan 21 12:27:29 PM PST 24
Finished	Jan 21 12:27:32 PM PST 24
Peak memory	220400 kb
Host	smart-d12de5e1-b81d-4e16-bd9e-837fdb91074b
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1241949950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.1241949950
Directory	/workspace/3.usbdev_sec_cm/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_intr_test.2164357927
Short name	T28
Test name
Test status
Simulation time	53930405 ps
CPU time	0.66 seconds
Started	Jan 21 07:49:54 PM PST 24
Finished	Jan 21 07:49:58 PM PST 24
Peak memory	201220 kb
Host	smart-fa86cfc3-2f54-42d2-a519-62faec094f63
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2164357927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.2164357927
Directory	/workspace/18.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1632770009
Short name	T6
Test name
Test status
Simulation time	93660595 ps
CPU time	2.82 seconds
Started	Jan 21 07:49:47 PM PST 24
Finished	Jan 21 07:49:53 PM PST 24
Peak memory	202044 kb
Host	smart-e7de2af1-5856-461b-af11-4a1b3b3d60f5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1632770009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.1632770009
Directory	/workspace/18.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.3804147650
Short name	T22
Test name
Test status
Simulation time	408580889 ps
CPU time	2.73 seconds
Started	Jan 21 07:49:04 PM PST 24
Finished	Jan 21 07:49:08 PM PST 24
Peak memory	201920 kb
Host	smart-f072d489-22e0-4859-8e3c-fe7ce64ebfef
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3804147650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.3804147650
Directory	/workspace/4.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_intr_test.3718817281
Short name	T29
Test name
Test status
Simulation time	24297828 ps
CPU time	0.7 seconds
Started	Jan 21 07:49:02 PM PST 24
Finished	Jan 21 07:49:04 PM PST 24
Peak memory	201236 kb
Host	smart-160a42cd-ebf0-421b-be38-37a4aebe0960
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3718817281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.3718817281
Directory	/workspace/3.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.3316547520
Short name	T21
Test name
Test status
Simulation time	157332675 ps
CPU time	1.52 seconds
Started	Jan 21 07:49:12 PM PST 24
Finished	Jan 21 07:49:16 PM PST 24
Peak memory	202036 kb
Host	smart-853c988f-74d6-4541-b879-4f0a9222a294
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316547520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_c sr_outstanding.3316547520
Directory	/workspace/4.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/46.usbdev_intr_test.3285523335
Short name	T65
Test name
Test status
Simulation time	30462408 ps
CPU time	0.67 seconds
Started	Jan 21 07:50:04 PM PST 24
Finished	Jan 21 07:50:07 PM PST 24
Peak memory	201104 kb
Host	smart-5ff23efb-b8d1-49fa-b0af-9c413fe5ac5c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3285523335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.3285523335
Directory	/workspace/46.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.2494140232
Short name	T25
Test name
Test status
Simulation time	55592065 ps
CPU time	0.84 seconds
Started	Jan 21 07:49:06 PM PST 24
Finished	Jan 21 07:49:09 PM PST 24
Peak memory	200504 kb
Host	smart-67ab1b0c-3ec8-43a3-bfbe-092cad44a257
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494140232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.2494140232
Directory	/workspace/1.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.902072230
Short name	T43
Test name
Test status
Simulation time	120325616 ps
CPU time	2.43 seconds
Started	Jan 21 07:49:13 PM PST 24
Finished	Jan 21 07:49:17 PM PST 24
Peak memory	202060 kb
Host	smart-135069a2-8f1f-4bab-b8c4-c992c7276fc9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=902072230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.902072230
Directory	/workspace/6.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_intr_test.4047625383
Short name	T73
Test name
Test status
Simulation time	26080899 ps
CPU time	0.74 seconds
Started	Jan 21 07:49:12 PM PST 24
Finished	Jan 21 07:49:15 PM PST 24
Peak memory	201200 kb
Host	smart-fde3a596-cc9f-4d6e-a7b0-8d40f0f5f28d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4047625383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.4047625383
Directory	/workspace/6.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.3991506894
Short name	T63
Test name
Test status
Simulation time	224944937 ps
CPU time	4.16 seconds
Started	Jan 21 07:49:44 PM PST 24
Finished	Jan 21 07:49:55 PM PST 24
Peak memory	201996 kb
Host	smart-befb6547-ff82-46f2-a1f5-d5a2ddfc03ac
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3991506894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.3991506894
Directory	/workspace/12.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/34.usbdev_intr_test.1706980764
Short name	T121
Test name
Test status
Simulation time	26641984 ps
CPU time	0.67 seconds
Started	Jan 21 08:53:40 PM PST 24
Finished	Jan 21 08:53:58 PM PST 24
Peak memory	201172 kb
Host	smart-f92c06c4-760f-479b-b323-dbb5a86f123f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1706980764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.1706980764
Directory	/workspace/34.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_tl_errors.2483789694
Short name	T17
Test name
Test status
Simulation time	229483594 ps
CPU time	3.06 seconds
Started	Jan 21 07:49:24 PM PST 24
Finished	Jan 21 07:49:34 PM PST 24
Peak memory	202080 kb
Host	smart-26c4b162-d859-44c9-a1e3-6a0a2cc0b0a4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2483789694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.2483789694
Directory	/workspace/9.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.1174156961
Short name	T108
Test name
Test status
Simulation time	345164038 ps
CPU time	3.31 seconds
Started	Jan 21 07:48:47 PM PST 24
Finished	Jan 21 07:48:51 PM PST 24
Peak memory	202028 kb
Host	smart-7c406d58-0726-4ce1-9e1e-a780c651ebc4
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174156961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.1174156961
Directory	/workspace/0.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.3811486313
Short name	T13
Test name
Test status
Simulation time	66669670 ps
CPU time	2.34 seconds
Started	Jan 21 07:48:58 PM PST 24
Finished	Jan 21 07:49:02 PM PST 24
Peak memory	218456 kb
Host	smart-680c2aed-0d6f-4ce1-a3ef-da4fd6cea76d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811486313 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_mem_rw_with_rand_reset.3811486313
Directory	/workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.2973269011
Short name	T62
Test name
Test status
Simulation time	169244851 ps
CPU time	2.55 seconds
Started	Jan 21 07:49:31 PM PST 24
Finished	Jan 21 07:49:39 PM PST 24
Peak memory	201936 kb
Host	smart-dfb7642a-8aae-4544-a924-2ddc5451cad4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2973269011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.2973269011
Directory	/workspace/10.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.283094109
Short name	T59
Test name
Test status
Simulation time	258998927 ps
CPU time	5.03 seconds
Started	Jan 21 07:49:26 PM PST 24
Finished	Jan 21 07:49:36 PM PST 24
Peak memory	201968 kb
Host	smart-0eb83e79-870e-40e9-9890-5c9271fe50e5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=283094109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.283094109
Directory	/workspace/7.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/default/1.usbdev_sec_cm.3995530938
Short name	T2
Test name
Test status
Simulation time	109875870 ps
CPU time	0.9 seconds
Started	Jan 21 12:35:51 PM PST 24
Finished	Jan 21 12:35:57 PM PST 24
Peak memory	220472 kb
Host	smart-96665d4a-f53d-4c8e-ba76-b7108464ff42
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3995530938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.3995530938
Directory	/workspace/1.usbdev_sec_cm/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_tl_errors.13587668
Short name	T90
Test name
Test status
Simulation time	176639911 ps
CPU time	2.11 seconds
Started	Jan 21 07:48:56 PM PST 24
Finished	Jan 21 07:49:00 PM PST 24
Peak memory	202288 kb
Host	smart-89ce2200-7a98-42dc-8122-ed26fce8c0f1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=13587668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.13587668
Directory	/workspace/1.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1425510421
Short name	T91
Test name
Test status
Simulation time	484832896 ps
CPU time	9.44 seconds
Started	Jan 21 07:48:57 PM PST 24
Finished	Jan 21 07:49:08 PM PST 24
Peak memory	202072 kb
Host	smart-0a750540-ff7b-4966-9864-53354ab77906
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425510421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.1425510421
Directory	/workspace/0.usbdev_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.2325138634
Short name	T24
Test name
Test status
Simulation time	48359242 ps
CPU time	0.79 seconds
Started	Jan 21 07:48:50 PM PST 24
Finished	Jan 21 07:48:52 PM PST 24
Peak memory	201788 kb
Host	smart-964236db-afa1-4965-890c-1242b7544407
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325138634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.2325138634
Directory	/workspace/0.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_rw.2192239634
Short name	T7
Test name
Test status
Simulation time	50438333 ps
CPU time	0.85 seconds
Started	Jan 21 07:48:54 PM PST 24
Finished	Jan 21 07:48:57 PM PST 24
Peak memory	201768 kb
Host	smart-9378b5c8-3256-48d3-be87-52b0fb3e0ff8
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192239634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.2192239634
Directory	/workspace/0.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_intr_test.4059415097
Short name	T67
Test name
Test status
Simulation time	26336110 ps
CPU time	0.64 seconds
Started	Jan 21 07:48:50 PM PST 24
Finished	Jan 21 07:48:53 PM PST 24
Peak memory	201128 kb
Host	smart-3998a579-7a5d-417c-a938-ae764bcfd65d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4059415097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.4059415097
Directory	/workspace/0.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.1573533561
Short name	T55
Test name
Test status
Simulation time	86703900 ps
CPU time	1.49 seconds
Started	Jan 21 07:48:50 PM PST 24
Finished	Jan 21 07:48:54 PM PST 24
Peak memory	202044 kb
Host	smart-798dfa7c-96ab-4942-ad6c-f636c00778d4
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1573533561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.1573533561
Directory	/workspace/0.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_mem_walk.2322055849
Short name	T12
Test name
Test status
Simulation time	245601884 ps
CPU time	2.64 seconds
Started	Jan 21 07:48:45 PM PST 24
Finished	Jan 21 07:48:50 PM PST 24
Peak memory	201964 kb
Host	smart-f9493a8f-4dd5-485c-b918-eee8adf36d26
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2322055849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.2322055849
Directory	/workspace/0.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.1908364518
Short name	T142
Test name
Test status
Simulation time	102835247 ps
CPU time	1.44 seconds
Started	Jan 21 07:48:51 PM PST 24
Finished	Jan 21 07:48:55 PM PST 24
Peak memory	202028 kb
Host	smart-c9a98c55-e1b6-4956-80df-b65696243ff1
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908364518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_c sr_outstanding.1908364518
Directory	/workspace/0.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_tl_errors.2192080197
Short name	T110
Test name
Test status
Simulation time	238451227 ps
CPU time	2.83 seconds
Started	Jan 21 07:48:50 PM PST 24
Finished	Jan 21 07:48:55 PM PST 24
Peak memory	202032 kb
Host	smart-7f44f32a-b715-4cba-b75d-91b105e8261a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2192080197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.2192080197
Directory	/workspace/0.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.374486467
Short name	T77
Test name
Test status
Simulation time	127768950 ps
CPU time	1.99 seconds
Started	Jan 21 07:49:06 PM PST 24
Finished	Jan 21 07:49:10 PM PST 24
Peak memory	201224 kb
Host	smart-f0d00770-bf71-49b9-8dc2-1c88da1d5fb9
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374486467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.374486467
Directory	/workspace/1.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.3237234628
Short name	T51
Test name
Test status
Simulation time	200719323 ps
CPU time	5.14 seconds
Started	Jan 21 07:48:58 PM PST 24
Finished	Jan 21 07:49:05 PM PST 24
Peak memory	201972 kb
Host	smart-86f3bc7e-49c9-422d-a6a8-ec29b386ceef
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237234628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.3237234628
Directory	/workspace/1.usbdev_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.3112146082
Short name	T140
Test name
Test status
Simulation time	34533384 ps
CPU time	1.38 seconds
Started	Jan 21 07:49:06 PM PST 24
Finished	Jan 21 07:49:09 PM PST 24
Peak memory	211232 kb
Host	smart-cad2a696-5d68-4c7c-8c31-c4ca10caf1bc
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112146082 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_mem_rw_with_rand_reset.3112146082
Directory	/workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_rw.2365153106
Short name	T52
Test name
Test status
Simulation time	51804347 ps
CPU time	0.87 seconds
Started	Jan 21 07:48:59 PM PST 24
Finished	Jan 21 07:49:01 PM PST 24
Peak memory	201748 kb
Host	smart-1108c356-3130-4534-89c6-45151b817443
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365153106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.2365153106
Directory	/workspace/1.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_intr_test.2253932708
Short name	T89
Test name
Test status
Simulation time	26216054 ps
CPU time	0.66 seconds
Started	Jan 21 07:49:00 PM PST 24
Finished	Jan 21 07:49:01 PM PST 24
Peak memory	201200 kb
Host	smart-aea2f932-ddc7-4b05-947b-46f690b5dce8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2253932708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.2253932708
Directory	/workspace/1.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.1792579914
Short name	T53
Test name
Test status
Simulation time	84548955 ps
CPU time	1.45 seconds
Started	Jan 21 07:48:59 PM PST 24
Finished	Jan 21 07:49:02 PM PST 24
Peak memory	201908 kb
Host	smart-b9d3141a-4f9f-4de3-bbfe-63bee4948a5c
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1792579914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.1792579914
Directory	/workspace/1.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_mem_walk.1279441170
Short name	T83
Test name
Test status
Simulation time	154710255 ps
CPU time	4.08 seconds
Started	Jan 21 07:48:54 PM PST 24
Finished	Jan 21 07:49:01 PM PST 24
Peak memory	202048 kb
Host	smart-447cf421-1778-48e6-8bbe-a53842241b4a
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1279441170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.1279441170
Directory	/workspace/1.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.917111883
Short name	T141
Test name
Test status
Simulation time	109917017 ps
CPU time	1.05 seconds
Started	Jan 21 07:49:02 PM PST 24
Finished	Jan 21 07:49:04 PM PST 24
Peak memory	201972 kb
Host	smart-be44d5fd-5a92-4066-915a-21df91fe44a4
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917111883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_cs r_outstanding.917111883
Directory	/workspace/1.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.1964596038
Short name	T30
Test name
Test status
Simulation time	336693638 ps
CPU time	3.26 seconds
Started	Jan 21 07:48:59 PM PST 24
Finished	Jan 21 07:49:04 PM PST 24
Peak memory	201904 kb
Host	smart-ee7c4731-1892-486c-a266-b4d2865362b7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1964596038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.1964596038
Directory	/workspace/1.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.3946142393
Short name	T96
Test name
Test status
Simulation time	51333245 ps
CPU time	1.31 seconds
Started	Jan 21 07:49:31 PM PST 24
Finished	Jan 21 07:49:38 PM PST 24
Peak memory	210296 kb
Host	smart-75606e88-d83e-41b5-b958-ba068f2396f0
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946142393 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_mem_rw_with_rand_reset.3946142393
Directory	/workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_csr_rw.2446914053
Short name	T100
Test name
Test status
Simulation time	66602259 ps
CPU time	0.91 seconds
Started	Jan 21 07:49:26 PM PST 24
Finished	Jan 21 07:49:31 PM PST 24
Peak memory	201872 kb
Host	smart-fe4b00ec-15db-4b5b-b61a-e0371a0a233a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446914053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.2446914053
Directory	/workspace/10.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_intr_test.1473295795
Short name	T137
Test name
Test status
Simulation time	21455541 ps
CPU time	0.65 seconds
Started	Jan 21 07:49:24 PM PST 24
Finished	Jan 21 07:49:31 PM PST 24
Peak memory	201156 kb
Host	smart-de5edcce-759b-4469-a625-5fb61cc91b6d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1473295795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.1473295795
Directory	/workspace/10.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2051263328
Short name	T93
Test name
Test status
Simulation time	167270109 ps
CPU time	1.69 seconds
Started	Jan 21 07:49:26 PM PST 24
Finished	Jan 21 07:49:32 PM PST 24
Peak memory	202028 kb
Host	smart-b7af74d9-7b65-4fff-9f5a-4fe426380940
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051263328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_ csr_outstanding.2051263328
Directory	/workspace/10.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_tl_errors.401333355
Short name	T127
Test name
Test status
Simulation time	63516961 ps
CPU time	2 seconds
Started	Jan 21 07:49:24 PM PST 24
Finished	Jan 21 07:49:33 PM PST 24
Peak memory	201604 kb
Host	smart-e9da47d4-58bd-4d3d-a749-2ef1acf67cd3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=401333355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.401333355
Directory	/workspace/10.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3228956243
Short name	T74
Test name
Test status
Simulation time	135418197 ps
CPU time	1.5 seconds
Started	Jan 21 07:49:33 PM PST 24
Finished	Jan 21 07:49:39 PM PST 24
Peak memory	210292 kb
Host	smart-26b0356c-eb07-4d99-ad48-aa3e5e3d1d22
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228956243 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_mem_rw_with_rand_reset.3228956243
Directory	/workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_csr_rw.962007707
Short name	T112
Test name
Test status
Simulation time	32900545 ps
CPU time	1 seconds
Started	Jan 21 07:49:27 PM PST 24
Finished	Jan 21 07:49:32 PM PST 24
Peak memory	202040 kb
Host	smart-42d859d7-301c-4f9d-9a15-7f302cfb27c2
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962007707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.962007707
Directory	/workspace/11.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_intr_test.3234307368
Short name	T40
Test name
Test status
Simulation time	50523273 ps
CPU time	0.66 seconds
Started	Jan 21 07:49:34 PM PST 24
Finished	Jan 21 07:49:38 PM PST 24
Peak memory	201120 kb
Host	smart-b8564a08-a9a4-47ff-bb03-0117eb5f365f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3234307368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.3234307368
Directory	/workspace/11.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.1504824653
Short name	T23
Test name
Test status
Simulation time	156280704 ps
CPU time	1.67 seconds
Started	Jan 21 07:49:27 PM PST 24
Finished	Jan 21 07:49:32 PM PST 24
Peak memory	202072 kb
Host	smart-d45e65e6-0ab5-4f65-b34a-462f6a02d52a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504824653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_ csr_outstanding.1504824653
Directory	/workspace/11.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_tl_errors.235138325
Short name	T31
Test name
Test status
Simulation time	190567581 ps
CPU time	2.58 seconds
Started	Jan 21 07:49:30 PM PST 24
Finished	Jan 21 07:49:39 PM PST 24
Peak memory	202088 kb
Host	smart-b8b1c4a7-b536-412e-8bb0-b4fd1229a911
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=235138325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.235138325
Directory	/workspace/11.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.4276526756
Short name	T149
Test name
Test status
Simulation time	31471002 ps
CPU time	1.19 seconds
Started	Jan 21 07:49:39 PM PST 24
Finished	Jan 21 07:49:41 PM PST 24
Peak memory	210544 kb
Host	smart-095b6a1e-ad60-43ee-b1af-48e3f70e581b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276526756 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_mem_rw_with_rand_reset.4276526756
Directory	/workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_csr_rw.2627732347
Short name	T130
Test name
Test status
Simulation time	70205989 ps
CPU time	0.99 seconds
Started	Jan 21 07:49:47 PM PST 24
Finished	Jan 21 07:49:52 PM PST 24
Peak memory	202100 kb
Host	smart-def869ea-6eaa-4d7a-bc8c-2632a7702c3a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627732347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.2627732347
Directory	/workspace/12.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3355990109
Short name	T86
Test name
Test status
Simulation time	168756219 ps
CPU time	1.58 seconds
Started	Jan 21 07:49:39 PM PST 24
Finished	Jan 21 07:49:43 PM PST 24
Peak memory	202216 kb
Host	smart-3aa150a3-fe6b-4c80-936a-9d45ba096a92
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355990109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_ csr_outstanding.3355990109
Directory	/workspace/12.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2520729608
Short name	T147
Test name
Test status
Simulation time	104770306 ps
CPU time	1.51 seconds
Started	Jan 21 07:49:30 PM PST 24
Finished	Jan 21 07:49:38 PM PST 24
Peak memory	202060 kb
Host	smart-23f25f1d-c6e1-45bf-b298-64c0eab1c521
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2520729608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.2520729608
Directory	/workspace/12.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.2064529866
Short name	T122
Test name
Test status
Simulation time	44152628 ps
CPU time	1.29 seconds
Started	Jan 21 07:49:36 PM PST 24
Finished	Jan 21 07:49:39 PM PST 24
Peak memory	210288 kb
Host	smart-42092512-0c9a-4c23-98be-5cf951b5061f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064529866 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_mem_rw_with_rand_reset.2064529866
Directory	/workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_csr_rw.2257682933
Short name	T87
Test name
Test status
Simulation time	41434961 ps
CPU time	0.89 seconds
Started	Jan 21 07:49:39 PM PST 24
Finished	Jan 21 07:49:41 PM PST 24
Peak memory	201860 kb
Host	smart-f74420d9-90f7-4cde-9ee3-156e1cfcabc7
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257682933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.2257682933
Directory	/workspace/13.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_intr_test.3579925809
Short name	T4
Test name
Test status
Simulation time	25873232 ps
CPU time	0.69 seconds
Started	Jan 21 07:49:41 PM PST 24
Finished	Jan 21 07:49:44 PM PST 24
Peak memory	201144 kb
Host	smart-d523e0f2-a507-4757-9221-6830b34e6264
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3579925809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.3579925809
Directory	/workspace/13.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.896087170
Short name	T146
Test name
Test status
Simulation time	116810509 ps
CPU time	1.65 seconds
Started	Jan 21 07:49:38 PM PST 24
Finished	Jan 21 07:49:41 PM PST 24
Peak memory	201980 kb
Host	smart-4d7900dc-752b-4ab5-a584-70e1285f756a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896087170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_c sr_outstanding.896087170
Directory	/workspace/13.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_tl_errors.2274358715
Short name	T115
Test name
Test status
Simulation time	200190633 ps
CPU time	2.8 seconds
Started	Jan 21 07:49:42 PM PST 24
Finished	Jan 21 07:49:46 PM PST 24
Peak memory	202076 kb
Host	smart-d58e7269-4268-488a-a969-c5e21ae5a071
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2274358715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.2274358715
Directory	/workspace/13.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.1800115614
Short name	T98
Test name
Test status
Simulation time	61351744 ps
CPU time	1.29 seconds
Started	Jan 21 07:49:45 PM PST 24
Finished	Jan 21 07:49:52 PM PST 24
Peak memory	210332 kb
Host	smart-acae98a0-1f0e-47e9-9ec0-0c96aebc049d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800115614 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_mem_rw_with_rand_reset.1800115614
Directory	/workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_csr_rw.2601025518
Short name	T79
Test name
Test status
Simulation time	33524158 ps
CPU time	0.96 seconds
Started	Jan 21 07:49:36 PM PST 24
Finished	Jan 21 07:49:39 PM PST 24
Peak memory	202040 kb
Host	smart-71bf4f0c-115d-4ca5-a5e8-1e3a69718ed6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601025518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.2601025518
Directory	/workspace/14.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.844308586
Short name	T133
Test name
Test status
Simulation time	70588936 ps
CPU time	1.08 seconds
Started	Jan 21 07:49:40 PM PST 24
Finished	Jan 21 07:49:43 PM PST 24
Peak memory	202032 kb
Host	smart-15951ed6-029c-456f-86e4-332b130c9e39
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844308586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_c sr_outstanding.844308586
Directory	/workspace/14.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_tl_errors.4077755004
Short name	T148
Test name
Test status
Simulation time	196109046 ps
CPU time	2.45 seconds
Started	Jan 21 07:49:38 PM PST 24
Finished	Jan 21 07:49:42 PM PST 24
Peak memory	202108 kb
Host	smart-583fbc6c-5410-4a21-a30a-dd91c4b83195
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4077755004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.4077755004
Directory	/workspace/14.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.4193007537
Short name	T32
Test name
Test status
Simulation time	422546485 ps
CPU time	4.76 seconds
Started	Jan 21 07:49:41 PM PST 24
Finished	Jan 21 07:49:48 PM PST 24
Peak memory	201964 kb
Host	smart-c5a3be3f-12a5-4a84-a5cf-40fadce6c5a3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=4193007537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.4193007537
Directory	/workspace/14.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.3350205930
Short name	T81
Test name
Test status
Simulation time	27329581 ps
CPU time	0.94 seconds
Started	Jan 21 07:49:53 PM PST 24
Finished	Jan 21 07:49:58 PM PST 24
Peak memory	202144 kb
Host	smart-93244e3a-3f7d-4b4a-b985-4335329ecb51
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350205930 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_mem_rw_with_rand_reset.3350205930
Directory	/workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_csr_rw.636600188
Short name	T54
Test name
Test status
Simulation time	26128274 ps
CPU time	0.84 seconds
Started	Jan 21 07:49:46 PM PST 24
Finished	Jan 21 07:49:52 PM PST 24
Peak memory	201816 kb
Host	smart-0af72d5a-5196-41e6-863f-4c922de74337
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636600188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.636600188
Directory	/workspace/15.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_intr_test.3141150618
Short name	T117
Test name
Test status
Simulation time	33087582 ps
CPU time	0.7 seconds
Started	Jan 21 07:49:45 PM PST 24
Finished	Jan 21 07:49:51 PM PST 24
Peak memory	201232 kb
Host	smart-ebfd3828-686f-4a47-8cd7-476e12e7c6f6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3141150618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.3141150618
Directory	/workspace/15.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3994496358
Short name	T20
Test name
Test status
Simulation time	80004468 ps
CPU time	1.06 seconds
Started	Jan 21 07:49:44 PM PST 24
Finished	Jan 21 07:49:52 PM PST 24
Peak memory	202028 kb
Host	smart-c7d24218-988b-4855-9caa-78a2cb3a27b2
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994496358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_ csr_outstanding.3994496358
Directory	/workspace/15.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_tl_errors.1569900047
Short name	T150
Test name
Test status
Simulation time	154988204 ps
CPU time	2.03 seconds
Started	Jan 21 07:49:40 PM PST 24
Finished	Jan 21 07:49:44 PM PST 24
Peak memory	202040 kb
Host	smart-62b659d5-d3ac-4ac0-9db0-dca98ca7b55e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1569900047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.1569900047
Directory	/workspace/15.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.571982356
Short name	T136
Test name
Test status
Simulation time	55511385 ps
CPU time	1.29 seconds
Started	Jan 21 07:49:47 PM PST 24
Finished	Jan 21 07:49:52 PM PST 24
Peak memory	210380 kb
Host	smart-2356d9cd-d039-4a57-947a-30c3ac30ab7c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571982356 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_mem_rw_with_rand_reset.571982356
Directory	/workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.4271823112
Short name	T78
Test name
Test status
Simulation time	70539622 ps
CPU time	1.45 seconds
Started	Jan 21 07:49:47 PM PST 24
Finished	Jan 21 07:49:52 PM PST 24
Peak memory	202044 kb
Host	smart-9ad12be0-6f1b-4445-97b6-dd93f1037f1e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271823112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_ csr_outstanding.4271823112
Directory	/workspace/16.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3245783100
Short name	T135
Test name
Test status
Simulation time	57592169 ps
CPU time	1.86 seconds
Started	Jan 21 07:49:45 PM PST 24
Finished	Jan 21 07:49:53 PM PST 24
Peak memory	202268 kb
Host	smart-ec424f8c-b297-476f-a86c-926bf577ecc2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3245783100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.3245783100
Directory	/workspace/16.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.2852350129
Short name	T118
Test name
Test status
Simulation time	29571001 ps
CPU time	1.22 seconds
Started	Jan 21 07:49:55 PM PST 24
Finished	Jan 21 07:49:59 PM PST 24
Peak memory	202108 kb
Host	smart-d1910e4b-6345-4173-8e9a-0dbb6ba3c42c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852350129 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_mem_rw_with_rand_reset.2852350129
Directory	/workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_csr_rw.4100354443
Short name	T37
Test name
Test status
Simulation time	34311017 ps
CPU time	0.82 seconds
Started	Jan 21 07:49:47 PM PST 24
Finished	Jan 21 07:49:52 PM PST 24
Peak memory	201848 kb
Host	smart-23377e63-2ffb-43d9-956d-a2e2bbcc9e89
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100354443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.4100354443
Directory	/workspace/17.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_intr_test.878263561
Short name	T132
Test name
Test status
Simulation time	23694329 ps
CPU time	0.63 seconds
Started	Jan 21 07:49:53 PM PST 24
Finished	Jan 21 07:49:58 PM PST 24
Peak memory	201152 kb
Host	smart-1817e884-42b4-430d-a6b3-b4f52aede12b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=878263561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.878263561
Directory	/workspace/17.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3759000760
Short name	T101
Test name
Test status
Simulation time	36851642 ps
CPU time	1 seconds
Started	Jan 21 07:49:55 PM PST 24
Finished	Jan 21 07:49:59 PM PST 24
Peak memory	202040 kb
Host	smart-3ed84d6d-07c0-4ac0-a86d-dfe902eec3a7
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759000760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_ csr_outstanding.3759000760
Directory	/workspace/17.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.4192088829
Short name	T58
Test name
Test status
Simulation time	185548890 ps
CPU time	2.57 seconds
Started	Jan 21 07:49:53 PM PST 24
Finished	Jan 21 07:49:59 PM PST 24
Peak memory	202068 kb
Host	smart-7f052a43-5b06-4ede-8c60-0c31f43e87a5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=4192088829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.4192088829
Directory	/workspace/17.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1367153204
Short name	T18
Test name
Test status
Simulation time	32064179 ps
CPU time	0.91 seconds
Started	Jan 21 08:53:40 PM PST 24
Finished	Jan 21 08:53:58 PM PST 24
Peak memory	202172 kb
Host	smart-091dad4a-3c31-4b4e-a652-fc9882210fdb
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367153204 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_mem_rw_with_rand_reset.1367153204
Directory	/workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_csr_rw.2335584774
Short name	T131
Test name
Test status
Simulation time	43600059 ps
CPU time	1.03 seconds
Started	Jan 21 07:49:55 PM PST 24
Finished	Jan 21 07:49:59 PM PST 24
Peak memory	202096 kb
Host	smart-65c54991-fa24-40e1-a133-51b4465261f2
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335584774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.2335584774
Directory	/workspace/18.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.3580342147
Short name	T143
Test name
Test status
Simulation time	62147288 ps
CPU time	1.76 seconds
Started	Jan 21 07:49:53 PM PST 24
Finished	Jan 21 07:49:59 PM PST 24
Peak memory	201992 kb
Host	smart-5d25080a-eaf4-4a1b-89eb-4d3c115db0ee
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580342147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_ csr_outstanding.3580342147
Directory	/workspace/18.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.1715102945
Short name	T111
Test name
Test status
Simulation time	354035110 ps
CPU time	4.37 seconds
Started	Jan 21 07:49:54 PM PST 24
Finished	Jan 21 07:50:01 PM PST 24
Peak memory	202008 kb
Host	smart-45cd5e3e-3a20-4ba3-bfc2-26c8280c9c8c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1715102945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.1715102945
Directory	/workspace/18.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2423797364
Short name	T106
Test name
Test status
Simulation time	52564667 ps
CPU time	1.5 seconds
Started	Jan 21 07:49:55 PM PST 24
Finished	Jan 21 07:49:59 PM PST 24
Peak memory	218472 kb
Host	smart-5615ce3d-075c-47cb-927b-85ffa5869e5a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423797364 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_mem_rw_with_rand_reset.2423797364
Directory	/workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_csr_rw.518659996
Short name	T50
Test name
Test status
Simulation time	52651685 ps
CPU time	0.84 seconds
Started	Jan 21 07:49:55 PM PST 24
Finished	Jan 21 07:49:59 PM PST 24
Peak memory	201836 kb
Host	smart-ca262d42-2bdd-4906-8ee7-bb97890204a4
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518659996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.518659996
Directory	/workspace/19.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_intr_test.1385633069
Short name	T70
Test name
Test status
Simulation time	24321142 ps
CPU time	0.66 seconds
Started	Jan 21 07:49:56 PM PST 24
Finished	Jan 21 07:49:59 PM PST 24
Peak memory	201164 kb
Host	smart-75f58638-e265-46f4-a48d-1e7b1fcd3348
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1385633069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.1385633069
Directory	/workspace/19.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.2536408877
Short name	T138
Test name
Test status
Simulation time	73989001 ps
CPU time	1.1 seconds
Started	Jan 21 07:49:59 PM PST 24
Finished	Jan 21 07:50:04 PM PST 24
Peak memory	201968 kb
Host	smart-4f66fea1-1f9e-4e72-ab76-6bf2f44cdf55
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536408877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_ csr_outstanding.2536408877
Directory	/workspace/19.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3586725976
Short name	T34
Test name
Test status
Simulation time	158502468 ps
CPU time	2.14 seconds
Started	Jan 21 08:56:00 PM PST 24
Finished	Jan 21 08:56:34 PM PST 24
Peak memory	202056 kb
Host	smart-a831a31b-a2e8-4cc6-840b-13b5bafd3e73
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3586725976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.3586725976
Directory	/workspace/19.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.545554762
Short name	T107
Test name
Test status
Simulation time	313431253 ps
CPU time	3.68 seconds
Started	Jan 21 07:49:03 PM PST 24
Finished	Jan 21 07:49:08 PM PST 24
Peak memory	201860 kb
Host	smart-246707f6-5994-44de-bc69-ed4bdf4a70a8
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545554762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.545554762
Directory	/workspace/2.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.891958338
Short name	T26
Test name
Test status
Simulation time	43241425 ps
CPU time	0.84 seconds
Started	Jan 21 07:48:56 PM PST 24
Finished	Jan 21 07:48:58 PM PST 24
Peak memory	201828 kb
Host	smart-cb77cb0e-1e69-4e3b-8115-702b94c39800
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891958338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.891958338
Directory	/workspace/2.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1295626777
Short name	T76
Test name
Test status
Simulation time	37023577 ps
CPU time	1.38 seconds
Started	Jan 21 07:49:07 PM PST 24
Finished	Jan 21 07:49:10 PM PST 24
Peak memory	210292 kb
Host	smart-5ecae370-afb5-4f2f-b66f-851b0a95ccb0
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295626777 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_mem_rw_with_rand_reset.1295626777
Directory	/workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_rw.1217510032
Short name	T38
Test name
Test status
Simulation time	50342896 ps
CPU time	0.9 seconds
Started	Jan 21 07:49:06 PM PST 24
Finished	Jan 21 07:49:08 PM PST 24
Peak memory	201860 kb
Host	smart-bebb1e7e-cdb5-4f7c-9f73-483751713698
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217510032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.1217510032
Directory	/workspace/2.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_intr_test.1664970248
Short name	T129
Test name
Test status
Simulation time	29383560 ps
CPU time	0.67 seconds
Started	Jan 21 07:49:06 PM PST 24
Finished	Jan 21 07:49:09 PM PST 24
Peak memory	199988 kb
Host	smart-df0c128d-0774-4a13-8e79-7d18e61c9788
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1664970248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.1664970248
Directory	/workspace/2.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.1555455620
Short name	T14
Test name
Test status
Simulation time	46212030 ps
CPU time	1.46 seconds
Started	Jan 21 07:48:55 PM PST 24
Finished	Jan 21 07:48:58 PM PST 24
Peak memory	202032 kb
Host	smart-fcd38540-07fd-4cba-802f-e06102c75fa7
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1555455620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.1555455620
Directory	/workspace/2.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_mem_walk.3874052894
Short name	T11
Test name
Test status
Simulation time	149326368 ps
CPU time	3.71 seconds
Started	Jan 21 07:48:57 PM PST 24
Finished	Jan 21 07:49:03 PM PST 24
Peak memory	202056 kb
Host	smart-663de7d2-2c4f-4687-b701-e6b4566c98b9
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3874052894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.3874052894
Directory	/workspace/2.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2990984752
Short name	T75
Test name
Test status
Simulation time	55099145 ps
CPU time	1.02 seconds
Started	Jan 21 07:49:03 PM PST 24
Finished	Jan 21 07:49:06 PM PST 24
Peak memory	202052 kb
Host	smart-60073461-9503-4160-8e6b-811dd4cdd8ed
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990984752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_c sr_outstanding.2990984752
Directory	/workspace/2.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_tl_errors.1695585266
Short name	T126
Test name
Test status
Simulation time	162745112 ps
CPU time	1.89 seconds
Started	Jan 21 07:48:58 PM PST 24
Finished	Jan 21 07:49:01 PM PST 24
Peak memory	202076 kb
Host	smart-1d519412-1519-4a4b-9f3a-55cd5c43b8ed
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1695585266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.1695585266
Directory	/workspace/2.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/22.usbdev_intr_test.3148268445
Short name	T85
Test name
Test status
Simulation time	35607028 ps
CPU time	0.69 seconds
Started	Jan 21 07:49:55 PM PST 24
Finished	Jan 21 07:49:58 PM PST 24
Peak memory	201152 kb
Host	smart-9b4ce396-1727-4fd2-816d-8c27dc801f81
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3148268445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.3148268445
Directory	/workspace/22.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.usbdev_intr_test.1856916337
Short name	T41
Test name
Test status
Simulation time	31691373 ps
CPU time	0.65 seconds
Started	Jan 21 07:57:32 PM PST 24
Finished	Jan 21 07:57:34 PM PST 24
Peak memory	201176 kb
Host	smart-79becbee-c1ff-4f0f-addc-74de924de5c8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1856916337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.1856916337
Directory	/workspace/24.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.usbdev_intr_test.572315195
Short name	T64
Test name
Test status
Simulation time	25583772 ps
CPU time	0.68 seconds
Started	Jan 21 07:49:55 PM PST 24
Finished	Jan 21 07:49:59 PM PST 24
Peak memory	201200 kb
Host	smart-b503732e-8f24-4ea7-9c93-298904d0db7f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=572315195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.572315195
Directory	/workspace/25.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.usbdev_intr_test.2982087122
Short name	T9
Test name
Test status
Simulation time	27895586 ps
CPU time	0.68 seconds
Started	Jan 21 07:50:08 PM PST 24
Finished	Jan 21 07:50:12 PM PST 24
Peak memory	200804 kb
Host	smart-771ce9ed-4c0a-42af-aa9d-8d23a6693547
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2982087122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.2982087122
Directory	/workspace/26.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.usbdev_intr_test.3291275219
Short name	T104
Test name
Test status
Simulation time	25795964 ps
CPU time	0.66 seconds
Started	Jan 21 08:50:09 PM PST 24
Finished	Jan 21 08:50:34 PM PST 24
Peak memory	201136 kb
Host	smart-06258780-2905-4db0-aaf8-b2c0a3372b02
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3291275219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.3291275219
Directory	/workspace/27.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.usbdev_intr_test.2187005058
Short name	T42
Test name
Test status
Simulation time	36342194 ps
CPU time	0.71 seconds
Started	Jan 21 07:49:55 PM PST 24
Finished	Jan 21 07:49:59 PM PST 24
Peak memory	201108 kb
Host	smart-72063f07-096a-4c2b-8b0c-9bcca71cb6c0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2187005058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.2187005058
Directory	/workspace/28.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.usbdev_intr_test.892499256
Short name	T109
Test name
Test status
Simulation time	21552396 ps
CPU time	0.66 seconds
Started	Jan 21 08:09:43 PM PST 24
Finished	Jan 21 08:09:45 PM PST 24
Peak memory	201268 kb
Host	smart-312b9a48-e029-4ba2-b0b9-a866f3b633eb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=892499256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.892499256
Directory	/workspace/29.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.2155454255
Short name	T49
Test name
Test status
Simulation time	321613079 ps
CPU time	3.58 seconds
Started	Jan 21 07:49:07 PM PST 24
Finished	Jan 21 07:49:13 PM PST 24
Peak memory	201948 kb
Host	smart-039ee602-8cbc-493b-af76-c920f7e5a5ab
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155454255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.2155454255
Directory	/workspace/3.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3456055926
Short name	T119
Test name
Test status
Simulation time	94222046 ps
CPU time	1.05 seconds
Started	Jan 21 07:49:02 PM PST 24
Finished	Jan 21 07:49:05 PM PST 24
Peak memory	202100 kb
Host	smart-6f2e4ed6-501f-46a7-80a1-f5dff567ac89
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456055926 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_mem_rw_with_rand_reset.3456055926
Directory	/workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_rw.536740547
Short name	T84
Test name
Test status
Simulation time	43583751 ps
CPU time	0.8 seconds
Started	Jan 21 07:49:02 PM PST 24
Finished	Jan 21 07:49:04 PM PST 24
Peak memory	201852 kb
Host	smart-1824ce0c-a7e9-4eba-b9b8-3f08858cbb98
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536740547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.536740547
Directory	/workspace/3.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.3078606700
Short name	T15
Test name
Test status
Simulation time	99106389 ps
CPU time	1.42 seconds
Started	Jan 21 07:49:06 PM PST 24
Finished	Jan 21 07:49:10 PM PST 24
Peak memory	202052 kb
Host	smart-3922fd27-32bb-47da-aad9-df083681f5f3
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3078606700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.3078606700
Directory	/workspace/3.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_mem_walk.328720530
Short name	T128
Test name
Test status
Simulation time	479372431 ps
CPU time	4.76 seconds
Started	Jan 21 07:49:01 PM PST 24
Finished	Jan 21 07:49:07 PM PST 24
Peak memory	201964 kb
Host	smart-ec0c79ce-7f3c-48ef-a439-3c29ae4fc240
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=328720530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.328720530
Directory	/workspace/3.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.2225601900
Short name	T44
Test name
Test status
Simulation time	43424102 ps
CPU time	0.95 seconds
Started	Jan 21 07:49:06 PM PST 24
Finished	Jan 21 07:49:09 PM PST 24
Peak memory	202028 kb
Host	smart-ed2af98a-f512-4a2a-9130-6eb0bc0aa2fc
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225601900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_c sr_outstanding.2225601900
Directory	/workspace/3.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_tl_errors.570206436
Short name	T46
Test name
Test status
Simulation time	261976508 ps
CPU time	3.39 seconds
Started	Jan 21 07:49:02 PM PST 24
Finished	Jan 21 07:49:06 PM PST 24
Peak memory	202232 kb
Host	smart-ddc18ba8-62cc-438d-95ff-1de2fc1c1901
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=570206436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.570206436
Directory	/workspace/3.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.2409799252
Short name	T60
Test name
Test status
Simulation time	136425027 ps
CPU time	2.39 seconds
Started	Jan 21 07:49:03 PM PST 24
Finished	Jan 21 07:49:08 PM PST 24
Peak memory	202008 kb
Host	smart-7d887c95-d95d-4810-ac91-b5266b8c66f7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2409799252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.2409799252
Directory	/workspace/3.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/32.usbdev_intr_test.351879099
Short name	T151
Test name
Test status
Simulation time	31017367 ps
CPU time	0.68 seconds
Started	Jan 21 07:49:55 PM PST 24
Finished	Jan 21 07:49:58 PM PST 24
Peak memory	201176 kb
Host	smart-91b5db2b-52b9-4405-8e15-96ad3695794f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=351879099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.351879099
Directory	/workspace/32.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.usbdev_intr_test.525744889
Short name	T8
Test name
Test status
Simulation time	30677648 ps
CPU time	0.65 seconds
Started	Jan 21 07:49:56 PM PST 24
Finished	Jan 21 07:49:59 PM PST 24
Peak memory	201192 kb
Host	smart-fe1ec852-03bd-448f-9ba6-083dce38cdd0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=525744889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.525744889
Directory	/workspace/35.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.usbdev_intr_test.1281541721
Short name	T99
Test name
Test status
Simulation time	42299241 ps
CPU time	0.7 seconds
Started	Jan 21 07:49:56 PM PST 24
Finished	Jan 21 07:50:00 PM PST 24
Peak memory	201164 kb
Host	smart-19fd546c-4ee7-44fc-891e-615355017795
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1281541721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.1281541721
Directory	/workspace/36.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.usbdev_intr_test.2237788298
Short name	T48
Test name
Test status
Simulation time	27291292 ps
CPU time	0.66 seconds
Started	Jan 21 07:50:02 PM PST 24
Finished	Jan 21 07:50:05 PM PST 24
Peak memory	201172 kb
Host	smart-25c6264d-4400-4be3-9bac-48a3b8da791a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2237788298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.2237788298
Directory	/workspace/37.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.usbdev_intr_test.2194262103
Short name	T125
Test name
Test status
Simulation time	31595479 ps
CPU time	0.74 seconds
Started	Jan 21 07:50:08 PM PST 24
Finished	Jan 21 07:50:12 PM PST 24
Peak memory	201144 kb
Host	smart-94489b81-96dc-49bc-b053-7bc8a0e8df6c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2194262103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.2194262103
Directory	/workspace/38.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.usbdev_intr_test.339960176
Short name	T47
Test name
Test status
Simulation time	22750353 ps
CPU time	0.67 seconds
Started	Jan 21 07:50:05 PM PST 24
Finished	Jan 21 07:50:08 PM PST 24
Peak memory	201140 kb
Host	smart-6ac8874a-0285-47d7-9715-ce7eb2bcfcb3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=339960176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.339960176
Directory	/workspace/39.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.3384218772
Short name	T123
Test name
Test status
Simulation time	307300771 ps
CPU time	3.52 seconds
Started	Jan 21 07:49:10 PM PST 24
Finished	Jan 21 07:49:16 PM PST 24
Peak memory	202080 kb
Host	smart-75dde233-6846-4541-94d7-ec319f2c49d4
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384218772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.3384218772
Directory	/workspace/4.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.586390147
Short name	T27
Test name
Test status
Simulation time	115106131 ps
CPU time	0.82 seconds
Started	Jan 21 07:49:05 PM PST 24
Finished	Jan 21 07:49:07 PM PST 24
Peak memory	201840 kb
Host	smart-14db40b9-49d5-4a05-a728-0119e623b30e
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586390147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.586390147
Directory	/workspace/4.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.3998961599
Short name	T134
Test name
Test status
Simulation time	30925674 ps
CPU time	0.97 seconds
Started	Jan 21 07:49:14 PM PST 24
Finished	Jan 21 07:49:16 PM PST 24
Peak memory	202128 kb
Host	smart-963c1d2f-3565-4c24-8939-974b49f820c4
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998961599 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_mem_rw_with_rand_reset.3998961599
Directory	/workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_intr_test.3421378746
Short name	T120
Test name
Test status
Simulation time	30720385 ps
CPU time	0.66 seconds
Started	Jan 21 07:49:02 PM PST 24
Finished	Jan 21 07:49:04 PM PST 24
Peak memory	201224 kb
Host	smart-6e1aa170-81b1-4681-83d7-82a677c204fd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3421378746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.3421378746
Directory	/workspace/4.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.3805585887
Short name	T105
Test name
Test status
Simulation time	196359098 ps
CPU time	2.35 seconds
Started	Jan 21 07:49:06 PM PST 24
Finished	Jan 21 07:49:11 PM PST 24
Peak memory	201996 kb
Host	smart-89637750-6f52-4148-8041-38fd7121fb4c
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3805585887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.3805585887
Directory	/workspace/4.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_mem_walk.3434180165
Short name	T88
Test name
Test status
Simulation time	199118779 ps
CPU time	4.04 seconds
Started	Jan 21 07:49:02 PM PST 24
Finished	Jan 21 07:49:08 PM PST 24
Peak memory	202048 kb
Host	smart-510be83d-e537-4664-89d4-0c1bc1cdc3b4
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3434180165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.3434180165
Directory	/workspace/4.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_tl_errors.989446806
Short name	T33
Test name
Test status
Simulation time	98930251 ps
CPU time	2.83 seconds
Started	Jan 21 07:49:07 PM PST 24
Finished	Jan 21 07:49:12 PM PST 24
Peak memory	202064 kb
Host	smart-b91f7471-8d73-4056-8c8f-65bfbdc08142
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=989446806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.989446806
Directory	/workspace/4.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/40.usbdev_intr_test.3765291810
Short name	T145
Test name
Test status
Simulation time	25608663 ps
CPU time	0.68 seconds
Started	Jan 21 07:50:01 PM PST 24
Finished	Jan 21 07:50:05 PM PST 24
Peak memory	201124 kb
Host	smart-de2dbf21-dad5-4c91-a6e6-b826838beea0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3765291810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.3765291810
Directory	/workspace/40.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.usbdev_intr_test.2535845584
Short name	T72
Test name
Test status
Simulation time	23264236 ps
CPU time	0.66 seconds
Started	Jan 21 07:50:04 PM PST 24
Finished	Jan 21 07:50:07 PM PST 24
Peak memory	201156 kb
Host	smart-0868d828-a49f-485e-a86a-e4d793d2d1f0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2535845584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.2535845584
Directory	/workspace/42.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.usbdev_intr_test.884914720
Short name	T116
Test name
Test status
Simulation time	36140233 ps
CPU time	0.68 seconds
Started	Jan 21 07:50:05 PM PST 24
Finished	Jan 21 07:50:08 PM PST 24
Peak memory	201232 kb
Host	smart-aa27c8cc-760f-4e8a-b266-f7827d06c66f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=884914720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.884914720
Directory	/workspace/43.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.usbdev_intr_test.2683476449
Short name	T68
Test name
Test status
Simulation time	27403803 ps
CPU time	0.68 seconds
Started	Jan 21 07:50:03 PM PST 24
Finished	Jan 21 07:50:06 PM PST 24
Peak memory	201172 kb
Host	smart-99688e44-aed1-448a-b53d-e9f305568c3b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2683476449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.2683476449
Directory	/workspace/44.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.usbdev_intr_test.1305416728
Short name	T19
Test name
Test status
Simulation time	21314843 ps
CPU time	0.65 seconds
Started	Jan 21 07:50:05 PM PST 24
Finished	Jan 21 07:50:09 PM PST 24
Peak memory	201148 kb
Host	smart-aeed4079-5e0a-404c-8b58-4def0aae7f6c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1305416728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.1305416728
Directory	/workspace/48.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.usbdev_intr_test.4292448236
Short name	T71
Test name
Test status
Simulation time	30844923 ps
CPU time	0.64 seconds
Started	Jan 21 07:50:04 PM PST 24
Finished	Jan 21 07:50:07 PM PST 24
Peak memory	201192 kb
Host	smart-267908e5-82d6-4adc-8ca7-2d0897359dfe
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4292448236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.4292448236
Directory	/workspace/49.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1176601863
Short name	T82
Test name
Test status
Simulation time	73053752 ps
CPU time	1.16 seconds
Started	Jan 21 07:49:24 PM PST 24
Finished	Jan 21 07:49:32 PM PST 24
Peak memory	202016 kb
Host	smart-2e14d70f-8f8f-46a4-8ca3-8dd8326b6782
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176601863 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_mem_rw_with_rand_reset.1176601863
Directory	/workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_csr_rw.617449365
Short name	T80
Test name
Test status
Simulation time	31676751 ps
CPU time	0.84 seconds
Started	Jan 21 07:49:09 PM PST 24
Finished	Jan 21 07:49:11 PM PST 24
Peak memory	201828 kb
Host	smart-eb87dbc0-c074-4082-a49b-14259efab934
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617449365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.617449365
Directory	/workspace/5.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_intr_test.1227854242
Short name	T113
Test name
Test status
Simulation time	57272287 ps
CPU time	0.65 seconds
Started	Jan 21 07:49:24 PM PST 24
Finished	Jan 21 07:49:31 PM PST 24
Peak memory	201236 kb
Host	smart-a3036130-46da-4a4f-99b0-b9634450be74
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1227854242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.1227854242
Directory	/workspace/5.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.2058994566
Short name	T56
Test name
Test status
Simulation time	57603518 ps
CPU time	1.52 seconds
Started	Jan 21 07:49:24 PM PST 24
Finished	Jan 21 07:49:32 PM PST 24
Peak memory	201996 kb
Host	smart-48e9bfdf-4a9f-4d17-8532-589c113196a0
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058994566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_c sr_outstanding.2058994566
Directory	/workspace/5.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_tl_errors.696395272
Short name	T16
Test name
Test status
Simulation time	166810023 ps
CPU time	2.05 seconds
Started	Jan 21 07:49:10 PM PST 24
Finished	Jan 21 07:49:15 PM PST 24
Peak memory	202120 kb
Host	smart-93600687-dc65-49ff-8299-7dc377d1888b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=696395272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.696395272
Directory	/workspace/5.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.2382282631
Short name	T103
Test name
Test status
Simulation time	277761061 ps
CPU time	2.64 seconds
Started	Jan 21 07:49:09 PM PST 24
Finished	Jan 21 07:49:15 PM PST 24
Peak memory	202016 kb
Host	smart-2aeb9d42-6272-4dd1-b350-cd0e450af28f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2382282631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.2382282631
Directory	/workspace/5.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.1344946434
Short name	T152
Test name
Test status
Simulation time	50087061 ps
CPU time	0.96 seconds
Started	Jan 21 07:49:21 PM PST 24
Finished	Jan 21 07:49:23 PM PST 24
Peak memory	217676 kb
Host	smart-fc8d90d3-9f2c-4528-b4ba-9bca195205c4
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344946434 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_mem_rw_with_rand_reset.1344946434
Directory	/workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_csr_rw.2783338420
Short name	T57
Test name
Test status
Simulation time	55283829 ps
CPU time	0.92 seconds
Started	Jan 21 07:49:24 PM PST 24
Finished	Jan 21 07:49:31 PM PST 24
Peak memory	201408 kb
Host	smart-845e9c2b-c871-41ef-b7a1-7010282fcf91
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783338420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.2783338420
Directory	/workspace/6.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3437736924
Short name	T102
Test name
Test status
Simulation time	139382469 ps
CPU time	1.56 seconds
Started	Jan 21 07:49:12 PM PST 24
Finished	Jan 21 07:49:15 PM PST 24
Peak memory	202084 kb
Host	smart-700ad60a-18e2-41aa-82b1-e324f19b2b2a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437736924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_c sr_outstanding.3437736924
Directory	/workspace/6.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1501427818
Short name	T45
Test name
Test status
Simulation time	104595195 ps
CPU time	1.48 seconds
Started	Jan 21 07:49:16 PM PST 24
Finished	Jan 21 07:49:19 PM PST 24
Peak memory	202120 kb
Host	smart-33dc8ba6-7381-4f41-8664-10341dd706be
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1501427818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.1501427818
Directory	/workspace/6.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.2601229418
Short name	T10
Test name
Test status
Simulation time	29940684 ps
CPU time	0.95 seconds
Started	Jan 21 07:49:29 PM PST 24
Finished	Jan 21 07:49:36 PM PST 24
Peak memory	202176 kb
Host	smart-0e4dfdb9-a773-4498-bc2b-b1979664a52a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601229418 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_mem_rw_with_rand_reset.2601229418
Directory	/workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_csr_rw.2435254635
Short name	T36
Test name
Test status
Simulation time	61393769 ps
CPU time	1.06 seconds
Started	Jan 21 07:49:30 PM PST 24
Finished	Jan 21 07:49:37 PM PST 24
Peak memory	202076 kb
Host	smart-c5c450ab-56ce-4256-af56-abfe37c04a40
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435254635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.2435254635
Directory	/workspace/7.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_intr_test.4043776043
Short name	T69
Test name
Test status
Simulation time	71252829 ps
CPU time	0.74 seconds
Started	Jan 21 07:49:25 PM PST 24
Finished	Jan 21 07:49:31 PM PST 24
Peak memory	201212 kb
Host	smart-2aea5352-5750-40e7-a5a4-e2453a98221b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4043776043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.4043776043
Directory	/workspace/7.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.3538452209
Short name	T94
Test name
Test status
Simulation time	60474013 ps
CPU time	1.56 seconds
Started	Jan 21 07:49:22 PM PST 24
Finished	Jan 21 07:49:29 PM PST 24
Peak memory	202016 kb
Host	smart-2f41b448-bd7c-4c15-882c-e4fab1180740
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538452209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_c sr_outstanding.3538452209
Directory	/workspace/7.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_tl_errors.1953218929
Short name	T35
Test name
Test status
Simulation time	116694893 ps
CPU time	1.53 seconds
Started	Jan 21 07:49:12 PM PST 24
Finished	Jan 21 07:49:15 PM PST 24
Peak memory	202144 kb
Host	smart-77e30be9-d935-4cdc-9d71-9ec35d4bd7e2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1953218929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.1953218929
Directory	/workspace/7.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.4280283151
Short name	T124
Test name
Test status
Simulation time	62759041 ps
CPU time	1.49 seconds
Started	Jan 21 07:49:26 PM PST 24
Finished	Jan 21 07:49:32 PM PST 24
Peak memory	202080 kb
Host	smart-fda33693-361f-4781-9d32-deb0ca031913
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280283151 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_mem_rw_with_rand_reset.4280283151
Directory	/workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2548807686
Short name	T139
Test name
Test status
Simulation time	59321325 ps
CPU time	1.06 seconds
Started	Jan 21 07:49:26 PM PST 24
Finished	Jan 21 07:49:32 PM PST 24
Peak memory	202068 kb
Host	smart-14f3c812-7795-4f78-a484-60874ddf5370
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548807686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.2548807686
Directory	/workspace/8.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_intr_test.4072309085
Short name	T97
Test name
Test status
Simulation time	25752837 ps
CPU time	0.65 seconds
Started	Jan 21 07:49:24 PM PST 24
Finished	Jan 21 07:49:31 PM PST 24
Peak memory	201236 kb
Host	smart-136c5480-ad1b-4805-ae0c-fc9dae9bb70a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4072309085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.4072309085
Directory	/workspace/8.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.762122135
Short name	T95
Test name
Test status
Simulation time	72970910 ps
CPU time	1.05 seconds
Started	Jan 21 07:49:26 PM PST 24
Finished	Jan 21 07:49:32 PM PST 24
Peak memory	202044 kb
Host	smart-05d8fe89-0ba6-4996-a983-5e64fe05813c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762122135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_cs r_outstanding.762122135
Directory	/workspace/8.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2513392368
Short name	T114
Test name
Test status
Simulation time	141482471 ps
CPU time	1.98 seconds
Started	Jan 21 07:49:22 PM PST 24
Finished	Jan 21 07:49:30 PM PST 24
Peak memory	202120 kb
Host	smart-c650ccf0-6335-4ee1-99c9-c2790946c470
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2513392368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.2513392368
Directory	/workspace/8.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.1131982792
Short name	T92
Test name
Test status
Simulation time	86542208 ps
CPU time	1.6 seconds
Started	Jan 21 07:49:24 PM PST 24
Finished	Jan 21 07:49:32 PM PST 24
Peak memory	210252 kb
Host	smart-c41774d9-9e8b-48d4-80d0-c38938a29bc6
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131982792 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_mem_rw_with_rand_reset.1131982792
Directory	/workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_csr_rw.3807558206
Short name	T39
Test name
Test status
Simulation time	69155640 ps
CPU time	1.02 seconds
Started	Jan 21 07:49:24 PM PST 24
Finished	Jan 21 07:49:32 PM PST 24
Peak memory	201844 kb
Host	smart-bb942362-8ab0-4923-b25b-aa76ef66f1e5
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807558206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.3807558206
Directory	/workspace/9.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_intr_test.3998760071
Short name	T66
Test name
Test status
Simulation time	18372505 ps
CPU time	0.65 seconds
Started	Jan 21 07:49:24 PM PST 24
Finished	Jan 21 07:49:31 PM PST 24
Peak memory	201240 kb
Host	smart-134ba2d5-5725-44d3-ba1d-91b3d0f423fd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3998760071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.3998760071
Directory	/workspace/9.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.1678287661
Short name	T144
Test name
Test status
Simulation time	73393162 ps
CPU time	1.21 seconds
Started	Jan 21 07:49:31 PM PST 24
Finished	Jan 21 07:49:38 PM PST 24
Peak memory	201996 kb
Host	smart-f8fea772-4f54-4888-aef3-f708127a90a3
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678287661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_c sr_outstanding.1678287661
Directory	/workspace/9.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.3220262165
Short name	T61
Test name
Test status
Simulation time	472564055 ps
CPU time	3.32 seconds
Started	Jan 21 07:49:27 PM PST 24
Finished	Jan 21 07:49:34 PM PST 24
Peak memory	202056 kb
Host	smart-1c85b914-8d20-4f8a-b770-9b0c82b4f334
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3220262165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.3220262165
Directory	/workspace/9.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/default/2.usbdev_sec_cm.3111403636
Short name	T3
Test name
Test status
Simulation time	175051871 ps
CPU time	1.08 seconds
Started	Jan 21 12:24:18 PM PST 24
Finished	Jan 21 12:24:21 PM PST 24
Peak memory	218956 kb
Host	smart-8e7de716-6180-4d90-8286-322da639babc
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3111403636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.3111403636
Directory	/workspace/2.usbdev_sec_cm/latest