Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=16}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=16}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=16}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	68	0	68	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=16}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	17	0	17	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=16}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	68	0	68	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	288	1		T4	5		T6	2		T8	5
all_pins[1]	288	1		T4	5		T6	2		T8	5
all_pins[2]	288	1		T4	5		T6	2		T8	5
all_pins[3]	288	1		T4	5		T6	2		T8	5
all_pins[4]	288	1		T4	5		T6	2		T8	5
all_pins[5]	288	1		T4	5		T6	2		T8	5
all_pins[6]	288	1		T4	5		T6	2		T8	5
all_pins[7]	288	1		T4	5		T6	2		T8	5
all_pins[8]	288	1		T4	5		T6	2		T8	5
all_pins[9]	288	1		T4	5		T6	2		T8	5
all_pins[10]	288	1		T4	5		T6	2		T8	5
all_pins[11]	288	1		T4	5		T6	2		T8	5
all_pins[12]	288	1		T4	5		T6	2		T8	5
all_pins[13]	288	1		T4	5		T6	2		T8	5
all_pins[14]	288	1		T4	5		T6	2		T8	5
all_pins[15]	288	1		T4	5		T6	2		T8	5
all_pins[16]	288	1		T4	5		T6	2		T8	5

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	4030	1		T4	57		T6	34		T8	70
values[0x1]	866	1		T4	28		T8	15		T9	22
transitions[0x0=>0x1]	648	1		T4	21		T8	10		T9	12
transitions[0x1=>0x0]	657	1		T4	21		T8	11		T9	12

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	68	0	68	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	230	1		T4	2		T6	2		T8	5
all_pins[0]	values[0x1]	58	1		T4	3		T9	3		T28	1
all_pins[0]	transitions[0x0=>0x1]	48	1		T4	3		T28	1		T29	3
all_pins[0]	transitions[0x1=>0x0]	33	1		T28	1		T19	2		T68	2
all_pins[1]	values[0x0]	245	1		T4	5		T6	2		T8	5
all_pins[1]	values[0x1]	43	1		T9	3		T28	1		T29	1
all_pins[1]	transitions[0x0=>0x1]	26	1		T9	1		T29	1		T68	2
all_pins[1]	transitions[0x1=>0x0]	49	1		T4	2		T8	2		T28	1
all_pins[2]	values[0x0]	222	1		T4	3		T6	2		T8	3
all_pins[2]	values[0x1]	66	1		T4	2		T8	2		T9	2
all_pins[2]	transitions[0x0=>0x1]	49	1		T8	1		T9	2		T28	2
all_pins[2]	transitions[0x1=>0x0]	33	1		T4	1		T28	1		T29	2
all_pins[3]	values[0x0]	238	1		T4	2		T6	2		T8	4
all_pins[3]	values[0x1]	50	1		T4	3		T8	1		T28	1
all_pins[3]	transitions[0x0=>0x1]	44	1		T4	3		T8	1		T28	1
all_pins[3]	transitions[0x1=>0x0]	35	1		T9	1		T28	2		T47	1
all_pins[4]	values[0x0]	247	1		T4	5		T6	2		T8	5
all_pins[4]	values[0x1]	41	1		T9	1		T28	2		T47	1
all_pins[4]	transitions[0x0=>0x1]	31	1		T28	2		T47	1		T48	2
all_pins[4]	transitions[0x1=>0x0]	55	1		T4	2		T8	1		T9	2
all_pins[5]	values[0x0]	223	1		T4	3		T6	2		T8	4
all_pins[5]	values[0x1]	65	1		T4	2		T8	1		T9	3
all_pins[5]	transitions[0x0=>0x1]	53	1		T4	2		T9	3		T29	2
all_pins[5]	transitions[0x1=>0x0]	32	1		T4	2		T28	1		T29	2
all_pins[6]	values[0x0]	244	1		T4	3		T6	2		T8	4
all_pins[6]	values[0x1]	44	1		T4	2		T8	1		T28	1
all_pins[6]	transitions[0x0=>0x1]	36	1		T4	2		T8	1		T28	1
all_pins[6]	transitions[0x1=>0x0]	33	1		T4	1		T28	1		T19	1
all_pins[7]	values[0x0]	247	1		T4	4		T6	2		T8	5
all_pins[7]	values[0x1]	41	1		T4	1		T28	1		T19	3
all_pins[7]	transitions[0x0=>0x1]	33	1		T4	1		T28	1		T19	2
all_pins[7]	transitions[0x1=>0x0]	42	1		T4	1		T8	2		T28	1
all_pins[8]	values[0x0]	238	1		T4	4		T6	2		T8	3
all_pins[8]	values[0x1]	50	1		T4	1		T8	2		T28	1
all_pins[8]	transitions[0x0=>0x1]	35	1		T4	1		T8	2		T29	3
all_pins[8]	transitions[0x1=>0x0]	34	1		T9	2		T28	2		T47	1
all_pins[9]	values[0x0]	239	1		T4	5		T6	2		T8	5
all_pins[9]	values[0x1]	49	1		T9	2		T28	3		T47	2
all_pins[9]	transitions[0x0=>0x1]	37	1		T28	3		T47	2		T42	3
all_pins[9]	transitions[0x1=>0x0]	40	1		T4	2		T8	1		T28	2
all_pins[10]	values[0x0]	236	1		T4	3		T6	2		T8	4
all_pins[10]	values[0x1]	52	1		T4	2		T8	1		T9	2
all_pins[10]	transitions[0x0=>0x1]	36	1		T4	1		T8	1		T28	1
all_pins[10]	transitions[0x1=>0x0]	36	1		T4	2		T29	2		T19	3
all_pins[11]	values[0x0]	236	1		T4	2		T6	2		T8	5
all_pins[11]	values[0x1]	52	1		T4	3		T9	2		T28	1
all_pins[11]	transitions[0x0=>0x1]	40	1		T4	2		T9	2		T28	1
all_pins[11]	transitions[0x1=>0x0]	30	1		T8	1		T28	1		T29	2
all_pins[12]	values[0x0]	246	1		T4	4		T6	2		T8	4
all_pins[12]	values[0x1]	42	1		T4	1		T8	1		T28	1
all_pins[12]	transitions[0x0=>0x1]	29	1		T4	1		T8	1		T29	2
all_pins[12]	transitions[0x1=>0x0]	35	1		T4	1		T9	2		T19	1
all_pins[13]	values[0x0]	240	1		T4	4		T6	2		T8	5
all_pins[13]	values[0x1]	48	1		T4	1		T9	2		T28	1
all_pins[13]	transitions[0x0=>0x1]	36	1		T4	1		T9	2		T29	2
all_pins[13]	transitions[0x1=>0x0]	45	1		T4	2		T28	2		T29	1
all_pins[14]	values[0x0]	231	1		T4	3		T6	2		T8	5
all_pins[14]	values[0x1]	57	1		T4	2		T28	3		T29	1
all_pins[14]	transitions[0x0=>0x1]	40	1		T28	3		T29	1		T47	1
all_pins[14]	transitions[0x1=>0x0]	43	1		T4	2		T8	3		T9	2
all_pins[15]	values[0x0]	228	1		T4	1		T6	2		T8	2
all_pins[15]	values[0x1]	60	1		T4	4		T8	3		T9	2
all_pins[15]	transitions[0x0=>0x1]	45	1		T4	3		T8	1		T9	2
all_pins[15]	transitions[0x1=>0x0]	33	1		T8	1		T28	2		T29	1
all_pins[16]	values[0x0]	240	1		T4	4		T6	2		T8	2
all_pins[16]	values[0x1]	48	1		T4	1		T8	3		T28	3
all_pins[16]	transitions[0x0=>0x1]	30	1		T4	1		T8	2		T28	3
all_pins[16]	transitions[0x1=>0x0]	49	1		T4	3		T9	3		T28	1