Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=16}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=16}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=16}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	23	0	23	100.00
Crosses	102	0	102	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=16}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	17	0	17	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=16}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	102	0	102	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	212	1		T4	4		T8	4		T9	4
all_values[1]	212	1		T4	4		T8	4		T9	4
all_values[2]	212	1		T4	4		T8	4		T9	4
all_values[3]	212	1		T4	4		T8	4		T9	4
all_values[4]	212	1		T4	4		T8	4		T9	4
all_values[5]	212	1		T4	4		T8	4		T9	4
all_values[6]	212	1		T4	4		T8	4		T9	4
all_values[7]	212	1		T4	4		T8	4		T9	4
all_values[8]	212	1		T4	4		T8	4		T9	4
all_values[9]	212	1		T4	4		T8	4		T9	4
all_values[10]	212	1		T4	4		T8	4		T9	4
all_values[11]	212	1		T4	4		T8	4		T9	4
all_values[12]	212	1		T4	4		T8	4		T9	4
all_values[13]	212	1		T4	4		T8	4		T9	4
all_values[14]	212	1		T4	4		T8	4		T9	4
all_values[15]	212	1		T4	4		T8	4		T9	4
all_values[16]	212	1		T4	4		T8	4		T9	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1984	1		T4	33		T8	40		T9	40
auto[1]	1620	1		T4	35		T8	28		T9	28

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	624	1		T4	10		T8	13		T9	13
auto[1]	2980	1		T4	58		T8	55		T9	55

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2098	1		T4	44		T8	42		T9	38
auto[1]	1506	1		T4	24		T8	26		T9	30

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	102	0	102	100.00
Automatically Generated Cross Bins	102	0	102	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	24	1		T8	1		T9	1		T28	2
all_values[0]	auto[0]	auto[0]	auto[1]	41	1		T4	1		T47	2		T48	2
all_values[0]	auto[0]	auto[1]	auto[0]	5	1		T8	1		T28	1		T64	1
all_values[0]	auto[0]	auto[1]	auto[1]	52	1		T4	1		T8	1		T9	1
all_values[0]	auto[1]	auto[0]	auto[1]	49	1		T4	1		T9	1		T29	2
all_values[0]	auto[1]	auto[1]	auto[1]	41	1		T4	1		T8	1		T9	1
all_values[1]	auto[0]	auto[0]	auto[0]	21	1		T4	2		T19	1		T48	1
all_values[1]	auto[0]	auto[0]	auto[1]	38	1		T28	2		T47	1		T48	1
all_values[1]	auto[0]	auto[1]	auto[0]	23	1		T4	2		T9	1		T29	2
all_values[1]	auto[0]	auto[1]	auto[1]	50	1		T8	3		T9	1		T29	2
all_values[1]	auto[1]	auto[0]	auto[1]	48	1		T8	1		T28	3		T29	2
all_values[1]	auto[1]	auto[1]	auto[1]	32	1		T9	2		T28	2		T29	1
all_values[2]	auto[0]	auto[0]	auto[0]	25	1		T4	2		T9	2		T28	1
all_values[2]	auto[0]	auto[0]	auto[1]	44	1		T8	1		T28	2		T19	1
all_values[2]	auto[0]	auto[1]	auto[0]	14	1		T29	3		T40	2		T41	1
all_values[2]	auto[0]	auto[1]	auto[1]	35	1		T4	1		T8	1		T9	1
all_values[2]	auto[1]	auto[0]	auto[1]	47	1		T8	1		T9	1		T28	2
all_values[2]	auto[1]	auto[1]	auto[1]	47	1		T4	1		T8	1		T28	2
all_values[3]	auto[0]	auto[0]	auto[0]	21	1		T8	1		T28	2		T19	1
all_values[3]	auto[0]	auto[0]	auto[1]	55	1		T4	1		T8	1		T9	2
all_values[3]	auto[0]	auto[1]	auto[0]	12	1		T41	1		T65	1		T67	1
all_values[3]	auto[0]	auto[1]	auto[1]	44	1		T4	2		T28	2		T29	2
all_values[3]	auto[1]	auto[0]	auto[1]	42	1		T4	1		T8	1		T9	1
all_values[3]	auto[1]	auto[1]	auto[1]	38	1		T8	1		T9	1		T28	2
all_values[4]	auto[0]	auto[0]	auto[0]	37	1		T8	2		T28	3		T29	2
all_values[4]	auto[0]	auto[0]	auto[1]	33	1		T4	2		T48	1		T41	1
all_values[4]	auto[0]	auto[1]	auto[0]	15	1		T28	2		T29	1		T40	2
all_values[4]	auto[0]	auto[1]	auto[1]	45	1		T8	1		T9	2		T28	1
all_values[4]	auto[1]	auto[0]	auto[1]	49	1		T4	2		T29	2		T47	1
all_values[4]	auto[1]	auto[1]	auto[1]	33	1		T8	1		T9	2		T28	1
all_values[5]	auto[0]	auto[0]	auto[0]	19	1		T28	1		T19	1		T48	1
all_values[5]	auto[0]	auto[0]	auto[1]	37	1		T4	1		T28	4		T29	1
all_values[5]	auto[0]	auto[1]	auto[0]	8	1		T19	3		T41	1		T69	2
all_values[5]	auto[0]	auto[1]	auto[1]	58	1		T4	2		T8	2		T9	1
all_values[5]	auto[1]	auto[0]	auto[1]	46	1		T8	2		T9	2		T28	1
all_values[5]	auto[1]	auto[1]	auto[1]	44	1		T4	1		T9	1		T47	2
all_values[6]	auto[0]	auto[0]	auto[0]	26	1		T4	2		T28	1		T47	1
all_values[6]	auto[0]	auto[0]	auto[1]	46	1		T28	1		T29	1		T47	2
all_values[6]	auto[0]	auto[1]	auto[0]	16	1		T28	3		T29	3		T40	1
all_values[6]	auto[0]	auto[1]	auto[1]	44	1		T4	1		T8	2		T9	2
all_values[6]	auto[1]	auto[0]	auto[1]	51	1		T8	2		T9	2		T29	1
all_values[6]	auto[1]	auto[1]	auto[1]	29	1		T4	1		T28	2		T29	1
all_values[7]	auto[0]	auto[0]	auto[0]	23	1		T9	1		T28	1		T48	1
all_values[7]	auto[0]	auto[0]	auto[1]	47	1		T4	1		T8	3		T9	1
all_values[7]	auto[0]	auto[1]	auto[0]	11	1		T40	2		T70	1		T71	1
all_values[7]	auto[0]	auto[1]	auto[1]	39	1		T4	2		T9	1		T28	1
all_values[7]	auto[1]	auto[0]	auto[1]	52	1		T4	1		T8	1		T9	1
all_values[7]	auto[1]	auto[1]	auto[1]	40	1		T28	2		T19	1		T47	1
all_values[8]	auto[0]	auto[0]	auto[0]	28	1		T8	1		T28	2		T19	1
all_values[8]	auto[0]	auto[0]	auto[1]	47	1		T4	1		T9	2		T28	1
all_values[8]	auto[0]	auto[1]	auto[0]	20	1		T28	2		T70	2		T67	3
all_values[8]	auto[0]	auto[1]	auto[1]	37	1		T4	1		T8	1		T28	1
all_values[8]	auto[1]	auto[0]	auto[1]	38	1		T4	1		T8	2		T9	2
all_values[8]	auto[1]	auto[1]	auto[1]	42	1		T4	1		T28	1		T29	1
all_values[9]	auto[0]	auto[0]	auto[0]	28	1		T8	1		T48	2		T40	2
all_values[9]	auto[0]	auto[0]	auto[1]	45	1		T4	2		T8	1		T9	1
all_values[9]	auto[0]	auto[1]	auto[0]	8	1		T29	1		T48	2		T72	2
all_values[9]	auto[0]	auto[1]	auto[1]	41	1		T4	1		T8	1		T9	1
all_values[9]	auto[1]	auto[0]	auto[1]	55	1		T4	1		T9	2		T28	3
all_values[9]	auto[1]	auto[1]	auto[1]	35	1		T8	1		T47	2		T40	1
all_values[10]	auto[0]	auto[0]	auto[0]	23	1		T28	1		T66	1		T65	2
all_values[10]	auto[0]	auto[0]	auto[1]	35	1		T4	1		T28	2		T29	1
all_values[10]	auto[0]	auto[1]	auto[0]	10	1		T29	2		T65	2		T72	2
all_values[10]	auto[0]	auto[1]	auto[1]	47	1		T4	2		T8	2		T9	1
all_values[10]	auto[1]	auto[0]	auto[1]	54	1		T8	1		T9	2		T28	1
all_values[10]	auto[1]	auto[1]	auto[1]	43	1		T4	1		T8	1		T9	1
all_values[11]	auto[0]	auto[0]	auto[0]	27	1		T8	1		T9	2		T19	1
all_values[11]	auto[0]	auto[0]	auto[1]	37	1		T8	1		T29	2		T48	1
all_values[11]	auto[0]	auto[1]	auto[0]	11	1		T72	1		T73	1		T69	1
all_values[11]	auto[0]	auto[1]	auto[1]	40	1		T4	2		T9	1		T28	3
all_values[11]	auto[1]	auto[0]	auto[1]	46	1		T4	1		T8	2		T9	1
all_values[11]	auto[1]	auto[1]	auto[1]	51	1		T4	1		T28	3		T29	5
all_values[12]	auto[0]	auto[0]	auto[0]	23	1		T8	1		T28	2		T40	1
all_values[12]	auto[0]	auto[0]	auto[1]	37	1		T4	1		T8	1		T9	2
all_values[12]	auto[0]	auto[1]	auto[0]	12	1		T28	1		T65	1		T67	1
all_values[12]	auto[0]	auto[1]	auto[1]	51	1		T4	2		T28	1		T29	2
all_values[12]	auto[1]	auto[0]	auto[1]	50	1		T8	1		T9	2		T28	2
all_values[12]	auto[1]	auto[1]	auto[1]	39	1		T4	1		T8	1		T28	1
all_values[13]	auto[0]	auto[0]	auto[0]	30	1		T4	1		T28	1		T29	2
all_values[13]	auto[0]	auto[0]	auto[1]	38	1		T4	1		T8	1		T28	2
all_values[13]	auto[0]	auto[1]	auto[0]	9	1		T9	1		T29	3		T40	1
all_values[13]	auto[0]	auto[1]	auto[1]	54	1		T8	2		T9	1		T28	1
all_values[13]	auto[1]	auto[0]	auto[1]	46	1		T4	1		T8	1		T9	1
all_values[13]	auto[1]	auto[1]	auto[1]	35	1		T4	1		T9	1		T29	1
all_values[14]	auto[0]	auto[0]	auto[0]	31	1		T8	4		T9	3		T28	2
all_values[14]	auto[0]	auto[0]	auto[1]	46	1		T29	2		T19	2		T47	1
all_values[14]	auto[0]	auto[1]	auto[0]	6	1		T9	1		T28	1		T42	1
all_values[14]	auto[0]	auto[1]	auto[1]	32	1		T4	1		T28	1		T40	2
all_values[14]	auto[1]	auto[0]	auto[1]	56	1		T4	2		T28	1		T29	4
all_values[14]	auto[1]	auto[1]	auto[1]	41	1		T4	1		T28	2		T29	1
all_values[15]	auto[0]	auto[0]	auto[0]	16	1		T29	2		T19	1		T47	1
all_values[15]	auto[0]	auto[0]	auto[1]	55	1		T9	1		T28	2		T29	2
all_values[15]	auto[0]	auto[1]	auto[0]	5	1		T29	1		T68	1		T67	1
all_values[15]	auto[0]	auto[1]	auto[1]	35	1		T4	2		T8	1		T9	1
all_values[15]	auto[1]	auto[0]	auto[1]	56	1		T8	2		T9	2		T28	2
all_values[15]	auto[1]	auto[1]	auto[1]	45	1		T4	2		T8	1		T28	3
all_values[16]	auto[0]	auto[0]	auto[0]	24	1		T4	1		T28	1		T19	2
all_values[16]	auto[0]	auto[0]	auto[1]	45	1		T4	1		T8	1		T9	2
all_values[16]	auto[0]	auto[1]	auto[0]	13	1		T9	1		T40	2		T41	1
all_values[16]	auto[0]	auto[1]	auto[1]	44	1		T4	1		T8	2		T28	3
all_values[16]	auto[1]	auto[0]	auto[1]	47	1		T4	1		T8	1		T28	1
all_values[16]	auto[1]	auto[1]	auto[1]	39	1		T9	1		T28	2		T29	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal