Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	38184	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	48489	1		T1	2		T2	1		T3	3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	51634	1		T1	2		T2	2		T3	2
values[0x0]	17135	1		T3	1		T5	1		T6	50
values[0x1]	17904	1		T1	1		T2	1		T4	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26486	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	60187	1		T1	2		T2	2		T3	3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	246	1		T20	1		T21	14		T12	1
valid_sources[0x01]	357	1		T10	11		T20	5		T21	7
valid_sources[0x02]	269	1		T6	1		T7	1		T10	32
valid_sources[0x03]	273	1		T20	34		T21	3		T28	17
valid_sources[0x04]	219	1		T6	1		T9	1		T20	1
valid_sources[0x05]	237	1		T20	7		T12	1		T22	4
valid_sources[0x06]	452	1		T6	1		T7	6		T22	6
valid_sources[0x07]	331	1		T6	1		T7	1		T9	1
valid_sources[0x08]	639	1		T7	1		T20	3		T24	1
valid_sources[0x09]	510	1		T6	2		T7	1		T10	26
valid_sources[0x0a]	271	1		T10	15		T20	30		T27	11
valid_sources[0x0b]	482	1		T6	1		T12	3		T29	2
valid_sources[0x0c]	311	1		T21	1		T12	1		T22	4
valid_sources[0x0d]	296	1		T12	14		T22	6		T49	3
valid_sources[0x0e]	378	1		T6	2		T20	4		T21	1
valid_sources[0x0f]	205	1		T6	1		T10	5		T21	2
valid_sources[0x10]	346	1		T7	2		T10	7		T20	8
valid_sources[0x11]	231	1		T7	1		T9	1		T12	8
valid_sources[0x12]	222	1		T20	2		T12	8		T29	4
valid_sources[0x13]	254	1		T6	1		T7	1		T21	1
valid_sources[0x14]	198	1		T21	2		T12	6		T25	3
valid_sources[0x15]	311	1		T20	3		T12	4		T29	1
valid_sources[0x16]	234	1		T7	1		T21	1		T12	9
valid_sources[0x17]	226	1		T6	3		T10	3		T20	2
valid_sources[0x18]	351	1		T6	1		T28	8		T12	2
valid_sources[0x19]	301	1		T7	1		T29	1		T22	6
valid_sources[0x1a]	399	1		T6	1		T10	10		T12	1
valid_sources[0x1b]	294	1		T7	1		T21	1		T12	1
valid_sources[0x1c]	322	1		T6	2		T10	10		T12	6
valid_sources[0x1d]	380	1		T7	1		T9	1		T10	33
valid_sources[0x1e]	401	1		T28	4		T12	4		T29	3
valid_sources[0x1f]	300	1		T6	2		T20	9		T12	1
valid_sources[0x20]	260	1		T6	2		T7	2		T10	6
valid_sources[0x21]	503	1		T7	1		T27	10		T28	2
valid_sources[0x22]	269	1		T6	1		T10	15		T21	1
valid_sources[0x23]	345	1		T7	1		T10	17		T29	1
valid_sources[0x24]	312	1		T7	1		T10	21		T12	6
valid_sources[0x25]	347	1		T7	1		T20	5		T27	1
valid_sources[0x26]	307	1		T6	2		T7	1		T20	2
valid_sources[0x27]	213	1		T10	2		T20	17		T21	6
valid_sources[0x28]	234	1		T7	1		T10	27		T20	8
valid_sources[0x29]	277	1		T20	9		T12	15		T29	2
valid_sources[0x2a]	282	1		T7	2		T12	10		T29	1
valid_sources[0x2b]	322	1		T7	1		T21	2		T28	1
valid_sources[0x2c]	240	1		T12	4		T29	2		T30	10
valid_sources[0x2d]	277	1		T7	1		T9	1		T20	1
valid_sources[0x2e]	581	1		T6	5		T10	15		T21	2
valid_sources[0x2f]	311	1		T20	1		T21	1		T28	1
valid_sources[0x30]	280	1		T6	1		T7	1		T20	23
valid_sources[0x31]	248	1		T6	1		T7	2		T21	1
valid_sources[0x32]	307	1		T7	2		T21	5		T27	1
valid_sources[0x33]	356	1		T9	1		T10	7		T25	1
valid_sources[0x34]	349	1		T7	1		T28	5		T12	4
valid_sources[0x35]	501	1		T9	2		T12	9		T29	1
valid_sources[0x36]	214	1		T7	1		T20	8		T12	5
valid_sources[0x37]	278	1		T27	17		T12	5		T29	4
valid_sources[0x38]	278	1		T6	1		T21	1		T22	3
valid_sources[0x39]	392	1		T6	1		T21	3		T27	4
valid_sources[0x3a]	216	1		T6	1		T9	1		T12	6
valid_sources[0x3b]	408	1		T6	1		T7	1		T12	5
valid_sources[0x3c]	309	1		T20	2		T12	15		T29	1
valid_sources[0x3d]	366	1		T6	1		T21	4		T12	6
valid_sources[0x3e]	389	1		T21	2		T12	1		T29	1
valid_sources[0x3f]	406	1		T6	2		T21	5		T12	4
valid_sources[0x40]	429	1		T7	2		T21	1		T29	1
valid_sources[0x41]	297	1		T6	1		T20	9		T21	7
valid_sources[0x42]	344	1		T6	1		T7	1		T9	1
valid_sources[0x43]	378	1		T7	1		T9	1		T10	9
valid_sources[0x44]	357	1		T27	11		T12	5		T29	3
valid_sources[0x45]	233	1		T10	5		T21	4		T28	1
valid_sources[0x46]	309	1		T7	1		T20	4		T21	4
valid_sources[0x47]	325	1		T7	1		T29	2		T22	6
valid_sources[0x48]	427	1		T7	1		T20	2		T29	1
valid_sources[0x49]	480	1		T6	2		T20	11		T21	6
valid_sources[0x4a]	266	1		T10	42		T20	1		T11	16
valid_sources[0x4b]	302	1		T10	15		T20	5		T21	10
valid_sources[0x4c]	250	1		T28	4		T12	6		T29	1
valid_sources[0x4d]	186	1		T20	1		T12	1		T29	2
valid_sources[0x4e]	287	1		T6	1		T20	6		T28	1
valid_sources[0x4f]	676	1		T9	1		T21	5		T22	5
valid_sources[0x50]	293	1		T6	1		T20	7		T12	4
valid_sources[0x51]	415	1		T6	1		T10	17		T28	7
valid_sources[0x52]	292	1		T7	1		T10	2		T20	1
valid_sources[0x53]	202	1		T7	1		T10	2		T20	1
valid_sources[0x54]	358	1		T20	3		T21	6		T12	8
valid_sources[0x55]	248	1		T7	2		T9	1		T10	6
valid_sources[0x56]	287	1		T6	3		T7	1		T29	2
valid_sources[0x57]	329	1		T21	4		T28	13		T29	5
valid_sources[0x58]	378	1		T1	3		T6	1		T7	1
valid_sources[0x59]	281	1		T9	1		T21	7		T27	4
valid_sources[0x5a]	332	1		T6	1		T20	6		T21	3
valid_sources[0x5b]	399	1		T21	1		T29	1		T22	8
valid_sources[0x5c]	277	1		T6	3		T7	1		T12	19
valid_sources[0x5d]	329	1		T10	3		T20	7		T28	11
valid_sources[0x5e]	307	1		T4	3		T20	10		T21	7
valid_sources[0x5f]	203	1		T21	1		T29	3		T22	6
valid_sources[0x60]	304	1		T7	1		T21	2		T22	11
valid_sources[0x61]	288	1		T21	3		T12	4		T29	1
valid_sources[0x62]	247	1		T9	1		T10	2		T20	1
valid_sources[0x63]	315	1		T6	2		T7	1		T20	14
valid_sources[0x64]	414	1		T7	2		T20	20		T28	2
valid_sources[0x65]	471	1		T7	1		T20	3		T66	2
valid_sources[0x66]	304	1		T6	1		T7	1		T20	6
valid_sources[0x67]	264	1		T20	6		T22	9		T49	4
valid_sources[0x68]	382	1		T6	1		T7	2		T9	1
valid_sources[0x69]	393	1		T7	2		T22	2		T49	4
valid_sources[0x6a]	346	1		T7	1		T9	3		T12	1
valid_sources[0x6b]	232	1		T21	6		T12	2		T29	4
valid_sources[0x6c]	302	1		T7	1		T10	12		T20	7
valid_sources[0x6d]	353	1		T6	1		T20	1		T21	1
valid_sources[0x6e]	303	1		T22	9		T49	7		T13	6
valid_sources[0x6f]	273	1		T9	1		T12	1		T22	4
valid_sources[0x70]	337	1		T6	2		T27	2		T12	1
valid_sources[0x71]	272	1		T6	1		T7	1		T21	6
valid_sources[0x72]	452	1		T21	13		T12	2		T29	1
valid_sources[0x73]	231	1		T6	1		T20	14		T12	3
valid_sources[0x74]	256	1		T7	1		T21	1		T22	3
valid_sources[0x75]	370	1		T12	4		T25	1		T22	9
valid_sources[0x76]	291	1		T5	2		T7	4		T12	2
valid_sources[0x77]	378	1		T12	11		T29	2		T22	2
valid_sources[0x78]	461	1		T10	23		T21	2		T12	3
valid_sources[0x79]	232	1		T7	1		T12	1		T29	1
valid_sources[0x7a]	355	1		T7	1		T10	13		T21	1
valid_sources[0x7b]	306	1		T6	1		T21	3		T12	10
valid_sources[0x7c]	635	1		T7	2		T20	8		T21	1
valid_sources[0x7d]	269	1		T6	1		T7	1		T28	3
valid_sources[0x7e]	346	1		T21	2		T27	2		T22	10
valid_sources[0x7f]	371	1		T10	11		T29	1		T22	8
valid_sources[0x80]	343	1		T7	2		T20	1		T12	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

18734

1

T1

1

T2

1

T3

2

values[0x0]

all_enables

biggest_size

15457

1

T3

1

T5

1

T6

49

values[0x1]

all_enables

biggest_size

14298

1

T1

1

T6

44

T7

53