Summary for Variable cp_num_num_enable_bytes
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_num_num_enable_bytes
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
partial |
52695 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T4 |
2 |
full_word |
49552 |
1 |
|
T1 |
2 |
|
T2 |
1 |
|
T3 |
3 |
Summary for Variable cp_tl_intg_err_type
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
4 |
0 |
4 |
100.00 |
Automatically Generated Bins for cp_tl_intg_err_type
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
102077 |
1 |
|
T1 |
3 |
|
T2 |
3 |
|
T3 |
3 |
auto[TlIntgErrCmd] |
66 |
1 |
|
T22 |
2 |
|
T49 |
4 |
|
T46 |
6 |
auto[TlIntgErrData] |
51 |
1 |
|
T22 |
6 |
|
T49 |
3 |
|
T46 |
3 |
auto[TlIntgErrBoth] |
53 |
1 |
|
T22 |
2 |
|
T49 |
3 |
|
T46 |
1 |
Summary for Variable cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_write
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53559 |
1 |
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
2 |
auto[1] |
48688 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Cross cr_all
Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
16 |
2 |
14 |
87.50 |
2 |
Automatically Generated Cross Bins for cr_all
Uncovered bins
cp_tl_intg_err_type | cp_num_num_enable_bytes | cp_write | COUNT | AT LEAST | NUMBER |
[auto[TlIntgErrData] , auto[TlIntgErrBoth]] |
[full_word] |
[auto[0]] |
-- |
-- |
2 |
Covered bins
cp_tl_intg_err_type | cp_num_num_enable_bytes | cp_write | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
partial |
auto[0] |
34545 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
1 |
auto[TlIntgErrNone] |
partial |
auto[1] |
17986 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T6 |
3 |
auto[TlIntgErrNone] |
full_word |
auto[0] |
18937 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
2 |
auto[TlIntgErrNone] |
full_word |
auto[1] |
30609 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T5 |
1 |
auto[TlIntgErrCmd] |
partial |
auto[0] |
32 |
1 |
|
T22 |
1 |
|
T46 |
2 |
|
T47 |
2 |
auto[TlIntgErrCmd] |
partial |
auto[1] |
31 |
1 |
|
T22 |
1 |
|
T49 |
4 |
|
T46 |
3 |
auto[TlIntgErrCmd] |
full_word |
auto[0] |
1 |
1 |
|
T69 |
1 |
|
- |
- |
|
- |
- |
auto[TlIntgErrCmd] |
full_word |
auto[1] |
2 |
1 |
|
T46 |
1 |
|
T70 |
1 |
|
- |
- |
auto[TlIntgErrData] |
partial |
auto[0] |
25 |
1 |
|
T22 |
2 |
|
T49 |
1 |
|
T46 |
2 |
auto[TlIntgErrData] |
partial |
auto[1] |
25 |
1 |
|
T22 |
4 |
|
T49 |
2 |
|
T46 |
1 |
auto[TlIntgErrData] |
full_word |
auto[1] |
1 |
1 |
|
T71 |
1 |
|
- |
- |
|
- |
- |
auto[TlIntgErrBoth] |
partial |
auto[0] |
19 |
1 |
|
T22 |
1 |
|
T49 |
1 |
|
T47 |
2 |
auto[TlIntgErrBoth] |
partial |
auto[1] |
32 |
1 |
|
T22 |
1 |
|
T49 |
1 |
|
T46 |
1 |
auto[TlIntgErrBoth] |
full_word |
auto[1] |
2 |
1 |
|
T49 |
1 |
|
T47 |
1 |
|
- |
- |