Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
73.90	83.72	36.90	93.90		55.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	696892	12123	0	0
ep_in_enable_rd_A	696892	1859	0	0
ep_out_enable_rd_A	696892	1730	0	0
in_iso_rd_A	696892	1528	0	0
intr_enable_rd_A	696892	2148	0	0
out_iso_rd_A	696892	1394	0	0
phy_config_rd_A	696892	771	0	0
phy_pins_drive_rd_A	696892	1505	0	0
rxenable_setup_rd_A	696892	1640	0	0
set_nak_out_rd_A	696892	1479	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696892	12123	0	0
T6	2190	1	0	0
T11	1584	2	0	0
T12	3555	10	0	0
T13	8563	0	0	0
T14	2445	2	0	0
T15	1476	0	0	0
T16	0	2	0	0
T17	0	495	0	0
T18	2425	0	0	0
T22	12217	1	0	0
T31	2223	0	0	0
T46	0	2	0	0
T47	0	2	0	0
T49	6342	1	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696892	1859	0	0
T7	2215	7	0	0
T17	8114	0	0	0
T21	4864	38	0	0
T41	3487	0	0	0
T42	1566	0	0	0
T43	2573	4	0	0
T44	13689	0	0	0
T45	1722	0	0	0
T46	15953	298	0	0
T50	0	285	0	0
T52	10732	142	0	0
T55	0	3	0	0
T63	0	2	0	0
T64	0	6	0	0
T65	0	3	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696892	1730	0	0
T7	2215	4	0	0
T17	8114	0	0	0
T21	4864	16	0	0
T41	3487	0	0	0
T42	1566	0	0	0
T43	2573	35	0	0
T44	13689	0	0	0
T45	1722	0	0	0
T46	15953	321	0	0
T50	0	312	0	0
T52	10732	115	0	0
T55	0	6	0	0
T63	0	9	0	0
T64	0	3	0	0
T65	0	9	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696892	1528	0	0
T7	2215	9	0	0
T17	8114	0	0	0
T21	4864	24	0	0
T41	3487	0	0	0
T42	1566	0	0	0
T43	2573	3	0	0
T44	13689	0	0	0
T45	1722	0	0	0
T46	15953	238	0	0
T50	0	236	0	0
T52	10732	122	0	0
T55	0	38	0	0
T63	0	6	0	0
T64	0	2	0	0
T65	0	8	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696892	2148	0	0
T7	2215	2	0	0
T9	5075	26	0	0
T13	8563	0	0	0
T19	0	17	0	0
T21	4864	7	0	0
T22	12217	0	0	0
T24	1579	17	0	0
T26	1318	16	0	0
T31	2223	0	0	0
T43	0	45	0	0
T46	0	220	0	0
T49	6342	0	0	0
T50	0	201	0	0
T52	0	135	0	0
T66	1237	0	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696892	1394	0	0
T17	8114	0	0	0
T21	4864	3	0	0
T41	3487	0	0	0
T42	1566	0	0	0
T43	2573	39	0	0
T44	13689	0	0	0
T45	1722	0	0	0
T46	15953	132	0	0
T47	13688	0	0	0
T50	0	264	0	0
T52	10732	134	0	0
T55	0	70	0	0
T63	0	6	0	0
T64	0	10	0	0
T65	0	4	0	0
T67	0	115	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696892	771	0	0
T7	2215	1	0	0
T17	8114	0	0	0
T21	4864	33	0	0
T23	0	2	0	0
T41	3487	0	0	0
T42	1566	0	0	0
T43	2573	8	0	0
T44	13689	0	0	0
T45	1722	0	0	0
T46	15953	83	0	0
T50	0	143	0	0
T52	10732	126	0	0
T55	0	7	0	0
T64	0	8	0	0
T65	0	11	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696892	1505	0	0
T7	2215	1	0	0
T17	8114	0	0	0
T21	4864	9	0	0
T41	3487	0	0	0
T42	1566	0	0	0
T43	2573	0	0	0
T44	13689	0	0	0
T45	1722	0	0	0
T46	15953	235	0	0
T50	0	229	0	0
T52	10732	156	0	0
T55	0	6	0	0
T63	0	7	0	0
T64	0	4	0	0
T65	0	3	0	0
T67	0	243	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696892	1640	0	0
T7	2215	4	0	0
T17	8114	0	0	0
T21	4864	28	0	0
T41	3487	0	0	0
T42	1566	0	0	0
T43	2573	0	0	0
T44	13689	0	0	0
T45	1722	0	0	0
T46	15953	311	0	0
T50	0	291	0	0
T52	10732	129	0	0
T55	0	58	0	0
T63	0	3	0	0
T65	0	4	0	0
T67	0	274	0	0
T68	0	14	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696892	1479	0	0
T7	2215	1	0	0
T17	8114	1	0	0
T41	3487	0	0	0
T42	1566	0	0	0
T43	2573	7	0	0
T44	13689	0	0	0
T45	1722	0	0	0
T46	15953	242	0	0
T47	13688	0	0	0
T50	0	115	0	0
T52	10732	152	0	0
T55	0	40	0	0
T63	0	1	0	0
T64	0	6	0	0
T65	0	6	0	0