Line Coverage for Module :
prim_reg_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
ALWAYS | 60 | 6 | 6 | 100.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
ALWAYS | 104 | 9 | 9 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
|
|
|
MISSING_ELSE |
74 |
1 |
1 |
98 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
139 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
187 |
1 |
1 |
Cond Coverage for Module :
prim_reg_cdc
| Total | Covered | Percent |
Conditions | 14 | 10 | 71.43 |
Logical | 14 | 10 | 71.43 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T10,T20,T21 |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T10,T20,T21 |
1 | 1 | Covered | T10,T20,T21 |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T10,T20,T21 |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T10,T20,T21 |
1 | 1 | Covered | T10,T20,T21 |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
Branch Coverage for Module :
prim_reg_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
60 |
4 |
4 |
100.00 |
IF |
104 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_src_ni))
-2-: 62 if (src_req)
-3-: 64 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T10,T20,T21 |
0 |
0 |
1 |
Covered |
T10,T20,T21 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 104 if ((!rst_src_ni))
-2-: 107 if (src_req)
-3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T10,T20,T21 |
0 |
0 |
1 |
Covered |
T10,T20,T21 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_reg_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1393784 |
6925 |
0 |
0 |
T10 |
2909 |
114 |
0 |
0 |
T12 |
3555 |
41 |
0 |
0 |
T20 |
2707 |
102 |
0 |
0 |
T21 |
4864 |
103 |
0 |
0 |
T22 |
12217 |
71 |
0 |
0 |
T27 |
1706 |
8 |
0 |
0 |
T28 |
1620 |
28 |
0 |
0 |
T29 |
1523 |
13 |
0 |
0 |
T30 |
3215 |
14 |
0 |
0 |
T31 |
2223 |
28 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
452570 |
395300 |
0 |
0 |
T1 |
2770 |
1164 |
0 |
0 |
T2 |
4028 |
2194 |
0 |
0 |
T3 |
3686 |
2164 |
0 |
0 |
T4 |
6274 |
3190 |
0 |
0 |
T5 |
4392 |
2704 |
0 |
0 |
T6 |
1368 |
1164 |
0 |
0 |
T7 |
1104 |
972 |
0 |
0 |
T8 |
6358 |
6210 |
0 |
0 |
T9 |
208 |
62 |
0 |
0 |
T10 |
2300 |
1924 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1393784 |
464 |
0 |
0 |
T10 |
2909 |
14 |
0 |
0 |
T12 |
3555 |
2 |
0 |
0 |
T20 |
2707 |
15 |
0 |
0 |
T21 |
4864 |
11 |
0 |
0 |
T22 |
12217 |
10 |
0 |
0 |
T27 |
1706 |
1 |
0 |
0 |
T28 |
1620 |
2 |
0 |
0 |
T29 |
1523 |
2 |
0 |
0 |
T30 |
3215 |
1 |
0 |
0 |
T31 |
2223 |
1 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1393784 |
1336194 |
0 |
0 |
T1 |
13316 |
11716 |
0 |
0 |
T2 |
8410 |
6684 |
0 |
0 |
T3 |
8432 |
6644 |
0 |
0 |
T4 |
14344 |
11324 |
0 |
0 |
T5 |
10040 |
8464 |
0 |
0 |
T6 |
4380 |
4248 |
0 |
0 |
T7 |
4430 |
4304 |
0 |
0 |
T8 |
14536 |
14374 |
0 |
0 |
T9 |
10150 |
9980 |
0 |
0 |
T10 |
5818 |
5524 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 17 | 14 | 82.35 |
CONT_ASSIGN | 54 | 0 | 0 | |
ALWAYS | 60 | 5 | 4 | 80.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
ALWAYS | 104 | 7 | 5 | 71.43 |
CONT_ASSIGN | 139 | 0 | 0 | |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
|
unreachable |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
|
unreachable |
64 |
1 |
1 |
65 |
0 |
1 |
|
|
|
MISSING_ELSE |
74 |
1 |
1 |
98 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
112 |
|
unreachable |
113 |
|
unreachable |
114 |
1 |
1 |
123 |
0 |
1 |
124 |
0 |
1 |
|
|
|
MISSING_ELSE |
139 |
|
unreachable |
144 |
1 |
1 |
145 |
1 |
1 |
187 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc
| Total | Covered | Percent |
Conditions | 13 | 4 | 30.77 |
Logical | 13 | 4 | 30.77 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
Branch Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
4 |
66.67 |
IF |
60 |
3 |
2 |
66.67 |
IF |
104 |
3 |
2 |
66.67 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_src_ni))
-2-: 62 if (src_req)
-3-: 64 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Unreachable |
|
0 |
0 |
1 |
Not Covered |
|
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 104 if ((!rst_src_ni))
-2-: 107 if (src_req)
-3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Unreachable |
|
0 |
0 |
1 |
Not Covered |
|
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
696892 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
226285 |
197650 |
0 |
0 |
T1 |
1385 |
582 |
0 |
0 |
T2 |
2014 |
1097 |
0 |
0 |
T3 |
1843 |
1082 |
0 |
0 |
T4 |
3137 |
1595 |
0 |
0 |
T5 |
2196 |
1352 |
0 |
0 |
T6 |
684 |
582 |
0 |
0 |
T7 |
552 |
486 |
0 |
0 |
T8 |
3179 |
3105 |
0 |
0 |
T9 |
104 |
31 |
0 |
0 |
T10 |
1150 |
962 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
696892 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
696892 |
668097 |
0 |
0 |
T1 |
6658 |
5858 |
0 |
0 |
T2 |
4205 |
3342 |
0 |
0 |
T3 |
4216 |
3322 |
0 |
0 |
T4 |
7172 |
5662 |
0 |
0 |
T5 |
5020 |
4232 |
0 |
0 |
T6 |
2190 |
2124 |
0 |
0 |
T7 |
2215 |
2152 |
0 |
0 |
T8 |
7268 |
7187 |
0 |
0 |
T9 |
5075 |
4990 |
0 |
0 |
T10 |
2909 |
2762 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
ALWAYS | 60 | 6 | 6 | 100.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
ALWAYS | 104 | 9 | 9 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
|
|
|
MISSING_ELSE |
74 |
1 |
1 |
98 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
139 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
187 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T10,T20,T21 |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T10,T20,T21 |
1 | 1 | Covered | T10,T20,T21 |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T10,T20,T21 |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T10,T20,T21 |
1 | 1 | Covered | T10,T20,T21 |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
60 |
4 |
4 |
100.00 |
IF |
104 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_src_ni))
-2-: 62 if (src_req)
-3-: 64 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T10,T20,T21 |
0 |
0 |
1 |
Covered |
T10,T20,T21 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 104 if ((!rst_src_ni))
-2-: 107 if (src_req)
-3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T10,T20,T21 |
0 |
0 |
1 |
Covered |
T10,T20,T21 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
696892 |
6925 |
0 |
0 |
T10 |
2909 |
114 |
0 |
0 |
T12 |
3555 |
41 |
0 |
0 |
T20 |
2707 |
102 |
0 |
0 |
T21 |
4864 |
103 |
0 |
0 |
T22 |
12217 |
71 |
0 |
0 |
T27 |
1706 |
8 |
0 |
0 |
T28 |
1620 |
28 |
0 |
0 |
T29 |
1523 |
13 |
0 |
0 |
T30 |
3215 |
14 |
0 |
0 |
T31 |
2223 |
28 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
226285 |
197650 |
0 |
0 |
T1 |
1385 |
582 |
0 |
0 |
T2 |
2014 |
1097 |
0 |
0 |
T3 |
1843 |
1082 |
0 |
0 |
T4 |
3137 |
1595 |
0 |
0 |
T5 |
2196 |
1352 |
0 |
0 |
T6 |
684 |
582 |
0 |
0 |
T7 |
552 |
486 |
0 |
0 |
T8 |
3179 |
3105 |
0 |
0 |
T9 |
104 |
31 |
0 |
0 |
T10 |
1150 |
962 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
696892 |
464 |
0 |
0 |
T10 |
2909 |
14 |
0 |
0 |
T12 |
3555 |
2 |
0 |
0 |
T20 |
2707 |
15 |
0 |
0 |
T21 |
4864 |
11 |
0 |
0 |
T22 |
12217 |
10 |
0 |
0 |
T27 |
1706 |
1 |
0 |
0 |
T28 |
1620 |
2 |
0 |
0 |
T29 |
1523 |
2 |
0 |
0 |
T30 |
3215 |
1 |
0 |
0 |
T31 |
2223 |
1 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
696892 |
668097 |
0 |
0 |
T1 |
6658 |
5858 |
0 |
0 |
T2 |
4205 |
3342 |
0 |
0 |
T3 |
4216 |
3322 |
0 |
0 |
T4 |
7172 |
5662 |
0 |
0 |
T5 |
5020 |
4232 |
0 |
0 |
T6 |
2190 |
2124 |
0 |
0 |
T7 |
2215 |
2152 |
0 |
0 |
T8 |
7268 |
7187 |
0 |
0 |
T9 |
5075 |
4990 |
0 |
0 |
T10 |
2909 |
2762 |
0 |
0 |